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TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

HSIN-CHU, TW

1. 20090283841 SCHOTTKY DEVICE - integrated circuit structure has a metal silicide layer formed on an n-type well region a p-type guard ring formed on the n-type well 11-19-2009
2. 20090271019 SYSTEM AND METHOD OF DEMAND AND CAPACITY MANAGEMENT 10-29-2009
3. 20090263214 FIXTURE FOR P-THROUGH SILICON VIA ASSEMBLY 10-22-2009
4. 20090233447 CONTROL WAFER RECLAMATION PROCESS - method of recycling a control wafer having a dielectric layer deposited thereon involves removing most of the 09-17-2009
5. 20090218693 LOW RESISTANCE HIGH RELIABILITY CONTACT VIA AND METAL LINE STRUCTURE FOR SEMICONDUCTOR DEVICE 09-03-2009
6. 20090200549 SEMICONDUCTOR DEVICE 08-13-2009
7. 20090188104 Method of Manufacturing a Coil Inductor - and a coil inductor are provided are provided 07-30-2009
8. 20090166817 EXTREME LOW-K DIELECTRIC FILM SCHEME FOR ADVANCED INTERCONNECTS 07-02-2009
9. 20090160024 VERTICAL RESISTORS AND BAND-GAP VOLTAGE REFERENCE CIRCUITS 06-25-2009
10. 20090157455 INSTRUCTION SYSTEM AND METHOD FOR EQUIPMENT PROBLEM SOLVING 06-18-2009
11. 20090140393 WAFER SCRIBE LINE STRUCTURE FOR IMPROVING IC RELIABILITY 06-04-2009
12. 20090140391 Seal Ring in Semiconductor Device - semiconductor device includes a first circuit, a first seal ring and at least one first notch 06-04-2009
13. 20090140383 METHOD OF CREATING SPIRAL INDUCTOR HAVING HIGH Q VALUE 06-04-2009
14. 20090124073 SEMICONDUCTOR DEVICE WITH BONDING PAD - method for forming a semiconductor device with a bonding pad is disclosed 05-14-2009
15. 20090101937 NOVEL METHOD FOR FOUR DIRECTION LOW CAPACITANCE ESD PROTECTION 04-23-2009
16. 20090081862 AIR GAP STRUCTURE DESIGN FOR ADVANCED INTEGRATED CIRCUIT TECHNOLOGY 03-26-2009
17. 20090067105 ESD PROTECTION CIRCUIT AND METHOD - system includes a driving device operating at first supply voltage V 03-12-2009
18. 20090058434 METHOD FOR MEASURING A PROPERTY OF INTERCONNECTIONS AND STRUCTURE FOR THE SAME 03-05-2009
19. 20090057902 METHOD AND STRUCTURE FOR INCREASED WIRE BOND DENSITY IN PACKAGES FOR SEMICONDUCTOR CHIPS 03-05-2009
20. 20090057741 Dram cell with enhanced capacitor area and the method of manufacturing the same 03-05-2009
21. 20090047796 Method of Manufacturing a Dielectric Layer having Plural High-K Films 02-19-2009
22. 20090039429 SOI MOSFET DEVICE WITH REDUCED POLYSILICON LOADING ON ACTIVE AREA 02-12-2009
23. 20090029547 NOVEL LADDER POLY ETCHING BACK PROCESS FOR WORD LINE POLY PLANARIZATION 01-29-2009
24. 20090026432 METHOD AND STRUCTURE FOR UNIFORM CONTACT AREA BETWEEN HEATER AND PHASE CHANGE MATERIAL IN PCRAM DEVICE 01-29-2009
25. 20090004851 SALICIDATION PROCESS USING ELECTROLESS PLATING TO DEPOSIT METAL AND INTRODUCE DOPANT IMPURITIES 01-01-2009
26. 20080318494 CHEMICAL MECHANICAL PLANARIZATION METHODS AND APPARATUS 12-25-2008
27. 20080311716 METHODS FOR FORMING FIELD EFFECT TRANSISTORS AND EPI-SUBSTRATE 12-18-2008
28. 20080308932 SEMICONDUCTOR PACKAGE STRUCTURES - semiconductor structure includes a plurality of solder structures between a first substrate and a second substrate 12-18-2008
29. 20080308782 SEMICONDUCTOR MEMORY STRUCTURES - semiconductor structure includes a transistor over a substrate the transistor comprising a gate and a contact region 12-18-2008
30. 20080305639 DUAL DAMASCENE PROCESS - method and system for forming dual damascene structures in a semiconductor package 12-11-2008
31. 20080305601 METHOD FOR FORMING SEMICONDUCTOR DEVICE USING MULTI-FUNCTIONAL SACRIFICIAL DIELECTRIC LAYER 12-11-2008
32. 20080304943 SUBSTRATE CARRIER AND FACILITY INTERFACE AND APPARATUS INCLUDING SAME 12-11-2008
33. 20080299769 SEMICONDUCTOR FABRICATION METHOD SUITABLE FOR MEMS 12-04-2008
34. 20080299723 METHODS FOR FORMING CAPACITOR STRUCTURES 12-04-2008
35. 20080298933 SUBSTRATE CARRIER, PORT APPARATUS AND FACILITY INTERFACE AND APPARATUS INCLUDING SAME 12-04-2008
36. 20080296571 MULTI-PROJECT WAFER AND METHOD OF MAKING SAME 12-04-2008
37. 20080296570 SEMICONDUCTOR DEVICE 12-04-2008
38. 20080295874 WET PROCESSING APPARATUSES - semiconductor apparatus includes a first tank configured to accommodate a first fluid 12-04-2008
39. 20080290467 SEMICONDUCTOR MEMORY STRUCTURES - semiconductor structure includes a first conductive layer coupled to a transistor 11-27-2008
40. 20080290416 HIGH-K METAL GATE DEVICES AND METHODS FOR MAKING THE SAME 11-27-2008
41. 20080281536 SEMICONDUCTOR CP (CIRCUIT PROBE) TEST MANAGEMENT SYSTEM AND METHOD 11-13-2008
42. 20080280393 METHODS FOR FORMING PACKAGE STRUCTURES - method for forming a semiconductor structure includes forming a first connector over at least one pad of a 11-13-2008
43. 20080277806 SEMICONDUCTOR WAFER WITH ASSISTING DICING STRUCTURE AND DICING METHOD THEREOF 11-13-2008
44. 20080277797 INTERCONNECT STRUCTURES - semiconductor structure includes a first dielectric layer over a substrate 11-13-2008
45. 20080277745 FIN FILLED EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME 11-13-2008
46. 20080268602 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 10-30-2008
47. 20080261410 METHOD FOR TREATING BASE OXIDE TO IMPROVE HIGH-K MATERIAL DEPOSITION 10-23-2008
48. 20080258227 STRAINED SPACER DESIGN FOR PROTECTING HIGH-K GATE DIELECTRIC 10-23-2008
49. 20080254600 METHODS FOR FORMING INTERCONNECT STRUCTURES 10-16-2008
50. 20080254588 METHODS FOR FORMING TRANSISTORS WITH HIGH-K DIELECTRIC LAYERS AND TRANSISTORS FORMED THEREFROM 10-16-2008
51. 20080252361 ELECTRICAL FUSES WITH REDUNDANCY - The present disclosure provides an electrical fuse cell with redundancy features and the method for operating the 10-16-2008
52. 20080251889 SEMICONDUCTOR DEVICE 10-16-2008
53. 20080250182 SIP (SYSTEM IN PACKAGE) DESIGN SYSTEMS AND METHODS 10-09-2008
54. 20080246152 SEMICONDUCTOR DEVICE WITH BONDING PAD - semiconductor device with a bonding pad is provided 10-09-2008
55. 20080245479 ETCHING SYSTEM 10-09-2008
56. 20080242039 METHOD OF ENHANCING DOPANT ACTIVATION WITHOUT SUFFERING ADDITIONAL DOPANT DIFFUSION 10-02-2008
57. 20080237703 HIGH VOLTAGE SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME 10-02-2008
58. 20080233710 METHODS FOR FORMING SINGLE DIES WITH MULTI-LAYER INTERCONNECT STRUCTURES AND STRUCTURES FORMED THEREFROM 09-25-2008
59. 20080231393 STRUCTURE DESIGN FOR MINIMIZING ON-CHIP INTERCONNECT INDUCTANCE 09-25-2008
60. 20080229161 MEMORY PRODUCTS AND MANUFACTURING METHODS THEREOF 09-18-2008
61. 20080227260 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH THIN GATE SPACER 09-18-2008
62. 20080225617 METHOD FOR HIGH SPEED SENSING FOR EXTRA LOW VOLTAGE DRAM 09-18-2008
63. 20080225616 METHOD FOR INCREASING RETENTION TIME IN DRAM 09-18-2008
64. 20080223724 APPARATUSES FOR ELECTROCHEMICAL DEPOSITION, CONDUCTIVE LAYER, AND FABRICATION METHODS THEREOF 09-18-2008
65. 20080218931 SYSTEM FOR DECHARGING A WAFER OR SUBSTRATE AFTER DECHUCKING FROM AN ELECTROSTATIC CHUCK 09-11-2008
66. 20080211106 VIA/CONTACT AND DAMASCENE STRUCTURES AND MANUFACTURING METHODS THEREOF 09-04-2008
67. 20080209381 SHALLOW TRENCH ISOLATION DUMMY PATTERN AND LAYOUT METHOD USING THE SAME 08-28-2008
68. 20080197473 CHIP HOLDER WITH WAFER LEVEL REDISTRIBUTION LAYER 08-21-2008
69. 20080197410 HIGH VOLTAGE DEVICE WITH LOW ON-RESISTANCE 08-21-2008