INFINEON TECHNOLOGIES AUSTRIA AG Patent applications |
Patent application number | Title | Published |
20160064547 | Semiconductor Device with Field Electrode Structures in a Cell Area and Termination Structures in an Edge Area - A semiconductor device includes field electrode structures regularly arranged in lines in a cell area and forming a first portion of a regular pattern. Termination structures are formed in an inner edge area surrounding the cell area, wherein at least portions of the termination structures form a second portion of the regular pattern. Cell mesas separate neighboring ones of the field electrode structures from each other in the cell area and include first portions of a drift zone, wherein a voltage applied to a gate electrode controls a current flow through the cell mesas. At least one doped region forms a homojunction with the drift zone in the inner edge area. | 03-03-2016 |
20160035862 | FIELD PLATE TRENCH TRANSISTOR AND METHOD FOR PRODUCING IT - A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials. | 02-04-2016 |
20150364586 | INSULATED GATE BIPOLAR TRANSISTOR - A semiconductor device is disclosed. One embodiment provides a cell area and a junction termination area at a first side of a semiconductor zone of a first conductivity type. At least one first region of a second conductivity type is formed at a second side of the semiconductor zone. The at least one first region is opposed to the cell area region. At least one second region of the second conductivity type is formed at the second side of the semiconductor zone. The at least one second region is opposed to the cell area region and has a lateral dimension smaller than the at least first region. | 12-17-2015 |
20150349632 | CONTROLLING A PAIR OF SWITCHES - Devices and methods are provided where a feedback is provided from a control terminal of a first switch, and a second switch is controlled based on the feedback. | 12-03-2015 |
20150346749 | System and Method for a Linear Voltage Regulator - In accordance with an embodiment, a method of operating a power supply includes measuring an output signal of the power supply, determining a control voltage based on the measured output signal, and determining whether a supply voltage of a voltage follower circuit is greater than a first threshold. When the supply voltage of the voltage follower circuit is greater than the first threshold, the control voltage is applied to an input of the voltage follower circuit and an output of the voltage follower circuit is applied to a control node of an output transistor in a first mode. When the supply voltage of the voltage follower circuit is not greater than the first threshold, the voltage follower circuit is shut down and the control voltage is applied to the control node of the output transistor in a second mode. | 12-03-2015 |
20150341027 | CIRCUIT ARRANGEMENT AND METHOD FOR GENERATING A DRIVE SIGNAL FOR A TRANSISTOR - Disclosed is a circuit arrangement for generating a drive signal for a transistor. In one embodiment, the circuit arrangement includes a control circuit that receives a switching signal, a driver circuit that outputs a drive signal, and at least one transmission channel. The control circuit transmits, depending on the switching signal for each switching operation of the transistor, switching information and switching parameter information via the transmission channel to the driver circuit. The driver circuit generates the drive signal depending on the switching information and depending on the switching parameter information. | 11-26-2015 |
20150311803 | ENHANCED POWER FACTOR CORRECTION - A power converter is described that includes a switch. The power converter may also include a controller that controls the switch. The controller may be configured to ascertain a first parameter. Additionally, the controller may be configured to ascertain a second parameter. The controller may dynamically modulate duty cycle of the switch based on the first parameter and the second parameter in addition and independent of the control loop. | 10-29-2015 |
20150295494 | System and Method for a Switched-Mode Power Supply - In accordance with an embodiment, a method of operating a switched-mode power supply includes receiving power from an input node via a first transistor, providing a first portion of the received power to a load via a switching transistor having a first terminal coupled to the first transistor and a second terminal coupled to the load via a series resistor and a series inductor, measuring a current through the load, measuring comprising monitoring a voltage across the series resistor; and controlling an average current through the load by switching on and switching off the switching transistor according to the measured current. | 10-15-2015 |
20150280696 | CIRCUIT FOR COMMON MODE REMOVAL FOR DC-COUPLED FRONT-END CIRCUITS - In one example, a method includes receiving a first differential signal including a first voltage signal and a second voltage signal, wherein the first differential signal includes a first common mode voltage; receiving a second common mode voltage. The method further includes determining, by a circuit, a second differential signal including a third voltage signal and a fourth voltage signal, wherein a difference between the third voltage signal and the fourth voltage signal is based on a difference between the first voltage signal and the second voltage signal, wherein the second differential signal includes the second common mode voltage. The method further includes outputting, substantially continuously, the second differential signal. | 10-01-2015 |
20150280584 | System and Method for a Switched-Mode Power Supply - In accordance with an embodiment, a method of operating a switched-mode power supply includes detecting a voltage decrease in a secondary winding of a transformer by detecting a first voltage transient using a sensor capacitively coupled to the secondary winding of the transformer. A secondary switch coupled to the secondary winding of the transformer is turned on based on when the first voltage transient is detected. | 10-01-2015 |
20150280574 | System and Method for a Switched-Mode Power Supply - In accordance with an embodiment, a method of operating a switched-mode power supply includes turning on a semiconductor switch coupled to a primary winding of a transformer for a first time period of a first cycle, turning off the semiconductor switch for a second time period of the first cycle, detecting a change in slew rate of a voltage at an output node of the semiconductor switch, determining a switch turn-on time based on detecting the change in the slew rate, and turning on the semiconductor switch at the determined switch turn-on time for a first time period of a second cycle. | 10-01-2015 |
20150280573 | System and Method for a Switched-Mode Power Supply - In accordance with an embodiment, a method of operating a switched-mode power supply includes synchronously rectifying a current in a secondary side of the switched-mode power supply by detecting a voltage drop of a secondary winding of a transformer and activating a semiconductor switch coupled to the secondary winding when the voltage drop is detected. The method also includes determining a digital signal transmitting the digital signal to a controller coupled to a primary winding of the transformer by switching the semiconductor switch in accordance with the digital signal | 10-01-2015 |
20150263100 | OPERATIONAL GALLIUM NITRIDE DEVICES - A power circuit is described that includes a semiconductor body having a common substrate and a Gallium Nitride (GaN) based substrate. The GaN based substrate includes one or more GaN devices adjacent to a front side of the common substrate. The common substrate is electrically coupled to a node of the power circuit. The node of the power circuit is at a particular potential that is equal to, or more negative than, a potential at one or more load terminals of the one or more GaN devices. | 09-17-2015 |
20150261248 | LINEAR HIGH SPEED TRACKING CURRENT SENSE SYSTEM WITH POSITIVE AND NEGATIVE CURRENT - In general, this disclosure describes linear tracking current sense systems having improved accuracy, bandwidth, and stability. An example device comprises a half bridge comprising a high side switch and a low side switch. The device further comprises a first second gain stage coupled to an operational transconductance amplifier (OTA) and the high side switch, wherein the first second gain stage is configured to sink or supply current to the high side switch from a first non-zero current. The device also comprises a second second gain stage coupled to the OTA and the low side switch, wherein the second second gain stage is configured to sink or supply current to the low side switch from a second non-zero current. | 09-17-2015 |
20150249393 | Interface Circuits for USB and Lighting Applications - In accordance with an embodiment of the present invention, a method of operating a power supply circuit includes receiving an input signal comprising a request for a target power supply voltage and/or current at an interface circuit at a secondary side of an adjustable power supply. The input signal is converted into a digital signal comprising the target power supply voltage and/or current. The digital signal is transmitted via a galavanically isolated signal path to a controller in a primary side of the adjustable power supply. | 09-03-2015 |
20150249354 | COMMUNICATION USING LOAD MODULATION - In one example, a method includes receiving, by a first device and from a second device, power via a power line of a cable connecting the first device to the second device, wherein receiving power comprises drawing, by the first device, current from the second device. The method may also include communicating, by the first device, with the second device via the power line, wherein communicating comprises adjusting, by the first device, the amount of current drawn by the first device. | 09-03-2015 |
20150249134 | Group III-Nitride-Based Enhancement Mode Transistor - A Group III-nitride-based enhancement mode transistor includes a multi-heterojunction fin structure. A first side face of the multi-heterojunction fin structure is covered by a p-type Group III-nitride layer. | 09-03-2015 |
20150249020 | SEMICONDUCTOR DEVICE WITH METAL CARRIER AND MANUFACTURING METHOD - Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of Al | 09-03-2015 |
20150248151 | COMMUNICATION OVER IDENTIFICATION LINE - In one example a method includes communicating, by a first device, with a second device via an identification (ID) line of a universal serial bus (USB) cable. A first connector of the USB cable may be attached to a USB connector of the first device. A second connector of the USB cable may be attached to a USB connector of the second device. The USB connector of the first device may include a bus voltage (V | 09-03-2015 |
20150243775 | NITRIDE SEMICONDUCTOR DEVICE - A semiconductor device is described. In one embodiment, the device includes a Group-III nitride channel layer and a Group-III nitride barrier layer on the Group-III nitride channel layer, wherein the Group-III nitride barrier layer includes a first portion and a second portion, the first portion having a thickness less than the second portion. A p-doped Group-III nitride gate layer section is arranged at least on the first portion of the Group-III nitride barrier layer and a gate contact formed on the p-doped Group-III nitride gate layer. | 08-27-2015 |
20150243592 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES HAVING A METALLISATION LAYER - A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallisation layer is formed on the second surface of the semiconductor substrate. The metallisation layer has a thickness which is greater than the device thickness. | 08-27-2015 |
20150242295 | TESTING USING COUPLING EMULATION - An apparatus and method associated with testing are disclosed, where a coupling between a device under test and at least one further device may be emulated. The coupling may be a bus. | 08-27-2015 |
20150230303 | UNIVERSAL INPUT AND WIDE OUTPUT FUNCTION FOR LIGHT EMITTING DIODE (LED) DRIVER - Techniques are described for controlling an amount of current flowing through one or more light-emitting-diodes (LEDs), without sensing input and/or output voltage, so that the amount of current flowing through the one or more LEDs is approximately equal to a target current level. The techniques provide for coarse and fine tuning of the amount of time a transistor, through which the current flows, is turned on to control the amount of current flowing through the one or more LEDs. | 08-13-2015 |
20150229204 | POWER FACTOR CORRECTOR TIMING CONTROL WITH EFFICIENT POWER FACTOR AND THD - Methods, devices, and integrated circuits are disclosed for controlling switch timing in a power factor correction timing switch. In one example, a device is configured to receive one or more indications of one or more power factor correction circuit parameters. The device is further configured to determine a switch delay time based at least in part on the one or more power factor correction circuit parameters. The device is further configured to generate an indication of a switch on time for the power factor correction timing switch, wherein the switch on time is based at least in part on the switch delay time. | 08-13-2015 |
20150207306 | DISTINGUISHING BETWEEN OVERLOAD AND OPEN LOAD IN OFF CONDITIONS - Techniques are described for determining whether a switch circuit experienced one of a latched overload condition and an open load with no input voltage condition. In the techniques, a first diagnostic signal is output if the switch circuit experienced the latched overload condition. Also, in the techniques, a second, different diagnostic signal is output if the switch circuit experienced the open load with no input voltage condition. | 07-23-2015 |
20150206820 | Electronic Component - An electronic component includes one or more semiconductor dice embedded in a first dielectric layer, means for a spreading heat in directions substantially parallel to a major surface of the one or more semiconductor dice embedded in a second dielectric layer and means for dissipating heat in directions substantially perpendicular to the major surface of the one or more semiconductor dice. | 07-23-2015 |
20150200725 | Lighting System Communication - A lighting system including a plurality of light modules is provided. Each of the light modules may be configured to emit visible light. At least one light module may be configured to communicate with another light module by modulating the emitted visible light with information that is to be communicated. The modulation of the visible light may be unnoticeable to the human eye. | 07-16-2015 |
20150195059 | MODULATOR DEVICE - Devices, chips and methods are provided which involve the use of either a first modulator path or a second modulator path depending on a level of a signal to be processed. | 07-09-2015 |
20150194836 | CABLE COMPENSATION BY ZERO-CROSSING COMPENSATION CURRENT AND RESISTOR - Methods, devices, and circuits are disclosed delivering a first level of output voltage to a rechargeable battery from a battery charger, the rechargeable battery is coupled to the battery charger by a charging cable. The methods, device, and circuits may further be disclosed applying, in response to an indication of an altered output voltage, a compensation current to one or more elements of the battery charger including a zero crossing (ZC) pin and a selected resistor, the selected resistor is defined by the charging cable coupling the battery charger to the rechargeable battery, and applying the compensation current to the ZC pin and the selected resistor causes an adjustment of the output voltage from the first level of output voltage to a second level of output voltage corresponding to the voltage drop from the impedance of the selected charging cable. | 07-09-2015 |
20150194377 | Chip arrangement and method of manufacturing the same - A chip arrangement is provided which comprises a carrier; and at least two chips arranged over the carrier; wherein a continuous insulating layer is arranged between the at least two chips and between the carrier and at least one of the at least two chips. | 07-09-2015 |
20150180362 | Full-Wave Rectifier - A full-wave rectifier is disclosed. In one embodiment the full-wave rectifier includes two input paths configured to receive an alternating input voltage, two output paths configured to provide a direct output voltage, and four switched-mode rectifying paths that are connected between each of the input paths and each of the output paths, wherein the switched mode rectifying paths are configured to connect a first input path to a first output path and a second input path to a second output path during a first half wave of the input voltage, and to connect the first input path to the second output path and the second input path to the first output path during a second half wave of the input voltage, and wherein the switched-mode rectifying paths include cascode circuits. | 06-25-2015 |
20150175467 | MOLD, METHOD FOR PRODUCING A MOLD, AND METHOD FOR FORMING A MOLD ARTICLE - Various embodiments provide a mold including a pyrolytic carbon film disposed at a surface of the mold. Various embodiments relate to using a low pressure chemical vapor deposition process (LPCVD) or using a physical vapor deposition (PVD) process in order to form a pyrolytic carbon film at a surface of a mold. | 06-25-2015 |
20150162828 | RECONFIGURABLE MULTIPHASE POWER STAGE FOR SWITCHED MODE CHARGERS - Methods, devices, and integrated circuits are disclosed for providing a buck converter charger in a multiphase buck converter topology comprising at least a first phase, a second phase, and an alternative charging switch, wherein the first phase includes a first high-side switch and a first low-side switch and the second phase includes a second high-side switch and a second low-side switch. The methods, devices, and integrated circuits may control at least one phase to operate as a boost converter, control at least one phase to operate as buck converter, and close the alternative charging switch in the multiphase buck converter topology to connect an alternative charging source to a system voltage output, the alternative charging switch coupled to the first phase between the first high-side switch and the first low-side switch. | 06-11-2015 |
20150162319 | Semiconductor Device Including Multiple Semiconductor Chips and a Laminate - A semiconductor device includes a laminate, a first semiconductor chip at least partly embedded in the laminate, a second semiconductor chip mounted on a first main surface of the laminate, and a first electrical contact arranged on the first main surface of the laminate. The second semiconductor chip is electrically coupled to the first electrical contact. | 06-11-2015 |
20150145486 | DIGITAL CONTROLLER FOR SWITCHED MODE POWER CONVERTER - In one example, a method includes receiving a voltage value and comparing the voltage value to a reference voltage value to determine a delta voltage value. The method may also include determining a reference current value based on the delta voltage value. The method may also include receiving a current value and comparing the current value to the reference current value to determine a delta current value. The method may also include determining a threshold value based on the delta current value, where the threshold value is used to define a control signal that controls a power converter. | 05-28-2015 |
20150145111 | Electronic component with electronic chip between redistribution structure and mounting structure - An electronic component which comprises an electrically conductive mounting structure, an electronic chip on the mounting structure, an electrically conductive redistribution structure on the electronic chip, and a periphery connection structure electrically coupled to the redistribution structure and being configured for connecting the electronic component to an electronic periphery, wherein at least one of the electrically conductive mounting structure and the electrically conductive redistribution structure comprises electrically conductive inserts in an electrically insulating matrix. | 05-28-2015 |
20150097544 | System and Method for Controlling a Power Supply - In accordance with an embodiment, a controller for a switched mode power supply includes an average current comparator that determines whether an average current within the switched mode power supply is below a current threshold, and a switch signal generation circuit coupled to the average current comparator having switch signal outputs configured to be coupled to a switching circuit of the switched mode power supply. The switch signal generation circuit produces a first switching pattern in a first mode of operation and produces a second switching pattern a second mode of operation. When the average current comparator determines that the average current is below the current threshold, the switch signal generation circuit is operated in a first mode, and when the average current comparator determines that the average current is not below the current threshold, the switch signal generation circuit is operated in a second mode. | 04-09-2015 |
20150092375 | Transistor arrangement with semiconductor chips between two substrates - An electronic device comprising a first substrate, a second substrate, a first semiconductor chip comprising a transistor, comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, and a second semiconductor chip comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, wherein the first semiconductor chip comprises a via electrically coupling a first transistor terminal at its first mounting surface with a second transistor terminal at its second mounting surface. | 04-02-2015 |
20150091452 | Converter Circuit Arrangement and Conversion Method - A converter circuit arrangement is provided, including a converter switch controller, a converter switch, a load circuit interface and an inductor. The converter switch controller may include a control input. The converter switch may be coupled between a first power supply potential and the control input. The inductor may be coupled between a second power supply potential and the load circuit interface. The load circuit interface may be coupled between the control input and the inductor. | 04-02-2015 |
20150077079 | MULTIPHASE BUCK CONVERTER WITH DYNAMIC PHASE FIRING - Methods, devices, and circuits are disclosed for a multiphase buck converter with dynamic phase firing that moderates phase output current. In one example, a method includes evaluating a current of a first phase output of the multiphase buck converter. The method further includes, in response to the current of the first phase output not being higher than a current threshold, applying one or more pulses from a first duty cycle signal to the first phase output. The method further includes, in response to the current of the first phase output being higher than the current threshold, applying one or more pulses from the first duty cycle signal to a second phase output. | 03-19-2015 |
20150076664 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE - One embodiment describes a method of manufacturing a semiconductor device. Here, impurities are implanted into a semiconductor body via a first side of the semiconductor body. Thereafter, a drift zone layer on the first side of the semiconductor body is formed. The following is an ablation of the semiconductor body from a second side of the semiconductor body and up to pn junction defined by impurities. | 03-19-2015 |
20150069990 | CURRENT ESTIMATION FOR A CONVERTER - A embodiment relates to a current estimation circuitry for a converter comprising: an integrator for integrating a voltage across an inductor of the converter; a current sense unit for obtaining a signal that is associated with the current flowing through at least one of the electronic switches of the converter; and a control unit for adjusting at least two parameters of the integrator based on comparing the output of the integrator with the signal provided by the current sense unit. | 03-12-2015 |
20150055258 | DRIVING CIRCUIT FOR AN ELECTRIC MOTOR - In various embodiments a circuit arrangement is provided, having a bridge circuit including at least two switches connected in series; a bridge node which may provide a phase voltage arranged between the at least two switches; an electric motor having at least one phase winding coupled with the bridge node; a decoupling switch; a controller, wherein in an error case the controller may be configured to switch off the at least two switches, to determine whether a predefined condition is satisfied, and to one of delayed switching off the decoupling switch; and switching off the at least two switches and the decoupling switch simultaneously, depending upon whether the predefined condition is satisfied; wherein the controller may determine that the predefined condition is satisfied when the decoupling switch may be switched off without damage from the current applied to it when the at least two switches are switched off. | 02-26-2015 |
20150048678 | MULTI-FUNCTION PIN FOR LIGHT EMITTING DIODE (LED) DRIVER - Techniques are described for a multi-function pin of a light emitting diode (LED) driver. The techniques utilize this multi-function pin for switching current that flows through one or more LEDs, as well as for charging the power supply of the LED driver. The techniques further utilize this multi-function pin to determine whether the voltage at an external transistor is beginning to oscillate, and utilize this multi-function pin to determine whether the current through the one or more LEDs has fully dissipated to an amplitude of zero. | 02-19-2015 |
20150048677 | MULTI-FUNCTION PIN FOR LIGHT EMITTING DIODE (LED) DRIVER - Techniques are described for a multi-function pin of a light emitting diode (LED) driver. The techniques utilize this multi-function pin for switching current that flows through one or more LEDs, as well as for charging the power supply of the LED driver. The techniques further utilize this multi-function pin to determine whether the voltage at an external transistor is beginning to oscillate, and utilize this multi-function pin to determine whether the current through the one or more LEDs has fully dissipated to an amplitude of zero. | 02-19-2015 |
20150043116 | HIGH-VOLTAGE SEMICONDUCTOR SWITCH AND METHOD FOR SWITCHING HIGH VOLTAGES - A high voltage semiconductor switch includes a first field-effect transistor having a source, a drain and a gate, and being adapted for switching a voltage at a rated high-voltage level, the first field-effect transistor being a normally-off enhancement-mode transistor, a second field-effect transistor having a source, a drain and a gate, connected in series to the first field-effect transistor, the second field-effect transistor being a normally-on depletion-mode transistor; and a control unit connected to the drain of the first field-effect transistor and to the gate of the second field-effect transistor and being operable for blocking the second field-effect transistor if a drain-source voltage across the first field-effect transistor exceeds the rated high-voltage level. | 02-12-2015 |
20150036403 | System and Method for a Power Converter - In accordance with a preferred embodiment of the present invention, an inverter circuit includes a direct current (DC)-to-DC power converter configured to receive an input energy from a device via a first input terminal and a second input terminal, where the DC-to-DC power converter is configured to convert a first portion of the input energy to a DC energy. The inverter circuit also includes an inverter stage coupled to an output of the DC-to-DC power converter, and is connected to the first input terminal of the DC-to-DC power converter and the second input terminal of the DC-to-DC power converter, where the inverter stage is configured to convert a second portion of the input energy to a first output energy. | 02-05-2015 |
20150035581 | SWITCH CIRCUIT ARRANGEMENTS AND METHOD FOR POWERING A DRIVER CIRCUIT - In various embodiment, a switch circuit arrangement is provided. The switch circuit arrangement may include a switch circuit, a driver circuit and a supply circuit. The driver circuit may be configured to control the switch circuit. The supply circuit may be configured to power the driver circuit. The supply circuit may include a first circuit configured to modify an output impedance of the supply circuit to have a first impedance when the driver circuit controls the switch circuit to be in a conducting state and to have a second impedance when the driver circuit controls the switch circuit to change from a non-conducting state to the conducting state. | 02-05-2015 |
20150035048 | A SUPPER JUNCTION STRUCTURE INCLUDES A THICKNESS OF FIRST AND SECOND SEMICONDUCTOR REGIONS GRADUALLY CHANGED FROM A TRANSISTOR AREA INTO A TERMINATION AREA - A super junction semiconductor device includes a super junction structure including first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction. Each one of the first areas includes a first semiconductor region of a first conductivity type. Each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type. A width w | 02-05-2015 |
20150034995 | SEMICONDUCTOR DEVICE WITH COMBINED PASSIVE DEVICE ON CHIP BACK SIDE - Semiconductor chips are described that combine a semiconductor device and a capacitor onto a single substrate such that the semiconductor device and the capacitor are electrically isolated from each other. In one example, a semiconductor chip includes a substrate having a first side and a second side, wherein the second side is opposite the first side. The semiconductor chip further includes a semiconductor device formed on the first side of the substrate and an electrically insulating layer formed on at least a portion of the second side of the substrate. The semiconductor chip further includes a capacitor device formed on at least a portion of the electrically insulating layer on the second side of the substrate, wherein the capacitor device is electrically insulated from the semiconductor device. | 02-05-2015 |
20150016163 | DETECTOR AND A VOLTAGE CONVERTER - A detector for detecting an occurrence of a current strength of interest of a current of a signal to be sensed includes a magnetoresistive structure and a detection unit. The magnetoresistive structure varies a resistance depending on a magnetic field caused by the current of the signal to be sensed. Further, the detection unit generates and provides a current detection signal indicating an occurrence of the current strength of interest based on a detected magnitude of the varying resistance of the magnetoresistive structure. | 01-15-2015 |
20140306732 | DETECTION OF DEFECTIVE ELECTRICAL CONNECTIONS - An embodiment relates to an integrated circuit comprising at least two electrical connections and at least one coil arranged adjacent to at least one of the electrical connection, wherein the at least one coil each comprises at least one winding and wherein the at least one coil is arranged on or in the integrated circuit. | 10-16-2014 |
20140306331 | CHIP AND CHIP ARRANGEMENT - Various embodiments provide a chip. The chip may include a body having two main surfaces and a plurality of side surfaces; a first power electrode extending over at least one main surface and at least one side surface of the body; and a second power electrode extending over at least one main surface and at least one side surface of the body. | 10-16-2014 |
20140301116 | Switched Mode Power Supply Including a Flyback Converter with Primary Side Control - A method and apparatus for controlling a flyback converter are presented. The flyback converter includes a transformer, a semiconductor switch coupled to a primary winding of the transformer, a current measurement circuit coupled to the semiconductor switch, a diode coupled in series to a secondary winding of the transformer, and a controller. The controller is configured to receive a feedback voltage, a reference signal, and the measured primary current and generate a control signal for the semiconductor switch dependent on the feedback voltage, the reference signal, and the measured primary current. The semiconductor switch switches on and off cyclically in CCM operation. | 10-09-2014 |
20140301039 | PACKAGE AND A METHOD OF MANUFACTURING THE SAME - In various embodiments, a package may be provided. The package may include a chip carrier. The package may further include a chip arranged over the chip carrier. The package may also include encapsulation material encapsulating the chip and partially the chip carrier. A coolant receiving recess may be provided over the chip in the encapsulation material, wherein the coolant receiving recess is configured to receive coolant. | 10-09-2014 |
20140293660 | Switched Mode Power Supply - A switching power converter includes an inductor coupled to a terminal operably supplied with an input voltage. A semiconductor switch is coupled to the inductor and configured to enable and disable an input current passing through the inductor in accordance with a drive signal. A current sense circuit is coupled to the inductor or the semiconductor switch and is configured to generate a current sense signal representing the input current passing through the inductor or the semiconductor switch. A control circuit receives the current sense signal and is configured to: close the semiconductor switch regularly in accordance with a clock frequency, to integrate the current sense signal thus providing an integrated current sense signal to compare the integrated current sense signal with a threshold that is a function of the input voltage. | 10-02-2014 |
20140291849 | Multi-Level Semiconductor Package - A semiconductor package includes a semiconductor die having a first electrode at a first side and a second electrode at a second side opposing the first side, a first lead under the semiconductor die and connected to the first electrode at a first level of the package, and a second lead having a height greater than the first lead and terminating at a second level in the package above the first level, the second level corresponding to a height of the semiconductor die. A connector of a single continuous planar construction over the semiconductor die and the second lead is connected to both the second electrode and the second lead at the same second level of the package. | 10-02-2014 |
20140284819 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES HAVING A METALLISATION LAYER - A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallisation layer is formed on the second surface of the semiconductor substrate. The metallisation layer has a thickness which is greater than the device thickness. | 09-25-2014 |
20140284774 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device includes a drift zone of a first conductivity type formed within a semiconductor body, wherein one side of opposing sides of the drift zone adjoins a first zone within the semiconductor body and the other side adjoins a second zone within the semiconductor body. First semiconductor subzones of a second conductivity type different from the first conductivity type are formed within each of the first and second zones opposing each other along a lateral direction extending parallel to a surface of the semiconductor body. A second semiconductor subzone is formed within each of the first and second zones and between the first semiconductor subzones along the lateral direction. An average concentration of dopants within the second semiconductor subzone along 10% to 90% of an extension of the second semiconductor subzone along a vertical direction perpendicular to the surface is smaller than the average concentration of dopants along a corresponding section of extension within the drift zone. | 09-25-2014 |
20140284615 | METHOD FOR MANUFACTURING A SILICON CARBIDE DEVICE AND A SILICON CARBIDE DEVICE - A method for manufacturing a silicon carbide device includes providing a silicon carbide wafer and manufacturing a mask layer on top of the silicon carbide wafer. Further, the method includes structuring the mask layer at an edge of a silicon carbide device to be manufactured, so that the mask layer includes a bevel at the edge of the silicon carbide device to be manufactured. Additionally, the method includes etching the mask layer and the silicon carbide wafer by a mutual etching process, so that the bevel of the mask layer is reproduced at the edge of the silicon carbide device. | 09-25-2014 |
20140278175 | CIRCUIT ARRANGEMENT AND METHOD FOR DETERMINING A CURRENT IN A CIRCUIT ARRANGEMENT - A circuit arrangement including a rectifier circuit and a current determining circuit. The rectifier circuit is configured to rectify an alternating signal into a rectified signal. The current determining circuit is configured to determine a current of the alternating signal from at least a current of the rectified signal. | 09-18-2014 |
20140268950 | System and Method for Calibrating a Power Supply - In accordance with an embodiment, a method of calibrating a power supply includes coupling a reference load to an output of the power supply, setting an output voltage of the power supply to a first output voltage, measuring a current delivered to the reference load, and determining a current metric based on the measuring. The output voltage of the power supply is increased until the determined current metric crosses a first threshold, which occurs when the output of the power supply is at a second output voltage, and the power supply it set to operate at the second output voltage. | 09-18-2014 |
20140266131 | Power Converter Circuit - A power converter circuit includes an input and an output. A supply circuit is configured to receive an input signal from the input and to generate a number of supply signals from the input signal. A number of converter units are provided. Each of the plurality of converter units is configured to receive one of the plurality of supply signals and to output an output signal to the output. | 09-18-2014 |
20140266081 | ADAPTIVE ADJUSTMENT TO OUTPUT RIPPLE IN A DEAD ZONE - An embodiment relates to a method for adjusting a dead zone, wherein an amplitude of an oscillating signal is determined, and wherein the dead zone is adjusted based on the amplitude of the oscillating signal. | 09-18-2014 |
20140264919 | CHIP ARRANGEMENT, WAFER ARRANGEMENT AND METHOD OF MANUFACTURING THE SAME - Various embodiments provide a chip arrangement. The chip arrangement may include a first chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its second chip side; a second chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its first chip side; wherein the second chip side of the first chip and the second chip side of the second chip are facing each other; a first electrically conductive structure extending from the at least one contact of the first chip from the second chip side of the first chip through the first chip to the first chip side of the first chip; and a second electrically conductive structure. | 09-18-2014 |
20140264798 | Packaged Device Comprising Non-Integer Lead Pitches and Method of Manufacturing the Same - Packaged chips comprising non-integer lead pitches, systems and methods for manufacturing packaged chips are disclosed. In one embodiment a packaged device includes a first chip, a package encapsulating the first chip and a plurality of leads protruding from the package, wherein the plurality of leads comprises differing non-integer multiple lead pitches. | 09-18-2014 |
20140264790 | CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Various embodiments provide a chip package. The chip package may include a metallic chip carrier; at least one chip carried by the metallic chip carrier; encapsulation material encapsulating the at least one chip and the metallic chip carrier; and a plurality of redistribution layers disposed over the at least one chip opposite the metallic chip carrier, wherein at least one redistribution layer of the plurality of redistribution layers is electrically coupled with the at least one chip. | 09-18-2014 |
20140264779 | Metal Deposition on Substrates - Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate. | 09-18-2014 |
20140252627 | SEMICONDUCTOR COMPONENT COMPRISING COPPER METALLIZATIONS - A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy. | 09-11-2014 |
20140252577 | CHIP CARRIER STRUCTURE, CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - Various embodiments provide a chip carrier structure. The chip carrier structure may include a structured metallic chip carrier; encapsulating material at least partially filling the structure; wherein the main surfaces of the metallic chip carrier are free from the encapsulating material. | 09-11-2014 |
20140252537 | PACKAGE ARRANGEMENT AND A METHOD OF MANUFACTURING A PACKAGE ARRANGEMENT - In various embodiments, a package arrangement is provided. The package arrangement may include a first package. The package arrangement may further include a through hole package including at least one contact terminal. The first package may include at least one hole in an encapsulant to receive the at least one contact terminal of the through hole package. The received at least one contact terminal may provide a solder contact. | 09-11-2014 |
20140252373 | Semiconductor Device and Method for Producing the Same - A method for producing a semiconductor device is provided. The method includes providing a semiconductor substrate, providing at least one semiconductor device on the substrate, having a back face opposite the semiconductor substrate and a front face towards the semiconductor substrate, providing a contact layer on the back face of the semiconductor device, bonding the contact layer to an auxiliary carrier, and separating the at least one semiconductor device from the substrate. Further, a semiconductor device produced according to the method and an intermediate product are provided. | 09-11-2014 |
20140246766 | Semiconductor Chip Package - The semiconductor chip package comprises a carrier, a semiconductor chip comprising a first main face and a second main face opposite to the first main face, chip contact elements disposed on one or more of the first or second main faces of the semiconductor chip, an encapsulation layer covering the first main face of the semiconductor chip, the encapsulation layer comprising a first main face facing the carrier and a second main face remote from the carrier, first contact elements disposed on the second main face of the encapsulation layer, each one of the first contact elements being connected to one of the chip contact elements, and second contact elements disposed on the first main face of the encapsulation layer, each one of the second contact elements being connected to one of the chip contact elements. | 09-04-2014 |
20140240945 | Multi-Die Package with Separate Inter-Die Interconnects - A first electrode at a first side of a first semiconductor die is connected to a first conductive region of a substrate. A first electrode at a first side of a second semiconductor die is connected to a second conductive region of the substrate. Each die has a second electrode at an opposing second side of the respective die. A first metal layer extends from a periphery region of the substrate to over the first die. The first metal layer has a generally rectangular cross-sectional area and connects one of the conductive regions in the periphery region of the substrate to the second electrode of the first die. A second metal layer separate from the first metal layer extends over the first and second dies. The second metal layer has a generally rectangular cross-sectional area and connects the second electrodes of the first and second dies. | 08-28-2014 |
20140239466 | Electronic Device - An electronic device includes a first transistor device with first contact elements, a second transistor device with second contact elements, and an electrical connection member with a first main face and a second main face opposite to the first main face. The first transistor device is disposed on the first main face of the electrical connection member and the second transistor device is disposed on the second main face of the electrical connection member. One of the first contact elements is electrically connected with one of the second contact elements by a part of the electrical connection member. | 08-28-2014 |
20140232006 | Device and Method for Manufacturing a Device - A device includes a semiconductor chip including a frontside, a backside, and a side surface extending from the backside to the frontside. The side surface includes a first region and a second region, wherein a level of the first region is different from a level of the second region. The device further includes an electrically conductive material arranged over the backside of the semiconductor chip and over the first region of the side surface, wherein the second region of the side surface is uncovered by the electrically conductive material. | 08-21-2014 |
20140231969 | SEMICONDUCTOR DEVICE WITH A CHARGE CARRIER COMPENSATION STRUCTURE AND METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR DEVICE - A semiconductor device has a cell field with drift zones of a first type of conductivity and charge carrier compensation zones of a second type of conductivity complementary to the first type. An edge region which surrounds the cell field has a higher blocking strength than the cell field, the edge region having a near-surface area which is undoped to more weakly doped than the drift zones, and beneath the near-surface area at least one buried, vertically extending complementarily doped zone is positioned. | 08-21-2014 |
20140231928 | Super Junction Semiconductor Device with an Edge Area Having a Reverse Blocking Capability - A semiconductor device includes a semiconductor layer with a super junction structure including first columns of a first conductivity type and second columns of a second conductivity type opposite the first conductivity type. The super junction structure is formed in a cell area and in an inner portion of an edge area surrounding the cell area. In the inner portion of the edge area a reverse blocking capability is locally reduced by a local modification of the semiconductor layer. The local modification allows an electric field to extend in case an avalanche breakdown occurs. The reverse blocking capability is locally reduced in the edge area, wherein once an avalanche breakdown has been triggered the semiconductor device accommodates a higher reverse voltage. Avalanche ruggedness is improved. | 08-21-2014 |
20140231910 | Manufacturing a Super Junction Semiconductor Device and Semiconductor Device - A super junction semiconductor device includes a semiconductor portion with a first surface and a parallel second surface. A doped layer of a first conductivity type is formed at least in a cell area. Columnar first super junction regions of a second, opposite conductivity type extend in a direction perpendicular to the first surface. Columnar second super junction regions of the first conductivity type separate the first super junction regions from each other. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A distance between the first super junction regions and the second surface does not exceed 30 μm. The on-state or forward resistance of low-voltage devices rated for reverse breakdown voltages below 1000 V can be defined by the resistance of the super junction structure. | 08-21-2014 |
20140231909 | Super Junction Semiconductor Device Comprising Implanted Zones - In a semiconductor substrate with a first surface and a working surface parallel to the first surface, columnar first and second super junction regions of a first and a second conductivity type are formed. The first and second super junction regions extend in a direction perpendicular to the first surface and form a super junction structure. The semiconductor portion is thinned such that, after the thinning, a distance between the first super junction regions having the second conductivity type and a second surface obtained from the working surface does not exceed 30 μm. Impurities are implanted into the second surface to form one or more implanted zones. The embodiments combine super junction approaches with backside implants enabled by thin wafer technology. | 08-21-2014 |
20140231904 | Super Junction Semiconductor Device with Overcompensation Zones - According to an embodiment, a super junction semiconductor device may be manufactured by introducing impurities of a first impurity type into an exposed surface of a first semiconductor layer of the first impurity type, thus forming an implant layer. A second semiconductor layer of the first impurity type may be provided on the exposed surface and trenches may be etched through the second semiconductor layer into the first semiconductor layer. Thereby first columns with first overcompensation zones obtained from the implant layer are formed between the trenches. Second columns of the second conductivity type may be provided in the trenches. The first and second columns form a super junction structure with a vertical first section in which the first overcompensation zones overcompensate a corresponding section in the second columns. | 08-21-2014 |
20140231903 | Semiconductor Device with a Super Junction Structure Having a Vertical Impurity Distribution - A super junction semiconductor device includes a semiconductor portion with parallel first and second surfaces. An impurity layer of a first conductivity type is formed in the semiconductor portion. Between the first surface and the impurity layer a super junction structure includes first columns of the first conductivity type and second columns of a second conductivity type. A sign of a compensation rate between the first and second columns may change along a vertical extension of the columns perpendicular to the first surface. A body zone of the second conductivity type is formed between the first surface and one of the second columns. A field extension zone of the second conductivity type may be electrically connected to the body zone or a field extension zone of the first conductivity type may be connected to the impurity layer. The field extension zone improves the avalanche characteristics of the semiconductor device. | 08-21-2014 |
20140231883 | Vertical JFET with Integrated Body Diode - A vertical junction field effect transistor (JFET) includes a drain, a source, a gate, a drift region, and a body diode. The source, gate, drift region, and body diode are all disposed in the same compound semiconductor epitaxial layer. The drain is vertically spaced apart from the source and the gate by the drift region. The body diode is connected between the drain and the source. | 08-21-2014 |
20140220758 | Method for Producing a Semiconductor Device with a Vertical Dielectric Layer - A method for producing a semiconductor device is disclosed. The method includes providing a semiconductor body having a first surface, and a second surface opposite the first surface, producing a first trench having a bottom and sidewalls and extending from the first surface into the semiconductor body, forming a dielectric layer along at least one sidewall of the trench, and filling the trench with a filling material. Forming the dielectric layer includes forming a protection layer on the least one sidewall such that the protection layer leaves a section of the at least one sidewall uncovered, oxidizing the semiconductor body in the region of the uncovered sidewall section to form a first section of the dielectric layer, removing the protection layer, and forming a second section of the dielectric layer on the at least one sidewall. | 08-07-2014 |
20140218978 | CONVERTER WITH GALVANIC ISOLATION - A converter is suggested comprising a transformer providing a galvanic isolation between a primary side and a secondary side of the converter; at least one switching element; a converter control unit comprising a first pin for controlling the at least one switching element and a second pin for detecting a current signal in the at least one switching element during a first phase; and for detecting an output voltage signal of the secondary side of the converter and an information regarding a current in a secondary winding of the transformer during a second phase. | 08-07-2014 |
20140218885 | Device Including a Semiconductor Chip and Wires - A device includes a carrier, a first semiconductor chip arranged over the carrier and a first electrically conductive element arranged over the carrier. The device further includes a first wire electrically coupled to the first electrically conductive element and a second wire electrically coupled to the first electrically conductive element and to the first semiconductor chip. The first electrically conductive element is configured to forward an electrical signal between the first wire and the second wire. | 08-07-2014 |
20140218097 | SYSTEM AND METHOD FOR A DRIVER CIRCUIT - In accordance with an embodiment, a method of operating a gate driving circuit includes monitoring a signal integrity at an output of the gate driving circuit. If the signal integrity is poor based on the monitoring, output of the gate driving circuit is placed in a high impedance state and an external signal integrity failure signal is asserted. | 08-07-2014 |
20140217998 | System and Method for a Power Supply Controller - In accordance with an embodiment, a power supply controller includes an error signal input configured to be coupled to a sensing node of a power supply, a control output configured to be coupled to a switch control circuit, and a control circuit having an input coupled to the error signal input. The control circuit is configured to provide a first variable limit signal if the error signal input is in a first range, and to adjust the first variable limit signal according to the error signal input. | 08-07-2014 |
20140217901 | SPATIAL INTENSITY DISTRIBUTION CONTROLLED FLASH - This disclosure describes techniques for outputting light with a controlled spatial intensity distribution. According to some examples, this disclosure describes a device that includes at least one LED matrix that includes a plurality of LED elements. According to these examples, the device controls the LED elements of the LED matrix to output the light by causing at least a first LED element of the LED matrix to output light of a first intensity, and causing a second LED element of the LED matrix to output light of a second, different intensity. In some examples, the device controls the first at least one LED element to output light of the first intensity to illuminate a first object, and controls the second LED element to output light of the second intensity to illuminate a second object. The second object may have a different location than the first object. | 08-07-2014 |
20140217596 | POWER TRANSISTOR ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME - Various embodiments provide a power transistor arrangement. The power transistor arrangement may include a carrier; a first power transistor having a control electrode and a first power electrode and a second power electrode; and a second power transistor having a control electrode and a first power electrode and a second power electrode. The first power transistor and the second power transistor may be arranged next to each other on the carrier such that the control electrode of the first power transistor and the control electrode of the second power transistor are facing the carrier. | 08-07-2014 |
20140217495 | Integrated Circuit with Power and Sense Transistors - An integrated circuit may include a semiconductor portion with a power transistor including first gate trenches that cross a first region and a sense transistor including second gate trenches that cross a second region. Each gate trench extends in a longitudinal direction and comprises a gate electrode and a field electrode. The first and second regions are arranged along the longitudinal direction. A first termination trench intersects at least the second gate trenches in a third region between the first and second regions. The first termination trench includes a first conductive structure that is electrically connected to the field electrodes in the second gate trenches. The characteristics of the sense transistor formed in the second region reliably and precisely replicate the characteristics of the power transistor. | 08-07-2014 |
20140210428 | POWER FACTOR CORRECTION CIRCUIT - In various embodiments a circuit arrangement is provided which may include: a first AC input node and a second AC input node; a first electronic switching device coupled between the first AC input node and an output node; a second electronic switching device coupled between the second AC input node and the output node; an inductor coupled between the first electronic switching device and the second electronic switching device; a controller configured to control the first electronic switching device and the second electronic switching device to, in a first mode, provide a first current path from the first AC input node to the output node via the inductor in a first current flow direction through the inductor; and, in a second mode, provide a second current path from the second AC input node to the output node via the inductor in a second current flow direction through the inductor, the second current flow direction being different from the first current flow direction. | 07-31-2014 |
20140210061 | CHIP ARRANGEMENT AND CHIP PACKAGE - Various embodiments provide a chip arrangement. The chip arrangement may include a first chip including a first contact and a second contact; a second chip; a leadframe including a first leadframe portion and a second leadframe portion electrically insulated from the first leadframe portion; and a plurality of pins coupled to the leadframe. At least one first pin is coupled to the first leadframe portion and at least one second pin is coupled to the second leadframe portion. The first contact of the first chip is electrically coupled to the first leadframe portion and the second contact of the first chip is coupled to the second leadframe portion. A contact of the second chip is electrically coupled to the second leadframe portion. | 07-31-2014 |
20140203709 | LED Driver Circuit - A semiconductor chip includes an LED driver circuit operably coupled to at least one LED and configured to supply a load current to the at least one LED such that an average load current matches a desired current level defined by a drive signal. A temperature measurement circuit is thermally coupled to the LED driver circuit or the LED(s) or both, and is configured to generate, as drive signal, a temperature dependent signal in such a manner that the drive signal is approximately at a higher constant level for temperatures below a first temperature, is approximately at a lower constant level for temperatures above a second temperature but below a maximum temperature, and continuously drops from the higher constant level to the lower constant level for temperatures rising from the first temperature to the second temperature. | 07-24-2014 |
20140191582 | Power Converter Circuit with AC Output and at Least One Transformer - A power converter circuit includes a synchronization circuit that is configured to generate at least one synchronization signal. A series circuit includes a number of converter units configured to output an output current. At least one of the converter units includes a transformer and is configured to generate an output current such that a frequency or a phase of the generated output current is dependent on the synchronization signal. | 07-10-2014 |
20140183621 | Charge Compensation Semiconductor Device - A semiconductor device has a source metallization, drain metallization, and semiconductor body. The semiconductor body includes a drift layer of a first conductivity contacted with the drain metallization, a buffer (and field-stop) layer of the first conductivity higher in maximum doping concentration than the drift layer, and a plurality of compensation regions of a second conductivity, each forming a pn-junction with the drift and buffer layers and in contact with the source metallization. Each compensation region includes a first portion between a second portion and the source metallization. The first portions and the drift layer form a first area having a vanishing net doping. The second portions and the buffer layer form a second area of the first conductivity. A space charge region forms in the second area when a reverse voltage of more than 30% of the device breakdown voltage is applied between the drain and source metallizations. | 07-03-2014 |
20140175888 | Power Converter Circuit with AC Output - A power converter circuit includes a synchronization circuit configured to generate at least one synchronization signal. A series circuit includes a number of converter units configured to output an overall output current. At least one of the converter units generates an output current such that at least one of a frequency and a phase of the generated output current is dependent on the synchronization signal. | 06-26-2014 |
20140167665 | Safety Circuit and Emergency Power Supply for Gate Control Circuit - A power supply circuit can be used to provide an alternating-current supply voltage to an electric motor. The power supply circuit is supplied by line power. The power supply circuit includes a inverter including at least one pair of transistor for generating a corresponding phase of the plurality of power supply phases. The inverter includes a transistor control circuit for switching the low-side transistor to its conducting state and the high-side transistor to its non-conducting state in case an excess voltage is detected at the input of the inverter. | 06-19-2014 |
20140167155 | SEMICONDUCTOR COMPONENT ARRANGEMENT AND METHOD FOR PRODUCING THEREOF - A semiconductor component arrangement and method for producing thereof is disclosed. One embodiment provides at least one power semiconductor component integrated in a semiconductor body and at least one logic component integrated in the semiconductor body. The logic component includes a trench extending into the semiconductor body proceeding from a first side, at least one gate electrode arranged in the trench and insulated from the semiconductor body by a gate dielectric, and at least one source zone and at least one drain zone of a first conduction type, which are formed in the semiconductor body in a manner adjacent to the gate dielectric and in a manner spaced apart from one another in a peripheral direction of the trench and between which at least one body zone of a second conduction type is arranged. | 06-19-2014 |
20140162552 | System and Method for Receiving Data Across an Isolation Barrier - In one embodiment, a system for communication has a receiver for receiving data from a passive transmitter capacitively coupled to the receiver. The receiver has a sensing element having a plurality of terminals configured to be capacitively coupled to the passive transmitter and DC isolated from the passive transmitter. | 06-12-2014 |
20140159697 | PROTECTION CIRCUIT FOR PROTECTING A HALF-BRIDGE CIRCUIT - The present invention relates to a protection circuit for protecting a half-bridge circuit. The protection circuit detects an incorrect response of the half-bridge by monitoring the current of a first switch at a series resistor of a second switch. The protection circuit has a detector for detecting the voltage across the resistor and an evaluation circuit which is designed in such a manner that it evaluates an output signal from the detector after the first switch has been switched on and provides a fault signal at an output when the voltage across the resistor is greater than the threshold voltage. | 06-12-2014 |
20140153294 | AC/DC Power Converter Arrangement - A converter arrangement, includes a DC/DC stage comprising a plurality of DC/DC converters. Each of the plurality of DC/DC converters is operable to receive one of a plurality of direct input voltages. The DC/DC stage is configured to generate an output voltage from the plurality of direct input voltages. | 06-05-2014 |
20140153206 | SYSTEMS AND METHODS FOR EMBEDDING DEVICES IN PRINTED CIRCUIT BOARD STRUCTURES - Embodiments relate to active devices embedded within printed circuit boards (PCBs). In embodiments, the active devices can comprise at least one die, such as a semiconductor die, and coupling elements for mechanically and electrically coupling the active device with one or more layers of the PCB in which the device is embedded. Embodiments thereby provide easy embedding of active devices in PCBs and inexpensive integration with existing PCB technologies and processes. | 06-05-2014 |
20140151804 | Semiconductor Device Including a Fin and a Drain Extension Region and Manufacturing Method - One embodiment of a semiconductor device includes a fin on a first side of a semiconductor body. The semiconductor device further includes a body region of a second conductivity type in at least a part of the fin. The semiconductor device further includes a drain extension region of a first conductivity type, a source and a drain region of the first conductivity type, and a gate structure adjoining opposing walls of the fin. The body region and the drain extension region are arranged one after another between the source region and the drain region. | 06-05-2014 |
20140145777 | System and Method for a Level Shifter - In accordance with an embodiment, a level shifter circuit includes a reconfigurable level shifting core coupled to a first node and a second node. The reconfigurable level shifting core is configured as a current mirror in a first mode, and as a cross-coupled device in a second mode. In the first mode, the current mirror mirrors a current at the first node to the second node, and in the second mode, the cross-coupled device produces a current at the second node in response to a voltage at the first node, and a current at the first node in response to a voltage at the second node. | 05-29-2014 |
20140141594 | Method for Manufacturing a Semiconductor Device - A method for producing a semiconductor device is provided. The method includes: providing a wafer including an upper surface and a plurality of semiconductor mesas extending to the upper surface; forming a first support structure made of a first material and adjoining the plurality of semiconductor mesas at the upper surface so that adjacent pairs of the plurality of semiconductor mesas are bridged by the first support structure; forming a second support structure made of a second material different from the first material and adjoining the plurality of semiconductor mesas at the upper surface so that the adjacent pairs of the plurality of semiconductor mesas are bridged by the second support structure; removing the first support structure; and at least partly removing the second support structure. | 05-22-2014 |
20140138833 | Semiconductor Device Assembly Including a Chip Carrier, Semiconductor Wafer and Method of Manufacturing a Semiconductor Device - A semiconductor device includes a chip carrier and a semiconductor die with a semiconductor portion and a conductive structure. A soldered layer mechanically and electrically connects the chip carrier and the conductive structure at a soldering side of the semiconductor die. At the soldering side an outermost surface portion along an edge of the semiconductor die has a greater distance to the chip carrier than a central surface portion. The conductive structure covers the central surface portion and at least a section of an intermediate surface portion tilted to the central surface portion. Solder material is effectively prevented from coating such semiconductor surfaces that are prone to damages and solder-induced contamination is significantly reduced. | 05-22-2014 |
20140133545 | System and Method for Multi-Channel Control System - A system having has a pulse width modulation controller to successively activate each of a plurality of channels each in its own individual channel time slot is described. The system also has a sampling multiplexer configured to successively sample a signal derived from each of the plurality of channels during each individual channel time slot. Each individual time slot has an individual sampling sequence. | 05-15-2014 |
20140131792 | Semiconductor Device with Metal-Filled Groove in Polysilicon Gate Electrode - A semiconductor device includes a semiconductor substrate, a body region of a first conductivity type in the substrate, a source region of a second conductivity type opposite the first conductivity type adjacent the body region, and a trench extending into the substrate adjacent the source and body regions. The trench contains a polysilicon gate electrode insulated from the substrate. The device further includes a dielectric layer on the substrate, a gate metallization on the dielectric layer and covering part of the substrate and a source metallization on the dielectric layer and electrically connected to the source region. The source metallization is spaced apart from the gate metallization and covers a different part of the substrate than the gate metallization. A metal-filled groove in the polysilicon gate electrode is electrically connected to the gate metallization, and extends along a length of the trench underneath at least part of the source metallization. | 05-15-2014 |
20140126165 | Packaged Nano-Structured Component and Method of Making a Packaged Nano-Structured Component - An assembled component and a method for assembling a component are disclosed. In one embodiment the assembled component includes a component carrier, an attachment layer disposed on the component carrier and a component disposed on the attachment layer, the component having a nano-structured first main surface facing the component carrier. | 05-08-2014 |
20140124851 | Radiation-Hardened Power Semiconductor Devices and Methods of Forming Them - According to an embodiment, a method of forming a power semiconductor device is provided. The method includes providing a semiconductor substrate and forming an epitaxial layer on the semiconductor substrate. The epitaxial layer includes a body region, a source region, and a drift region. The method further includes forming a dielectric layer on the epitaxial layer. The dielectric layer is formed thicker above a drift region of the epitaxial layer than above at least part of the body region and the dielectric layer is formed at a temperature less than 950° C. | 05-08-2014 |
20140124791 | HEMT with Compensation Structure - A high electron mobility transistor includes a source, a gate and a drain, a first III-V semiconductor region, and a second III-V semiconductor region below the first III-V semiconductor region. The high electron mobility transistor further includes a compensation structure interposed between the first and second III-V semiconductor regions so that the first and second III-V semiconductor regions are spaced apart from one another by the compensation structure. The compensation structure has a different band gap than the first and second III-V semiconductor regions. | 05-08-2014 |
20140118057 | Half Bridge Flyback and Forward - A circuit includes a transformer having a first winding and a second winding, an input connected to a first terminal of the first winding, a first power transistor and a second power transistor. The first power transistor has a source, a gate, and a drain connected to a second terminal of the first winding. The second power transistor has a source connected to ground, a gate connected to a pulsed voltage drive source and a drain connected to the source of the first power transistor. The gate of the first power transistor is connected to a DC source or the same pulsed voltage drive source as the gate of the second power transistor. The first power transistor actively turns off independent of load current. Other circuit embodiments and corresponding load switching methods are also provided. | 05-01-2014 |
20140111955 | HIGH EFFICIENCY EMBEDDING TECHNOLOGY - Representative implementations of devices and techniques provide improved electrical access to components, such as chip dice, for example, disposed within layers of a multi-layer printed circuit board (PCB). One or more insulating layers may be located on either side of a spacer layer containing the components. The insulating layers may have apertures strategically located to provide electrical connectivity between the components and conductive layers of the PCB. | 04-24-2014 |
20140111951 | HIGH PERFORMANCE VERTICAL INTERCONNECTION - Representative implementations of devices and techniques provide improved electrical performance of components, such as chip dice, for example, disposed on different layers of a multi-layer printed circuit board (PCB). In an example, the components may be embedded within layers of the PCB. An insulating layer located between two component layers or sets of layers includes a conductive portion that may be strategically located to provide electrical connectivity between the components. The conductive portion may also be arranged to improve thermal conductivity between points of the PCB. | 04-24-2014 |
20140110828 | Semiconductor Packages and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor device includes a lead frame having a die paddle and a lead. A chip is disposed over the die paddle of the lead frame. The semiconductor device further includes a clip, which is disposed over the chip. The clip couples a pad on the chip to the lead of the lead frame. The clip also includes a heat sink. | 04-24-2014 |
20140110820 | PASSIVE COMPONENT AS THERMAL CAPACITANCE AND HEAT SINK - Representative implementations of devices and techniques provide improved thermal performance of a chip die disposed within a layered printed circuit board (PCB). Passive components may be strategically located on one or more surfaces of the PCB. The passive components may be arranged to conduct heat generated by the chip die away from the chip die. | 04-24-2014 |
20140106516 | SELF-DOPED OHMIC CONTACTS FOR COMPOUND SEMICONDUCTOR DEVICES - A compound semiconductor device is manufactured by forming an III-nitride compound semiconductor device structure on a silicon-containing semiconductor substrate, the III-nitride compound semiconductor device structure including a GaN alloy on GaN and a channel region arising near an interface between the GaN alloy and the GaN. One or more silicon-containing insulating layers are formed on a surface of the III-nitride compound semiconductor device structure adjacent the GaN alloy, and a contact opening is formed which extends through the one or more silicon-containing insulating layers to at least the GaN alloy. A region of GaN is regrown in the contact opening, and the regrown region of GaN is doped exclusively with Si out-diffused from the one or more silicon-containing insulating layers to form an ohmic contact which is doped only with the Si out-diffused from the one or more silicon-containing insulating layers. | 04-17-2014 |
20140104905 | RECTIFIER CIRCUIT WITH A VOLTAGE SENSOR - A rectifier circuit with a semiconductor element is disclosed. The semiconductor element includes at least one field effect transistor with a control electrode, and at least one driver. The driver cooperates with a voltage sensor, and controls the field effect transistor to a conducting state. The semiconductor element includes the voltage sensor insulated from the at least one field effect transistor. The voltage sensor includes a separate sensor electrode, and a sensor capacitance of the voltage sensor forms a non-linear voltage divider with a reference capacitance. | 04-17-2014 |
20140103398 | RF POWER HEMT GROWN ON A SILICON OR SIC SUBSTRATE WITH A FRONT-SIDE PLUG CONNECTION - A compound semiconductor device includes a plurality of high-resistance crystalline silicon epitaxial layers and a plurality of activated dopant regions disposed in a same region of at least some of the epitaxial layers so that the activated dopant regions are aligned in a vertical direction perpendicular to a main surface of the epitaxial layers. The compound semiconductor device further includes an III-nitride compound semiconductor device structure disposed on the main surface of the epitaxial layers. The III-nitride compound semiconductor device structure has a source, a drain and a gate. An electrically conductive structure is formed from the activated dopant regions. The electrically conductive structure extends in the vertical direction through the epitaxial layers with the activated dopant regions toward the III-nitride compound semiconductor device structure, and is electrically connected to the source. | 04-17-2014 |
20140097478 | REDUCED CHARGE TRANSISTOR - Representative implementations of devices and techniques provide a reduced charge transistor arrangement. The capacitance and/or charge of a transistor structure may be reduced by minimizing an overlap of a top gate with respect to a drain of the transistor. | 04-10-2014 |
20140091852 | Switch Circuit with a First Transistor Device and a Second Transistor Device Connected in Series - A method can be used for driving a switch circuit. The switch circuit includes a first transistor device and a second transistor device. Both the first transistor device and the second transistor device have a load path and a control terminal. The load paths of the first transistor device and the second transistor device are connected in series. The control terminal of the first transistor device is configured to receive a first drive signal and the control terminal of the second transistor device is configured to receive a second drive signal. One of an on-level switching on the first transistor device or an off-level switching off the first transistor device of the first drive signal is selected and one of a first signal level and a second signal level of the second drive signal is selected. | 04-03-2014 |
20140091840 | High-Side Semiconductor-Switch Low-Power Driving Circuit and Method - A high-side semiconductor-switch driving method includes generating power for controlling a high side semiconductor switch. The high side semiconductor switch has a control terminal and the power allows a current to flow into the control terminal of the high side semiconductor switch to switch the high side semiconductor switch. The voltage at the control terminal of the high side semiconductor switch is quantified. The power dependent on the voltage at the control terminal of the high side semiconductor switch is controlled so that the current provided is increased when the voltage at the control terminal indicates that the current is not sufficient to switch the high side semiconductor switch. | 04-03-2014 |
20140091839 | Electronic Circuit with a Reverse Conducting Transistor Device - An electronic circuit includes a first transistor device with a control terminal and a load path. A drive circuit includes an input terminal and an output terminal. The output terminal is coupled to the control terminal of the first transistor device. The drive circuit is operable to drive the first transistor device dependent on an input signal received at the input terminal. A polarity detector is coupled in parallel with the load path of the first transistor device. The polarity detector includes a second transistor device and a current detector. The second transistor device includes a load path connected to the load path of the first transistor device. The current detector includes a sense path in series with the load path of the second transistor device and an output connected to the input terminal of the drive circuit. | 04-03-2014 |
20140084295 | Transistor Device with Field Electrode - A transistor device includes a semiconductor body having a source region, a drift region, and a body region between the source region and the drift region. A source electrode is electrically coupled to the source region. A gate electrode adjacent the body region is dielectrically insulated from the body region by a gate dielectric. A field electrode adjacent the drift region is dielectrically insulated from the drift region by a field electrode dielectric and electrically coupled to one of the gate electrode and the source electrode. A rectifier element electrically couples the field electrode to the one of the gate electrode and the source electrode. | 03-27-2014 |
20140080294 | Method for Manufacturing a Semiconductor Structure - According to an embodiment, a method for manufacturing a semiconductor structure includes providing a first monocrystalline semiconductor portion having a first lattice constant in a reference direction and forming a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion. | 03-20-2014 |
20140073110 | METHOD FOR FABRICATING A TRENCH STRUCTURE, AND A SEMICONDUCTOR ARRANGEMENT COMPRISING A TRENCH STRUCTURE - A semiconductor device, in which a first trench section is produced proceeding from a surface of a semiconductor body into the semiconductor body. A semiconductor layer is produced above the surface and above the first trench section. A further trench section is produced in the semiconductor layer in such a way that the first trench section and the further trench section form a continuous trench structure. | 03-13-2014 |
20140072429 | CIRCUITS, SYSTEMS AND METHODS FOR INTEGRATING SENSING AND HEATING FUNCTIONS - Embodiments relate to integrated circuits, systems and methods for combined sensing and heating functions in structures suitable for use in deicing, heating and other applications. In an embodiment, an integrated circuit is coupled to a heating element and configured to control operation of the heating element to provide heat as well as to utilize the heating element as at least part of a sensing structure to sense the presence of ice, water or air on or near the heating element. In embodiments, the heating element comprises a conductive polymer structure, and the presence of ice, water or air is sensed based on a capacitance, impedance or other spectroscopy of the structure sensed and analyzed by integrated circuitry coupled to the structure. | 03-13-2014 |
20140070728 | Circuit and Method for Driving LEDs - A circuit for driving light emitting diodes includes a first semiconductor switch that is responsive to a driver signal and a freewheeling device coupled between a first supply terminal that provides a supply voltage and a second supply terminal that provides a reference potential. An LED and an inductor are coupled in series between a common circuit node of the first semiconductor switch and the freewheeling device and either the first supply terminal or the second supply terminal. A current measurement circuit is coupled to the LED and provides a load current signal that represents a load current passing through the at least one LED. A first feedback circuit includes an on-off controller that receives load current signal and a reference signal, compares the load current signal with the reference signal and generates the driver signal dependent on the comparison. | 03-13-2014 |
20140070727 | CIRCUIT AND METHOD FOR DRIVING LEDS - A circuit for driving light emitting diodes (LEDs) includes a first semiconductor switch and a freewheeling device coupled between a first supply terminal that provides a supply voltage and a second supply terminal that provides a reference potential. The first semiconductor switch is responsive to a driver signal. An LED and an inductor are coupled in series between a common circuit node of the first semiconductor switch and the freewheeling device and either the first supply terminal or the second supply terminal. A current measurement circuit is coupled to the LED and provides a load current signal which represents a load current passing through the at least one LED. A first feedback circuit includes an on-off controller that receives load current signal and a reference signal. | 03-13-2014 |
20140070356 | Method for Protecting a Semiconductor Device Against Degradation and a Method for Manufacturing a Semiconductor Device Protected Against Hot Charge Carriers - A method for protecting a semiconductor device against degradation of its electrical characteristics is provided. The method includes providing a semiconductor device having a first semiconductor region and a charged dielectric layer which form a dielectric-semiconductor interface. The majority charge carriers of the first semiconductor region are of a first charge type. The charged dielectric layer includes fixed charges of the first charge type. The charge carrier density per area of the fixed charges is configured such that the charged dielectric layer is shielded against entrapment of hot majority charge carriers generated in the first semiconductor region. Further, a semiconductor device which is protected against hot charge carriers and a method for forming a semiconductor device are provided. | 03-13-2014 |
20140063882 | Circuit Arrangement with Two Transistor Devices - A circuit arrangement includes a first transistor device and a second transistor device. Each transistor device includes a first load terminal, a second load terminal, a gate terminal, and a control terminal. The first load terminals are electrically connected, and the control terminals are electrically connected. A capacitive storage element is connected between the first load terminals and the control terminals. | 03-06-2014 |
20140062544 | Semiconductor Device Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices - Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device. | 03-06-2014 |
20140062436 | VOLTAGE REGULATOR - In various embodiments a voltage regulating circuit is provided which may include a control transistor at least partially formed in an n-type substrate, and a regulating circuit including a regulating output coupled to a control region of the control transistor, wherein the regulating circuit includes at least one transistor which is formed at least one of on and in the n-type substrate. | 03-06-2014 |
20140061863 | METHOD FOR PRODUCING A SEMICONDUCTOR LAYER - A method for producing a semiconductor layer is disclosed. One embodiment provides for a semiconductor layer on a semiconductor substrate containing oxygen. Crystal defects are produced at least in a near-surface region of the semiconductor substrate. A thermal process is carried out wherein the oxygen is taken up at the crystal defects. The semiconductor layer is deposited epitaxially over the near-surface region of the semiconductor substrate. | 03-06-2014 |
20140061647 | Field-Effect Semiconductor Device and Manufacturing Method Therefor - According to an embodiment of a field-effect semiconductor device, the field-effect semiconductor device includes a semiconductor body and a source electrode. The semiconductor body includes a drift region, a gate region and a source region of a first semiconductor material having a first band-gap and an anode region of a second semiconductor material having a second band-gap lower than the first band-gap. The drift region is of a first conductivity type. The gate region forms a pn-junction with the drift region. The source region is of the first conductivity type and in resistive electric connection with the drift region and has a higher maximum doping concentration than the drift region. The anode region is of the second conductivity type, forms a heterojunction with the drift region and is spaced apart from the source region. The source metallization is in resistive electric connection with the source region and the anode region. | 03-06-2014 |
20140055114 | System for Balancing Current Supplied to a Load - A system for balancing current supplied by a plurality of regulators coupled to a load includes circuitry operable to measure an average load current supplied by each regulator, determine an overall average current to be shared by the plurality of regulators, and compare each average load current with the overall average current to be shared by the plurality of regulators. The circuitry included in the system is also operable to adjust an output current of one or more of the plurality of regulators so that the plurality of regulators supply the same current to the load. | 02-27-2014 |
20140054697 | SEMICONDUCTOR DEVICE WITH FIELD ELECTRODE AND METHOD - A semiconductor device with a field electrode and method. One embodiment provides a controllable semiconductor device including a control electrode for controlling the semiconductor device and a field electrode. The field electrode includes a number of longish segments which extend in a first lateral direction and which run substantially parallel to one another. The control electrode includes a number of longish segments extending in a second lateral direction and running substantially parallel to one another, wherein the first lateral direction is different from the second lateral direction. | 02-27-2014 |
20140049866 | Method for Controlling a Transistor and Control Circuit - A description is given of a method for the pulsed control of a transistor which has a control terminal and a load path. The load path of the transistor is connected in series with a load. A control circuit is provided for a transistor. In the method, the transistor is controlled with a control pulse of a first type, which has a first control level at least for a first time duration, before a control pulse of a second type, which has a second control level, which is higher in comparison with the first control level. A voltage across the load path of the transistor is evaluated and the pulsed control is terminated if the voltage across the load path exceeds a predefined threshold value. | 02-20-2014 |
20140042631 | SEMICONDUCTOR COMPONENT COMPRISING COPPER METALLIZATIONS - A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy. | 02-13-2014 |
20140042595 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING GRINDING FROM A BACK SURFACE AND SEMICONDUCTOR DEVICE - A cavity is etched from a front surface into a semiconductor substrate. After providing an etch stop structure at the bottom of the cavity, the cavity is closed. From a back surface opposite to the front surface the semiconductor substrate is grinded at least up to an edge of the etch stop structure oriented to the back surface. Providing the etch stop structure at the bottom of an etched cavity allows for precisely adjusting a thickness of a semiconductor body of a semiconductor device. | 02-13-2014 |
20140042593 | SEMICONDUCTOR DEVICE INCLUDING A TRENCH IN A SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate. A first trench extends into or through the semiconductor substrate from a first side. A semiconductor layer adjoins the semiconductor substrate at the first side. The semiconductor layer caps the first trench at the first side. The semiconductor device further includes a contact at a second side of the semiconductor substrate opposite to the first side. | 02-13-2014 |
20140042448 | High Breakdown Voltage III-Nitride Device - A semiconductor device includes a semiconductor body having a compound semiconductor material on a substrate. The compound semiconductor material has a channel region. A source region extends to the compound semiconductor material. A drain region also extends to the compound semiconductor material and is spaced apart from the source region by the channel region. An insulating region is buried in the semiconductor body between the compound semiconductor material and the substrate in an active region of the semiconductor device. The active region includes the source, the drain and the channel region of the device. The insulating region is discontinuous over a length of the channel region between the source region and the drain region. | 02-13-2014 |
20140038413 | Method of Manufacturing a Semiconductor Device including a Dielectric Structure - A dielectric layer is deposited on a working surface of a substrate, wherein the dielectric layer contains or consists of a dielectric polymer. The dielectric layer is partially cured. A portion of the partially cured dielectric layer is removed using a chemical mechanical polishing process. Then the curing of remnant portions of the partially cured dielectric layer is continued to form a dielectric structure. The partially cured dielectric layer shows high removal rates during chemical mechanical polishing. With remnant portions of the dielectric layer provided in cavities, high volume insulating structures can be provided in an efficient manner. | 02-06-2014 |
20140035003 | Protection Device for Normally-On and Normally-Off High Electron Mobility Transistors - A transistor device includes a compound semiconductor body, a normally-on high electron mobility field effect transistor (HEMT) formed in the compound semiconductor body and a protection device monolithically integrated in the same compound semiconductor body as the normally-on HEMT. The normally-on HEMT has a source, a drain, a gate, and a threshold voltage. The protection device has a source and a drain each shared with the normally-on HEMT, a gate and a positive threshold voltage that is less than a difference of the threshold voltage of the normally-on HEMT and a gate voltage used to turn off the normally-on HEMT. The protection device is operable to conduct current in a reverse direction when the normally-on HEMT is switched off. A transistor device including a normally-off HEMT and a monolithically integrated protection device is also provided. | 02-06-2014 |
20140028346 | Low Supply Voltage Logic Circuit - A low supply voltage logic circuit includes a first current source operable to generate a first current dependent on a first control signal and to generate a first leakage current. A second current source is operable to generate a second current dependent on a second control signal and to generate a second leakage current. A third current source has a third current path between the output terminal and the first supply voltage terminal and is operable to generate a third current through the third current path to compensate for the second leakage current. A fourth current source has a fourth current path between the output terminal and the second supply voltage terminal and is operable to generate a fourth current through the fourth current path to compensate for the first leakage current. | 01-30-2014 |
20140028086 | CIRCUIT ARRANGEMENTS AND A METHOD FOR RECEIVING INFORMATION - A circuit arrangement is provided, the circuit arrangement including a receiver configured to receive signal information from a sensor circuit; a discharge circuit configured to discharge a capacitance by providing a discharge pulse; and a modulation circuit configured to modulate a bit pattern onto the discharge pulse. | 01-30-2014 |
20140027879 | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT - One aspect of the invention relates to a semiconductor component with a semiconductor body with a top side and with a bottom side. A first coil that is monolithically integrated with the semiconductor body is arranged distant from the bottom side and comprises N first windings, wherein N≧1. The first coil has a first coil axis that extends in a direction different from a surface normal of the bottom side. | 01-30-2014 |
20140017874 | SEMICONDUCTOR BODY WITH A BURIED MATERIAL LAYER AND METHOD - One aspect includes a method for forming a buried material layer in a semiconductor body, including providing a semiconductor body having a first side and having a plurality of first trenches extending from the first surface into the semiconductor body. Each of the plurality of first trenches has a bottom and has at least one sidewall and the plurality of first trenches is separated from one another by semiconductor mesa regions. A first material layer is formed on the bottom of each of the plurality of first trenches such that the first material layer leaves at least one segment of at least one sidewall of each of the plurality of trenches uncovered. Each of the plurality of first trenches is filled by epitaxially growing a semiconductor material from the at least one uncovered sidewall segment. After filling the first trenches, second trenches are formed in the mesa regions. | 01-16-2014 |
20140002145 | DRIVING CIRCUIT FOR A TRANSISTOR | 01-02-2014 |
20140002141 | System and Method for a Driver Circuit | 01-02-2014 |
20140001615 | Package-In-Packages and Methods of Formation Thereof | 01-02-2014 |
20140001558 | Semiconductor Device | 01-02-2014 |
20140001552 | Super Junction Semiconductor Device Comprising a Cell Area and an Edge Area | 01-02-2014 |
20140001547 | Semiconductor Device Including an Edge Area and Method of Manufacturing a Semiconductor Device | 01-02-2014 |
20130337640 | METHOD FOR FABRICATING A POROUS SEMICONDUCTOR BODY REGION - A method for fabricating a porous semiconductor body region, including producing at least one trench in a semiconductor body, starting from a surface of the semiconductor body, producing at least one porous semiconductor body region in the semiconductor body starting from the at least one trench at least along a portion of the side walls of the trench, and filling the trench with a semiconductor material of the semiconductor body. | 12-19-2013 |
20130334653 | Semiconductor Device with an Edge Termination Structure - A semiconductor device having a semiconductor die and an edge termination structure is provided. The semiconductor die includes an outer edge and an active area defining a main horizontal surface and being spaced apart from the outer edge. The edge termination structure includes at least one vertical trench having an insulated side wall forming, in a horizontal cross-section, an acute angle with the outer edge. The acute angle is lower than about 20°. | 12-19-2013 |
20130334649 | SEMICONDUCTOR DEVICE HAVING VARIABLY LATERALLY DOPED ZONE WITH DECREASING CONCENTRATION FORMED IN THE TERMINATION REGION - In a semiconductor body, a semiconductor device has an active region with a vertical drift section of a first conduction type and a near-surface lateral well of a second, complementary conduction type. An edge region surrounding this active region comprises a variably laterally doped doping material zone (VLD zone). This VLD zone likewise has the second, complementary conduction type and adjoins the well. The concentration of doping material of the VLD zone decreases to the concentration of doping material of the drift section along the VLD zone towards a semiconductor chip edge. Between the lateral well and the VLD zone, a transitional region is provided which contains at least one zone of complementary doping located at a vertically lower point than the well in the semiconductor body. | 12-19-2013 |
20130334573 | Multi-Channel HEMT - A transistor device includes a semiconductor heterostructure including a plurality of alternating two-dimensional electron gasses (2DEGs) and two-dimensional hole gasses (2DHGs) extending in parallel at different depths in the semiconductor heterostructure. The 2DEGs form current channels of the transistor device. The transistor device further includes a source extending into the semiconductor heterostructure in contact with the 2DEGs at a first end of the current channels, and a drain extending into the semiconductor heterostructure in contact with the 2DEGs at an opposing second end of the current channels. The transistor device also includes a plurality of spaced apart gate structures extending into the semiconductor heterostructure and including an electrically conductive material separated from the surrounding semiconductor heterostructure by an insulating material. | 12-19-2013 |
20130334565 | Method of Manufacturing a Semiconductor Device Using an Impurity Source Containing a Metallic Recombination Element and Semiconductor Device - Source zones of a first conductivity type and body zones of a second conductivity type are formed in a semiconductor die. The source zones directly adjoin a first surface of the semiconductor die. A dielectric layer adjoins the first surface. Polysilicon plugs extend through the dielectric layer and are electrically connected to the source and the body zones. An impurity source containing at least one metallic recombination element is provided in contact with deposited polycrystalline silicon material forming the polysilicon plugs and distant to the semiconductor die. Atoms of the metallic recombination element, for example platinum atoms, may be diffused out from the impurity source into the semiconductor die to reliably reduce the reverse recovery charge. | 12-19-2013 |
20130333203 | Method for Manufacturing a Transformer Device on a Glass Substrate - A method for manufacturing a transformer device includes providing a glass substrate having a first side and a second side arranged opposite the first side, forming a first recess in the glass substrate at the first side of the glass substrate, forming a second recess in the glass substrate at the second side of the glass substrate opposite to the first recess, forming a first coil in the first recess, and forming a second coil in the second recess. | 12-19-2013 |
20130328183 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES HAVING A GLASS SUBSTRATE - A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallisation region is formed on the machined second surface of the semiconductor wafer. | 12-12-2013 |
20130326100 | Arbiter for Asynchronous State Machines - An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the data signals and the validity vector includes values depending on the request signals when the latch array is in a transparent state. Logic circuitry is configured to trigger the latch array when any of the request signals becomes active, to activate a global request signal a delay time after the latch has been triggered, and to selectively activate the acknowledge signals for a channel or channels for which an active request signal has been latched. | 12-05-2013 |
20130323897 | SEMICONDUCTOR DEVICE WITH IMPROVED ON-RESISTANCE - A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone. | 12-05-2013 |
20130322125 | DRIVING CIRCUIT FOR A TRANSISTOR - In various embodiments, a driving circuit for a transistor is provided, wherein the transistor may include a transistor having a control terminal, a diode, a capacitance with a first terminal and a second terminal, wherein the first terminal may be coupled to the control terminal and the second terminal may be coupled to a reference potential via the diode, and a resistor, which is coupled in parallel to the capacitance. | 12-05-2013 |
20130321053 | METHOD AND DEVICE FOR SAMPLING AN INPUT SIGNAL - In accordance with various embodiments, a method for sampling an input signal may be provided, wherein the method may include providing a single frequency clock signal; selecting clock pulses from the single frequency clock signal in a random manner to generate a spread spectrum clock signal; and sampling the input signal using the spread spectrum clock signal. A corresponding device for sampling an input signal may be provided. | 12-05-2013 |
20130320952 | MONOLITHICALLY INTEGRATED HEMT AND CURRENT PROTECTION DEVICE - A transistor device includes a high electron mobility field effect transistor (HEMT) and a protection device. The HEMT has a source, a drain and a gate. The HEMT switches on and conducts current from the source to the drain when a voltage applied to the gate exceeds a threshold voltage of the HEMT. The protection device is monolithically integrated with the HEMT so that the protection device shares the source and the drain with the HEMT and further includes a gate electrically connected to the source. The protection device conducts current from the drain to the source when the HEMT is switched off and a reverse voltage between the source and the drain exceeds a threshold voltage of the protection device. The protection device has a lower threshold voltage than the difference of the threshold voltage of the HEMT and a gate voltage used to turn off the HEMT. | 12-05-2013 |
20130320512 | Semiconductor Device and Method of Manufacturing a Semiconductor Device - A method of manufacturing a semiconductor device includes forming a trench in a semiconductor body. The method further includes doping a part of the semiconductor body via sidewalls of the trench by plasma doping. | 12-05-2013 |
20130320487 | Semiconductor Device with Trench Structures - A semiconductor body of a semiconductor device includes a doped layer of a first conductivity type and one or more doped zones of a second conductivity type. The one or more doped zones are formed between the doped layer and the first surface of a semiconductor body. Trench structures extend from one of the first and the second opposing surface into the semiconductor body. The trench structures are arranged between portions of the semiconductor body which are electrically connected to each other. The trench structures may be arranged for mitigating mechanical stress, locally controlling charge carrier mobility, locally controlling a charge carrier recombination rate and/or shaping buried diffusion zones. | 12-05-2013 |
20130320444 | INTEGRATED CIRCUIT HAVING VERTICAL COMPENSATION COMPONENT - An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed. | 12-05-2013 |
20130320350 | Compound Semiconductor Transistor with Self Aligned Gate - A transistor device includes a compound semiconductor body having a first surface and a two-dimensional charge carrier gas disposed below the first surface in the compound semiconductor body. The transistor device further includes a source in contact with the two-dimensional charge carrier gas and a drain spaced apart from the source and in contact with the two-dimensional charge carrier gas. A first passivation layer is in contact with the first surface of the compound semiconductor body, and a second passivation layer is disposed on the first passivation layer. The second passivation layer has a different etch rate selectivity than the first passivation layer. A gate extends through the second passivation layer into the first passivation layer. | 12-05-2013 |
20130313653 | MOS Transistor with Multi-finger Gate Electrode - A field effect transistor is described. In accordance with the one example, the transistor includes a semiconductor substrate, a gate pad for receiving a gate signal, a number of transistor cells integrated in the substrate, wherein each transistor cell has at least one gate electrode. The transistor further includes a number of gate runners for distributing the gate signal to the gate electrodes of the transistor cells. Each individual gate runner is electrically coupled to the gate pad via a respective gate resistor having a defined resistance. | 11-28-2013 |
20130313632 | Semiconductor Device with Voltage Compensation Structure - A voltage compensation structure includes a first semiconductor or insulating material disposed along one or more sidewalls of a trench formed in a doped epitaxial semiconductor material. The first semiconductor or insulating material has a dopant diffusion constant which is at least 2× different for n-type dopant atoms than p-type dopant atoms. The voltage compensation structure further includes a doped second semiconductor material disposed in the trench so that the first semiconductor or insulating material is interposed between the doped second semiconductor material and the doped epitaxial semiconductor material. The doped second semiconductor material has a different dopant diffusion constant than the first semiconductor or insulating material so that a lateral charge separation occurs between the doped second semiconductor material and the doped epitaxial semiconductor material. | 11-28-2013 |
20130307589 | Driver Circuit for driving Semiconductor Switches - A driver circuit can be used to drive a semiconductor switch to an on-state or an off-state in accordance with a control signal. The operating voltage range of the control signal is represented by a reference voltage. And input stage receives the control signal and the reference voltage and generates a modified control signal. An output stage is coupled to the input stage and receives the modified control signal. The output stage is configured to provide a driver signal for driving the semiconductor switch on and off in accordance with the modified control signal. The input stage is configured to scale the control signal dependent on the level of the reference voltage, to compare the scaled control signal with at least one threshold value that is responsive to the reference voltage, and to generate the modified control signal dependent on the result of the comparison. | 11-21-2013 |
20130307127 | Semiconductor Device Including A Silicate Glass Structure and Method of Manufacturing A Semiconductor Device - A semiconductor device includes a semiconductor body including a first surface. The semiconductor device further includes a continuous silicate glass structure over the first surface. A first part of the continuous glass structure over an active area of the semiconductor body includes a first composition of dopants that differs from a second composition of dopants in a second part of the continuous glass structure over an area of the semiconductor body outside of the active area. | 11-21-2013 |
20130307059 | Semiconductor Device and Method for Manufacturing a Semiconductor Device - A semiconductor device includes a first region of a first conductivity type and a body region of a second conductivity type, the first conductivity type being different from the second conductivity type. The body region is disposed on a side of a first surface of the semiconductor substrate. The semiconductor device further includes a plurality of trenches arranged in the first surface of the substrate, the trenches extending in a first direction having a component perpendicular to the first surface. Doped portions of the second conductivity type are adjacent to a lower portion of a sidewall of the trenches. The doped portions are electrically coupled to the body region via contact regions. The semiconductor device further includes a gate electrode disposed in an upper portion of the trenches. | 11-21-2013 |
20130307058 | Semiconductor Devices Including Superjunction Structure and Method of Manufacturing - A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. A superjunction structure in the semiconductor body includes drift regions of a first conductivity type and compensation structures alternately disposed in a first direction parallel to the first surface. Each of the charge compensation structures includes a first semiconductor region of a second conductivity type complementary to the first conductivity type and a first trench including a second semiconductor region of the second conductivity type adjoining the first semiconductor region. The first semiconductor region and the first trench are disposed one after another in a second direction perpendicular to the first surface. | 11-21-2013 |
20130307031 | SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR STRUCTURE, AND METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE - According to an embodiment, a semiconductor structure includes a first monocrystalline semiconductor portion having a first lattice constant in a reference direction; a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion; and a metal layer formed on and in contact with the second monocrystalline semiconductor portion. | 11-21-2013 |
20130304958 | System and Method for Processing Device with Differentiated Execution Mode - In accordance with an embodiment of the present invention, a method of operating a system includes operating in a first operating mode to not permit access to an address range, receiving a priority interrupt (PI) signal. The method further includes operating in a second operating mode to permit access to the address range in response to receiving the PI signal. | 11-14-2013 |
20130299842 | Contact Structures for Compound Semiconductor Devices - A semiconductor device includes a semiconductor body including a plurality of compound semiconductor layers and a two-dimensional charge carrier gas channel region formed in one of the compound semiconductor layers. The semiconductor device further includes a contact structure disposed in the semiconductor body. The contact structure includes a metal region and a doped region. The metal region extends into the semiconductor body from a first side of the semiconductor body to at least the compound semiconductor layer which includes the channel region. The doped region is formed in the semiconductor body between the metal region and the channel region so that the channel region is electrically connected to the metal region through the doped region. | 11-14-2013 |
20130299841 | GaN-Based Optocoupler - An optocoupler includes a GaN-based photosensor disposed on a substrate and a GaN-based light source disposed on the same substrate as the GaN-based photosensor. A transparent material is interposed between the GaN-based photosensor and the GaN-based light source. The transparent material provides galvanic isolation and forms an optical channel between the GaN-based photosensor and the GaN-based light source. | 11-14-2013 |
20130285631 | Low-Dropout Voltage Regulator - A low-dropout voltage regulator includes a power transistor configured to receive an input voltage and to provide a regulated output voltage at an output voltage node. The power transistor includes a control electrode configured to receive a driver signal. A reference circuit is configured to generate a reference voltage. A feedback network is coupled to the power transistor and is configured to provide a first feedback signal and a second feedback signal. The first feedback signal represents the output voltage and the second feedback signal represents an output voltage gradient. An error amplifier is configured to receive the reference voltage and the first feedback signal representing the output voltage. The error amplifier is configured to generate the driver signal dependent on the reference voltage and the first feedback signal. The error amplifier includes an output stage that is biased with a bias current responsive to the second feedback signal. | 10-31-2013 |
20130280879 | Method for Producing a Conductor Line - A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed. | 10-24-2013 |
20130278372 | Semiconductor Component with Coreless Transformer - A semiconductor component has integrated a coreless transformer with a first connection contact, a second connection contact, an electrically conductive spiral first coil, an electrically conductive first ring, and an electrically conductive second ring. The electrically conductive spiral first coil is electrically connected between the first connection contact and the second connection contact. The electrically conductive first ring surrounds the first coil and one or both of the first connection contact and the second connection contact. The electrically conductive second ring is arranged between the first coil and the first ring, electrically connected to the first coil, and surrounds the first coil and one or both of the first connection contact and the second connection contact. | 10-24-2013 |
20130271095 | Linear Voltage Regulator - A voltage regulator includes an output stage including a control terminal and a load path, with the load path coupled between the input terminal and the output terminal. The voltage regulator also includes a control circuit with an input stage, a first current mirror, and a second current mirror. The input stage includes a first control input configured to receive a first reference voltage, a second control input configured to receive a second reference voltage, a feedback input coupled to the output terminal, a first output terminal, and a second output terminal. The first current mirror includes a reference current path coupled between a first supply terminal and the first output terminal of the input stage, and an output current path coupled between the first supply terminal and the control terminal of the pass device. | 10-17-2013 |
20130256699 | Gate Overvoltage Protection for Compound Semiconductor Transistors - A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region. A gate is provided for controlling the channel region. The transistor device further includes a gate overvoltage protection device connected between the source and the gate, the gate overvoltage protection device including p-type and n-type silicon-containing semiconductor material. | 10-03-2013 |
20130254896 | Method to Detect Tampering of Data - A method to detect tampering includes constant acquiring of measurement raw data in a sensor unit; processing of measurement raw data of a defined time interval in a metrology unit, obtaining first measurement results; at least one of storing of the first measurement results and transmitting of the first measurement results to an authority at defined time instances via a communication channel; at least one of storing of a defined fraction of measurement raw data and transmitting of a defined fraction of measurement raw data to the authority in a random manner via the communication channel; processing of the measurement raw data of the defined time interval at the authority, obtaining second measurement results; and comparing the first and second measurement results of a time interval. | 09-26-2013 |
20130254881 | Method to Detect Tampering of Data - A method to detect tampering of data includes constant acquiring of raw measurement data in a sensor unit. The raw measurement data of a defined time interval is processed in a metrology unit to obtain first measurement results. The first measurement results are transmitted to an authority at defined time instances via a communication channel. A defined fraction of raw measurement data is transmitted to the authority in a random manner via the communication channel. The raw measurement data of the defined time interval is processed at the authority to obtain second measurement results. The first and second measurement results of a time interval are compared. | 09-26-2013 |
20130252423 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device and semiconductor device. One embodiment provides a semiconductor substrate with an active region and a margin region bordering on the active region. The spacer layer in the margin region is broken through at a selected location and at least part of the spacer layer is removed in the active region using a common process. The location is selected such that at least part of the semiconductor mesa structure is exposed and the spacer layer in the margin region is broken through to the conductive layer and not to the semiconductor substrate. | 09-26-2013 |
20130250627 | POWER CONVERTER WITH REDUCED POWER CONSUMPTION IN STANDBY MODE - In accordance with various embodiments a converter is provided, including: a transformer comprising a primary side and a secondary side; a primary side circuit arrangement coupled to the primary side of the transformer; a secondary side circuit arrangement coupled to the secondary side of the transformer, wherein the secondary side circuit arrangement is configured to provide at least one of an output voltage and an output current; a coupling component configured to provide information about at least one of the output voltage and the output current to the primary side circuit arrangement; a first energy supply configured to provide the coupling component with a first current; and second energy supply configured to provide the coupling component with a second current, wherein the second current is lower than the first current. | 09-26-2013 |
20130249602 | Semiconductor Arrangement with a Power Transistor and a High Voltage Device Integrated in a Common Semiconductor Body - A semiconductor arrangement includes a semiconductor body and a power transistor including a source region, a drain region, a body region and a drift region arranged in the semiconductor body, a gate electrode arranged adjacent to the body region and dielectrically insulated from the body region by a gate dielectric. The semiconductor arrangement further includes a high voltage device arranged within a well-like dielectric structure in the semiconductor body and comprising a further drift region. | 09-26-2013 |
20130249001 | Semiconductor Arrangement with a Superjunction Transistor and a Further Device Integrated in a Common Semiconductor Body - A semiconductor arrangement includes a semiconductor body and a power transistor arranged in a first device region of the semiconductor body. The power transistor includes at least one source region, a drain region, and at least one body region, at least one drift region of a first doping type and at least one compensation region of a second doping complementary to the first doping type, and a gate electrode arranged adjacent to the at least one body region and dielectrically insulated from the body region by a gate dielectric. The semiconductor arrangement also includes a further semiconductor device arranged in a second device region of the semiconductor body. The second device region includes a well-like structure of the second doping type surrounding a first semiconductor region of the first doping type. The further semiconductor device includes device regions arranged in the first semiconductor region. | 09-26-2013 |
20130248993 | Stress-Reduced Field-Effect Semiconductor Device and Method for Forming Therefor - A field-effect semiconductor device is provided. The field-effect semiconductor device includes a semiconductor body with a first surface defining a vertical direction. In a vertical cross-section the field-effect semiconductor device further includes a vertical trench extending from the first surface into the semiconductor body. The vertical trench includes a field electrode, a cavity at least partly surrounded by the field electrode, and an insulation structure substantially surrounding at least the field electrode. Further, a method for producing a field-effect semiconductor device is provided. | 09-26-2013 |
20130241685 | Method of Constructing Inductors and Transformers - An embodiment of the invention relates to an apparatus including a magnetic device and a related method. A multilayer substrate is constructed with a winding formed in a metallic layer, an electrically insulating layer above the metallic layer, and a via formed in the electrically insulating layer to couple the winding to a circuit element positioned on the multilayer substrate. A depression is formed in the multilayer substrate, and a polymer solution, preferably an epoxy, containing a ferromagnetic component such as nanocrystaline nickel zinc ferrite is deposited within a mold positioned on a surface of the multilayer substrate above the winding and in the depression. An integrated circuit electrically coupled to the winding may be located on the multilayer substrate. The multilayer substrate may be a semiconductor substrate or a printed wiring board, and the circuit element may be an integrated circuit formed on the multilayer substrate. | 09-19-2013 |
20130240987 | SEMICONDUCTOR FIELD EFFECT POWER SWITCHING DEVICE - A semiconductor device having a semiconductor body, a source metallization arranged on a first surface of the semiconductor body and a trench including a first trench portion and a second trench portion and extending from the first surface into the semiconductor body is provided. The semiconductor body further includes a pn-junction formed between a first semiconductor region and a second semiconductor region. The first trench portion includes an insulated gate electrode which is connected to the source metallization, and the second trench portion includes a conductive plug which is connected to the source metallization and to the second semiconductor region. | 09-19-2013 |
20130240986 | Semiconductor Device Including Charged Structure and Methods for Manufacturing A Semiconductor Device - A semiconductor device includes a trench region extending into a drift zone of a semiconductor body from a surface. The semiconductor device further includes a dielectric structure extending along a lateral side of the trench region, wherein a part of the dielectric structure is a charged insulating structure. The semiconductor device further includes a gate electrode in the trench region and a body region of a conductivity type other than the conductivity type of the drift zone. The charged insulating structure adjoins each one of the drift zone, the body region and the dielectric structure and further adjoins or is arranged below a bottom side of a gate dielectric of the dielectric structure. | 09-19-2013 |
20130240985 | Semiconductor Device Including Auxiliary Structure and Methods for Manufacturing A Semiconductor Device - A semiconductor device includes a trench region extending into a drift zone of a semiconductor body from a surface. The semiconductor device further includes a dielectric structure including a first step and a second step along a lateral side of the trench region. The semiconductor device further includes an auxiliary structure of a first conductivity type between the first step and the second step, a gate electrode in the trench region and a body region of a second conductivity type other than the first conductivity type of the drift zone. The auxiliary structure adjoins each one of the drift zone, the body region and the dielectric structure. | 09-19-2013 |
20130240955 | VERTICAL TRANSISTOR HAVING EDGE TERMINATION STRUCTURE - Described herein are embodiments of a vertical power transistor having drain and gate terminals located on the same side of a semiconductor body and capable of withstanding high voltages in the off-state, in particular voltages of more than 100V. | 09-19-2013 |
20130234297 | SEMICONDUCTOR DEVICE, WAFER ASSEMBLY AND METHODS OF MANUFACTURING WAFER ASSEMBLIES AND SEMICONDUCTOR DEVICES - A cavity is formed in a working surface of a substrate in which a semiconductor element is formed. A glass piece formed from a glass material is bonded to the substrate, and the cavity is filled with the glass material. For example, a pre-patterned glass piece is used which includes a protrusion fitting into the cavity. Cavities with widths of more than 10 micrometers are filled fast and reliably. The cavities may have inclined sidewalls. | 09-12-2013 |
20130234239 | Charge Compensation Semiconductor Device - A semiconductor device includes a semiconductor body having a first surface defining a vertical direction and a source metallization arranged on the first surface. In a vertical cross-section the semiconductor body further includes: a drift region of a first conductivity type; at least two compensation regions of a second conductivity type each of which forms a pn-junction with the drift region and is in low resistive electric connection with the source metallization; a drain region of the first conductivity type having a maximum doping concentration higher than a maximum doping concentration of the drift region, and a third semiconductor layer of the first conductivity type arranged between the drift region and the drain region and includes at least one of a floating field plate and a floating semiconductor region of the second conductivity type forming a pn-junction with the third semiconductor layer. | 09-12-2013 |