Interuniversitair Microelektronica Centrum vzw (IMEC) Patent applications |
Patent application number | Title | Published |
20120034787 | Defect Etching of Germanium - The present invention provides an etching solution for revealing defects in a germanium layer, a method for revealing defects in a germanium layer using such an etching solution and to a method for making such an etching solution. The etching solution according to embodiments of the present invention is able to exhibit an etch rate of between 4 nm·min | 02-09-2012 |
20110183509 | Non-Volatile Memory Device with Improved Immunity to Erase Saturation and Method for Manufacturing Same - A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate. | 07-28-2011 |
20100084632 | NANOSTRUCTURE INSULATED JUNCTION FIELD EFFECT TRANSISTOR - A novel nanostructure device operating in Junction Field Effect Transistor (JFET) mode is provided that avoids the majority of the carriers that interact with the interface (e.g. surface roughness, high-k scattering). | 04-08-2010 |
20100012977 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. In one aspect, the device has a first and second active layer on a substrate, the second active layer having a higher bandgap than the first active layer, being substantially Ga-free and including at least Al | 01-21-2010 |
20100002236 | METHOD FOR DETERMINING THE DOPING PROFILE OF A PARTIALLY ACTIVATED DOPED SEMICONDUCTOR REGION - A method is disclosed for determining the inactive doping concentration of a semiconductor region using a PMOR method. In one aspect, the method includes providing two semiconductor regions having substantially the same known as-implanted concentration but known varying junction depths. The method includes determining on one of these semiconductor regions the as-implanted concentration. The semiconductor regions are then partially activated. PMOR measures are then performed on the partially activated semiconductor regions to measure (a) the signed amplitude of the reflected probe signal as function of junction depth and (b) the DC probe reflectivity as function of junction depth. The method includes extracting from these measurements the active doping concentration and then calculating the inactive doping concentration using the determined total as-implanted concentration and active doping concentration. The method may also include extracting thermal diffusivity, refraction index, absorption coefficient, and/or SRHF lifetime from these measurements. | 01-07-2010 |
20090317639 | METHOD FOR MANUFACTURING A STRETCHABLE ELECTRONIC DEVICE - A method for manufacturing a stretchable electronic device is disclosed. In one aspect, the device comprises at least one electrically conductive channel connecting at least two components of the device. The method comprises forming the channel by laser-cutting a flexible substrate into a predetermined geometric shape. | 12-24-2009 |
20090313730 | METHOD FOR COST-EFFICIENT MANUFACTURING DIAMOND TIPS FOR ULTRA-HIGH RESOLUTION ELECTRICAL MEASUREMENTS AND DEVICES OBTAINED THEREOF - An atomic force microscopy probe configuration and a method for manufacturing the same are disclosed. In one aspect, the probe configuration includes a cantilever, and a planar tip attached to the cantilever. The cantilever only partially overlaps the planar tip, and extends along a longitudinal direction thereof. The planar tip is of a two-dimensional geometry having at least one corner remote from the cantilever, which corner during use contacts a surface to be scanned. | 12-17-2009 |
20090283835 | METHOD FOR FABRICATING A DUAL WORKFUNCTION SEMICONDUCTOR DEVICE AND THE DEVICE MADE THEREOF - A method for manufacturing a dual workfunction semiconductor device and the device made thereof are disclosed. In one aspect, the method includes manufacturing a first transistor in a first region and a second transistor in a second region of a substrate, the first transistor including a first gate stack, the first gate stack having a first gate dielectric capping layer and a first metal gate electrode layer. The second gate stack is similar to the first gate stack. The method includes applying a first thermal budget to the first gate dielectric capping layer and a second thermal budget to the second gate dielectric capping material to tune the workfunction of the first and second gate stack, the first thermal budget being smaller than the second thermal budget such that after the thermal treatment the first and the second gate stack have different work functions. | 11-19-2009 |
20090283756 | SCALABLE QUANTUM WELL DEVICE AND METHOD FOR MANUFACTURING THE SAME - A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap. | 11-19-2009 |
20090273010 | REMOVAL OF IMPURITIES FROM SEMICONDUCTOR DEVICE LAYERS - A method for removing impurities from at least one semiconductor device layer during manufacturing of a semiconductor device is disclosed. The semiconductor device layer has a compound semiconductor material and/or germanium. Each heating process performed during the manufacturing of the semiconductor device after provision of the semiconductor device layer has a low thermal budget determined by temperatures equal to or lower than about 900° C. and time periods equal to or lower than about 5 minutes. In one aspect, the method includes providing a germanium gettering layer with a higher solubility for the impurities than the semiconductor device layer. The germanium gettering layer is provided at least partly in direct or indirect contact with the at least one semiconductor device layer, such that impurities can diffuse from the at least one semiconductor device layer to the germanium gettering layer. | 11-05-2009 |
20090272976 | METHOD FOR PRODUCING NMOS AND PMOS DEVICES IN CMOS PROCESSING - A method for producing one or more nMOSFET devices and one or more pMOSFET devices on the same semiconductor substrate is disclosed. In one aspect, the method relates to the use of a single activation anneal that serves for both Si NMOS and Ge pMOS. By use of a solid phase epitaxial regrowth (SPER) process for the Si nMOS, the thermal budget for the Si NMOS can be lowered to be compatible with Ge pMOS. | 11-05-2009 |
20090261424 | METHOD FOR FABRICATING A DUAL WORKFUNCTION SEMICONDUCTOR DEVICE AND THE DEVICE MADE THEREOF - A dual workfunction semiconductor device and a device made thereof is disclosed. In one aspect, the device includes a first gate stack in a first region and a second gate stack in a second region. The first gate stack has a first effective workfunction, and the second gate stack has a second effective workfunction different from the first effective workfunction. The first gate stack includes a first gate dielectric capping layer, a gate dielectric host layer, a first metal gate electrode layer, a barrier metal gate electrode, a second gate dielectric capping layer, and a second metal gate electrode. The second gate stack includes a gate dielectric host layer, a first metal gate electrode, a second gate dielectric capping layer, and a second metal gate electrode. | 10-22-2009 |
20090243103 | SYNTHESIS OF ZEOLITE CRYSTALS AND FORMATION OF CARBON NANOSTRUCTURES IN PATTERNED STRUCTURES - A method is provided for incorporating zeolite crystals in patterned structures, the zeolite crystals having pores (channels) with an orientation which is defined by the topology of the zeolite crystal type and the geometry of the patterned structure, resulting in pores parallel with the length axis of the patterned structures. The patterned structures may be vias (vertical contacts) and trenches (horizontal lines) in a semiconductor substrate. These zeolite crystals can advantageously be used for dense and aligned nanocarbon growth or in other words growth of carbon nanostructures such as carbon nanotubes (CNT) within the pores of the zeolite structure. The growth of CNT is achieved within the porous structure of the zeolite crystals whereby the pores can be defined as confined spaces (channels) in nanometer dimensions acting as a micro-reactor for CNT growth. A method for growing carbon nanostructures within zeolite crystals is also provided, by adding, after creation of the zeolite crystals, a novel compound within the porous structure of the zeolite crystals whereby said novel compound is acting as a carbon source to create the carbon nanostructures. The improved growth method gives a significantly higher carbon density (yield) compared to state of the art techniques. | 10-01-2009 |
20090218702 | METHODS FOR BONDING AND MICRO-ELECTRONIC DEVICES PRODUCED ACCORDING TO SUCH METHODS - One inventive aspect is related to a method of bonding two elements and micro-electronic devices produced according to such methods. In one aspect, a micro-electronic device includes a first and a second element, bonded together by a joining structure. The joining structure has a first micropattern portion, a second micropattern portion, and a joining portion in between the first and second micropattern portions. The first and second micropattern portions are made of cobalt. The joining portion includes intermetallic compounds of cobalt and tin (Sn). | 09-03-2009 |
20090217224 | METHOD AND SYSTEM FOR MASK DESIGN FOR DOUBLE PATTERNING - A method and system for setting up multiple patterning lithographic processing of a pattern in a single layer is disclosed. The multiple patterning lithographic processing comprises a first and second patterning step. In one aspect, a method includes, for at least one process condition, obtaining values for a metric expressing a splitting correlated process quality as function of design parameters of a pattern and/or split parameters for the multiple patterning lithographic processing. The method also includes evaluating the values of the metric and selecting based thereon design and split parameters considering the process condition. The method may further include deriving design and/or split guidelines for splitting patterns to be processed using multiple patterning lithographic processing based on the evaluation. | 08-27-2009 |
20090215276 | PHOTOELECTROCHEMICAL CELL WITH CARBON NANOTUBE-FUNCTIONALIZED SEMICONDUCTOR ELECTRODE - Photoelectrochemical cells and methods are provided, in particular, to the functionalization of semiconductor surfaces such that its semiconducting and light generating properties are maintained and the surface becomes stable in wet environments. In particular the preferred embodiments relate to unstable semiconductor materials which have photocurrent generating properties, and to methods for the functionalization of surfaces with metallic carbon nanotubes (CNTs). | 08-27-2009 |
20090215275 | Defect Etching of Germanium - The present invention provides an etching solution for revealing defects in a germanium layer, a method for revealing defects in a germanium layer using such an etching solution and to a method for making such an etching solution. The etching solution according to embodiments of the present invention is able to exhibit an etch rate of between 4 nm·min | 08-27-2009 |
20090191674 | AIGaN/GaN HIGH ELECTRON MOBILITY TRANSISTOR DEVICES - The present invention recites a new method for manufacturing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET devices or MESFET devices, grown by Metal-Organic Vapor Phase Expitaxy, with higher performance (power), by covering the surface with a thin SiN layer on the top AlGaN layer, in the reactor where the growth takes place at high temperature, prior cooling down the structure and loading the sample out of the reactor, as well as a method to produce some HEMT transistors on those heterostructures, by depositing the contact on the surface without any removal of the SiN layer by MOCVD. The present invention recites also a device. | 07-30-2009 |
20090184376 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function. | 07-23-2009 |
20090184358 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE MADE THEREOF - A method for fabricating a semiconductor device and the device made thereof are disclosed. In one aspect, the method includes providing a substrate comprising a semiconductor material. The method further includes patterning at least one fin in the substrate, the fin comprising a top surface, at least one sidewall surface, and at least one corner. A supersaturation of point defects is created in the at least one fin. The at least one fin is annealed and then cooled down such that semiconductor atoms of the semiconductor material migrate via the point defects. | 07-23-2009 |
20090175381 | DIGITAL RECEIVER FOR REACTIVE RADIO - A digital receiver is disclosed. In one aspect, the receiver includes a receiving module for receiving packetized data. The receive may further include a first processing module for packet detection having a first programmable processor. The receiver may further include a second processing module for demodulation and packet decoding having a second programmable processor. The receiver may further include a first digital receive controller having a third processor arranged for being notified of detection of data by the first processing module and for activating the second processing module. | 07-09-2009 |
20090174003 | DUAL WORK FUNCTION DEVICE WITH STRESSOR LAYER AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method relates to providing a substrate with a first and a second region. A gate dielectric is formed overlying the first and the second region. A metal gate layer is formed overlying the gate dielectric on the first and the second region. The metal gate layer has a first (as-deposited) work function that can be modified upon inducing strain thereon. The method further relates to selecting a first strain which induces a first pre-determined work function shift (ΔWF1) in the first (as-deposited) work function of the metal gate layer on the first region and selectively forming a first strained conductive layer overlying the metal gate layer on the first region, the first strained conductive layer exerting the selected first strain on the metal gate layer. | 07-09-2009 |
20090173359 | PHOTON INDUCED CLEANING OF A REACTION CHAMBER - The present invention provides a method for in-situ cleaning of walls of a reaction chamber, e.g. reactive ion etching chamber, to remove contamination, e.g. copper comprising contamination from the walls. The method comprises converting the contamination, e.g. copper comprising contamination into a halide compound, e.g. copper halide compound and exposing the halide compound, e.g. copper halide compound to a photon comprising ambient, thereby initiating formation of volatile halide products, e.g. volatile copper halide products. The method furthermore comprises removing the volatile halide products, e.g. volatile copper halide products from the reaction chamber to avoid saturation of the volatile halide products, e.g. volatile copper halide products in the reaction chamber in order to avoid re-deposition of the volatile halide products, e.g. volatile copper halide products to the walls of the reaction chamber. | 07-09-2009 |
20090163143 | METHOD FOR DETERMINING AND COMPENSATING TRANSCEIVER NON-IDEALITIES - A method for estimating transceiver non-idealities is disclosed. In one aspect, the method comprises generating a preamble comprising multiple sets of known training sequences with a synchronization part preceding an estimation part. The training sequences in the estimation part comprises at least two sequences which are (i) complementary Golay sequence pairs and (ii) selected to satisfy a predetermined correlation relationship chosen for estimation of a first non-ideality characteristic. A first estimate of a non-ideality characteristic is determined on the basis of the known training sequences of the synchronization part of the received preamble. The estimation part of the received preamble is compensated by this estimate. Another non-ideality characteristic is determined by the compensated estimation part, exploiting the predetermined correlation relationship. | 06-25-2009 |
20090159972 | METHOD OF FABRICATING MULTI-GATE SEMICONDUCTOR DEVICES WITH IMPROVED CARRIER MOBILITY - A method of fabricating a multi-gate device is disclosed. In one aspect, the method includes providing a substrate having a first semiconductor layer with a first carrier mobility enhancing parameter, an insulating layer, a second semiconductor layer with a second carrier mobility enhancing parameter different from the first carrier mobility enhancing parameter. A first and second dielectric layer are then provided on the substrate. A first trench is formed in a first active region through the dielectric layers, the second semiconductor layer and the buried insulating layer. A first fin is formed in the first trench, protruding above the first dielectric layer and having the first carrier mobility enhancing parameter. A second trench is formed in a second active region through the dielectric layers. A second fin is formed in the second trench, protruding above the first dielectric layer and having the second mobility enhancing parameter. | 06-25-2009 |
20090151030 | DUAL TIP ATOMIC FORCE MICROSCOPY PROBE AND METHOD FOR PRODUCING SUCH A PROBE - One inventive aspect is related to an atomic force microscopy probe. The probe comprises a tip configuration with two probe tips on one cantilever arm. The probe tips are electrically isolated from each other and of approximately the same height with respect to the cantilever arm. The outer surface of the tip configuration has the shape of a body with a base plane and an apex. The body is divided into two sub-parts by a gap located approximately symmetrically with respect to the apex and approximately perpendicular to the base plane. Another inventive aspect related to methods for producing such an AFM probe. | 06-11-2009 |
20090137102 | METHOD FOR MAKING QUANTUM DOTS - A method for forming at least one quantum dot at least one predetermined location on a substrate is disclosed. In one aspect, the method comprises providing a layer of semiconductor material on an insulating layer on the substrate. The layer of semiconductor material is patterned so as to provide at least one line of semiconductor material having a width (w | 05-28-2009 |
20090134453 | Non-Volatile Memory Device with Improved Immunity to Erase Saturation and Method for Manufacturing Same - A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate. | 05-28-2009 |
20090112344 | DESIGN OPTIMIZATION - A method for optimizing a design for a device is disclosed. Such an optimization is performed with respect to a predetermined metric, e.g. device speed, area, power consumption or yield. In one aspect, the method comprises obtaining a design for a device. The design comprises design components. The method also comprises determining from the design components at least one group of first design components that has a higher sensitivity to the predetermined metric than second design components. The first design components may be on the critical path in the design. The method further comprises tuning the first design components and the technology for manufacturing the first design components thus reducing the variability of the first design components and obtaining an optimized design with respect to the predetermined metric. | 04-30-2009 |
20090107704 | COMPOSITE SUBSTRATE - A composite substrate is disclosed. In one aspect, the substrate has a stretchable and/or flexible material. The substrate may further have patterned features embedded in the stretchable and/or flexible material. The patterned features have one or more patterned conducting layers. | 04-30-2009 |
20090103069 | DETECTION OF CONTAMINATION IN EUV SYSTEMS - A sensor for sensing contamination in an application system is disclosed. In one aspect, the sensor comprises a capping layer. The sensor is adapted to cause a first reflectivity change upon initial formation of a first contamination layer on the capping layer when the sensor is provided in the system. The first reflectivity change is larger than an average reflectivity change upon formation of a thicker contamination layer on the capping layer and larger than an average reflectivity change upon formation of an equal contamination on the actual mirrors of the optics of the system. | 04-23-2009 |
20090090971 | MOSFET DEVICES AND METHODS FOR MAKING THEM - A semiconductor device is disclosed. The device comprises a first MOSFET transistor. The transistor comprises a substrate, a first high-k dielectric layer upon the substrate, a first dielectric capping layer upon the first high-k dielectric, and a first gate electrode made of a semiconductor material of a first doping level and a first conductivity type upon the first dielectric capping layer. The first dielectric capping layer comprises Scandium. | 04-09-2009 |
20090085167 | Methods for Forming Metal-Germanide Layers and Devices Obtained Thereby - The present invention is related to the field of semiconductor processing and, more particularly, to the formation of low resistance layers on germanium substrates. One aspect of the present invention is a method comprising: providing a substrate on which at least one area of a germanium layer is exposed; depositing over the substrate and said germanium area a metal, e.g., Co or Ni; forming over said metal, a capping layer consisting of a silicon oxide containing layer, of a silicon nitride layer, or of a tungsten layer, preferably of a SiO | 04-02-2009 |
20090079494 | METHOD OF OPERATING QUANTUM-MECHANICAL MEMORY AND COMPUTATIONAL DEVICES - A method of operating a quantum system comprising computational elements, including an insulated ring of superconductive material, and semi-closed rings used as an interface between the computational elements and the external world, is disclosed. In one aspect, the method comprises providing an electrical signal, e.g. a current, in an input ring magnetically coupled to a computational element, which generates a magnetic field in the computational element and sensing the change in the current and/or voltage of an output element magnetically coupled to the computational element. The electrical input signal can be an AC signal or a DC signal. The computational element is electromagnetically coupled with other adjacent computational elements and/or with the interface elements. The corresponding magnetic flux between the computational elements and/or the interface elements acts as an information carrier. Ferromagnetic cores are used to improve the magnetic coupling between adjacent elements. | 03-26-2009 |
20090072222 | METHOD FOR FORMING CATALYST NANOPARTICLES FOR GROWING ELONGATED NANOSTRUCTURES - Preferred embodiments provide a method for forming at least one catalyst nanoparticle on at least one sidewall of a three-dimensional structure on a main surface of a substrate, the main surface lying in a plane and the sidewall of the three-dimensional structure lying in a plane substantially perpendicular to the plane of the main surface of the substrate. The method comprises obtaining a three-dimensional structure on the main surface, the three-dimensional structure comprising catalyst nanoparticles embedded in a non-catalytic matrix and selectively removing at least part of the non-catalytic matrix at the sidewalls of the three-dimensional structure to thereby expose at least one catalyst nanoparticle. According to preferred embodiments a method is also provided for forming at least one elongated nanostructure, such as e.g. a nanowire or carbon nanotube, using the catalyst nanoparticles formed by the method according to preferred embodiments as a catalyst. The methods according to preferred embodiments may be used in, for example, semiconductor processing. The methods according to preferred embodiments are scalable and fully compatible with existing semiconductor processing technology. | 03-19-2009 |
20090070552 | RECONFIGURABLE MULTI-PROCESSING COARSE-GRAIN ARRAY - A signal processing device adapted for simultaneous processing of at least two process threads in a multi-processing manner is disclosed. In one embodiment, the device comprises a plurality of functional units capable of executing word- or subword-level operations on data. The device further comprises means for interconnecting the plurality of functional units, the means for interconnecting supporting a plurality of dynamically switchable interconnect arrangements, and at least one of the interconnect arrangements interconnects the plurality of functional units into at least two non-overlapping processing units each with a pre-determined topology. The device further comprises at least two control modules each assigned to one of the processing units. | 03-12-2009 |
20090068768 | QUANTIFICATION OF HYDROPHOBIC AND HYDROPHILIC PROPERTIES OF MATERIALS - A non-destructive and simple analytical method is provided which allows in situ monitoring of plasma damage during the plasma processing such as resist stripping. If a low-k film is damaged during plasma processing, one of the reaction products is water, which is remained adsorbed onto the low-k film (into pores), if the temperature is lower than 100-150 C. A plasma (e.g. He) that emits high energy EUV photons (E>20 eV) which is able to destruct water molecules forming electronically excited oxygen atoms is used to detect the adsorbed water. The excited oxygen is detected from optical emission at 777 nm. Therefore, the higher the adsorbed water concentration (higher damage), a more intensive (oxygen) signal is detected. Therefore, intensity of oxygen signal is a measure of plasma damage in the previous strip step. The proposed analytical method can be performed in-situ immediately after plasma processing and most preferred the optical emission of oxygen radicals is monitored during the de-chucking step in the plasma chamber. | 03-12-2009 |
20090065025 | CLEANING OF PLASMA CHAMBER WALLS USING NOBLE GAS CLEANING STEP - An improved reaction chamber cleaning process is provided for removing water residues that makes use of noble-gas plasma reactions. The method is easy applicable and may be combined with standard cleaning procedure. A noble-gas plasma (e.g. He) that emits high energy EUV photons (E>20 eV) which is able to destruct water molecules to form electronically excited oxygen atoms is used to remove the adsorbed water. | 03-12-2009 |
20090031268 | METHODS FOR CHARACTERIZATION OF ELECTRONIC CIRCUITS UNDER PROCESS VARIABILITY EFFECTS - A method for determining an estimate of statistical properties of an electronic system comprising individual components subject to manufacturing process variability is disclosed. In one aspect, the method comprises obtaining statistical properties of the performance of individual components of the electronic system, obtaining information about execution of an application on the system, simulating execution of the application based on the obtained information about execution of the application on the system for a simulated electronic system realization constructed by selecting individual components with the obtained statistical properties determining the delay and energy of the electronic system, and determining the statistical properties of the delay and energy of the electronic system. | 01-29-2009 |
20090024378 | SIMULATION METHOD FOR EFFICIENT CHARACTERIZATION OF ELECTRONIC SYSTEMS UNDER VARIABILITY EFFECTS - A method of determining the behavior of an electronic system comprising electronic components under variability is disclosed. In one aspect, the method comprises for at least one parameter of at least one of the electronic components, showing variability defining a range and a population of possible values within the range, each possible value having a probability of occurrence, thereby defining an input domain. The method further comprises selecting inputs randomly from the input domain, wherein the probability to sample (PTS) is obtained from the probability of occurrence (PTOIR). The method further comprises performing simulation to obtain the performance parameters of the electronic system, thereby defining an output domain sample. The method further comprises aggregating results of the individual computations into the parameter/variability of the electronic system and assigning a frequency of occurrence (FoO) to the resulting sample, the parameter variability and the frequency of occurrence defining the behavior. | 01-22-2009 |
20090020821 | DUAL WORKFUNCTION SEMICONDUCTOR DEVICE - A dual workfunction semiconductor device which comprises a first and second control electrode comprising a metal-semiconductor compound, e.g. a silicide or a germanide, and a dual workfunction semiconductor device thus obtained are disclosed. In one aspect, the method comprises forming a blocking region for preventing diffusion of metal from the metal-semiconductor compound of the first control electrode to the metal-semiconductor compound of the second control electrode, the blocking region being formed at a location where an interface between the first and second control electrodes is to be formed or is formed. By preventing metal to diffuse from the one to the other control electrode the constitution of the metal-semiconductor compounds of the first and second control electrodes may remain substantially unchanged during e.g. thermal steps in further processing of the device. | 01-22-2009 |
20090020786 | SEMICONDUCTOR DEVICE - A method for forming a semiconductor device on a substrate having a first major surface lying in a plane and the semiconductor device are disclosed. In one aspect, the method comprises, after patterning the substrate to form at least one structure extending from the substrate in a direction substantially perpendicular to a major surface of the substrate, forming locally modified regions at locations in the substrate not covered by the structure, thus locally increasing etching resistance of these regions. Forming locally modified regions may prevent under-etching of the structure during further process steps in the formation of the semiconductor device. | 01-22-2009 |
20090011604 | PHOTON INDUCED REMOVAL OF COPPER - Preferred embodiments provide a method for removing at least part of a copper comprising layer from a substrate, the substrate comprising at least a copper comprising surface layer. The method comprises in a first reaction chamber converting at least part of the copper comprising surface layer into a copper halide surface layer and in a second reaction chamber removing at least part of the copper halide surface layer by exposing it to a photon comprising ambient, thereby initiating formation of volatile copper halide products. During exposure to the photon comprising ambient, the method furthermore comprises removing the volatile copper halide products from the second reaction chamber to avoid saturation of the volatile copper halide products in the second reaction chamber. The method according to preferred embodiments may be used to pattern copper comprising layers. For example, the method according to preferred embodiments may be used to form copper comprising interconnect structures in a semiconductor device. | 01-08-2009 |
20090011147 | PHOTON INDUCED FORMATION OF METAL COMPRISING ELONGATED NANOSTRUCTURES - The preferred embodiments provide a method for forming at least one metal comprising elongated nanostructure on a substrate. The method comprises exposing a metal halide compound surface to a photon comprising ambient to initiate formation of the at least one metal comprising elongated nanostructure. The preferred embodiments also provide metal comprising elongated nanostructures obtained by the method according to preferred embodiments. | 01-08-2009 |
20080317062 | METHOD FOR CONFIGURING MUTLI-CHANNEL COMMUNICATION - A method of configuring communication with a plurality of non-overlapping channels and between communication units with first communication units and second communication units is disclosed. The first communication units are privileged with respect to the second communication units, the second communication units having dynamically adaptable transceivers enabling channel switching, at least one of the second communication units being within the communication range of one of the first communication units. In one aspect, the method comprises determining information on the availability of the channels of the communication system for communication by the second communication units, based at least in part on information regarding whether the first communication units are active or not on the channels. The method further comprises selecting based on the information which channels to use for communication by the second communication units and adapting the second communication units transceivers for data communication via the selected channels. | 12-25-2008 |
20080301691 | METHOD FOR IMPROVING RUN-TIME EXECUTION OF AN APPLICATION ON A PLATFORM BASED ON APPLICATION METADATA - A method for improving run-time execution of an application on a platform based on application metadata is disclosed. In one embodiment, the method comprises loading a first information in a standardized predetermined format describing characteristics of at least one of the applications. The method further comprises generating the run-time manager, based on the first information, the run-time manager comprising at least two run-time sub-managers, each handling the management of a different resource. The information needed to generate the two run-time sub-managers is at least partially shared. | 12-04-2008 |
20080297189 | MOBILITY MEASUREMENTS OF INVERSION CHARGE CARRIERS - A method and device for determining the quality of the interface surface between a layer of a dielectric material and the top surface of the semiconductor substrate are disclosed. In one aspect, the method comprises providing a semiconductor substrate with a top surface whereon a layer of a dielectric material is deposited thereby forming an interface surface, the surface of the layer of the dielectric material being or not in direct contact with the semiconductor substrate defining a top surface. A charge is then applied on a dedicated area of the top surface. A voltage Vs is measured on the top surface. The dedicated area is illuminated to define an illuminated spot. The photovoltage is measured inside and outside the determined illuminated spot during the illumination of the area. | 12-04-2008 |
20080294882 | DISTRIBUTED LOOP CONTROLLER ARCHITECTURE FOR MULTI-THREADING IN UNI-THREADED PROCESSORS - In one aspect, a virtually multi-threaded distributed instruction memory hierarchy that can support the execution of multiple incompatible loops in parallel is disclosed. In addition to regular loops, irregular loops with conditional constructs and nested loops can be mapped. The loop buffers are clustered, each loop buffer having its own local controller, and each local controller is responsible for indexing and regulating accesses to its loop buffer. | 11-27-2008 |
20080285637 | DEVICE AND METHOD FOR CALIBRATING MIMO SYSTEMS - A device and method for calibrating MIMO systems are disclosed. In one aspect, a calibration circuit comprises at least a first and a second input/output port, each arranged for being connected to a different transmitter/receiver pair of a multiple input multiple output (MIMO) system. The circuit further comprises at least a third and a fourth input/output port, each arranged for being connected to a different antenna. The circuit further comprises an attenuator having a first attenuator port and a second attenuator port. The circuit further comprises a first and a second non-reciprocal switch, the first switch being arranged for establishing a connection between the first input/output port and either the third input/output port or the first attenuator port, and the second switch arranged for establishing a connection between the second input/output port and either the fourth input/output port or the second attenuator port. | 11-20-2008 |
20080284424 | SPIN DETECTION DEVICE AND METHODS FOR USE THEREOF - Embodiments of the invention are related to methods for and devices for performing electrical spin detection. A method for spin detection of charged carriers having a spin and forming a flux in a medium is disclosed, the method comprises measuring a first current on a first contact on the medium that has a first spin selectivity, measuring a second current on a second contact on the medium that has a second spin selectivity, comparing the first measured current and the second measured current, and deriving the average or statistically relevant spin state of the flux of charge carriers. Corresponding devices are disclosed. | 11-20-2008 |
20080277285 | BIPOLAR ELECTROLESS PROCESSING METHODS - A bipolar photo-electrochemical process is disclosed for electroless deposition (referred to as photo Bi-OCD) of a metallic compound onto the top surface of a semiconducting substrate whereby differential illumination of the front side of the substrate versus the back side of the substrate provides a driving force to separate the cathodic and anodic partial reactions leading to high yield deposition of the metallic compound. A selective photo Bi-OCD process is further disclosed whereby the top surface of the substrate is at least partly covered with an insulating pattern such that the deposition of the metallic compound takes place selectively into the openings of the pattern. | 11-13-2008 |
20080267087 | GATEWAY WITH IMPROVED QoS AWARENESS - A device and method for exchanging data frames are disclosed. In one aspect, the device exchanges data between a WAN and one or more LAN segments in an optimized way leading to a better quality of experience for the user. The device comprises an interface exchanging data frames over an access network, at least a first and second subnet interface exchanging data frames and arranged for being coupled to a network, a memory storing classification rules, a classification agent extracting information from an incoming data frame and applying the rules to the extracted information to determine the interface via which the incoming data frame is to be forwarded, and a Quality of Service monitoring agent for retrieving Quality of Service information from the subnet interfaces and dynamically updating the classification rules according to the QoS information. | 10-30-2008 |
20080265380 | METHOD FOR FABRICATING A HIGH-K DIELECTRIC LAYER - One inventive aspect relates to a method for fabricating a high-k dielectric layer. The method comprises depositing onto a substrate a layer of a high-k dielectric material having a first thickness. The high-k dielectric material has a bulk density value and the first thickness is so that the high-k dielectric layer has a density of at least the bulk density value of the high-k dielectric material minus about 10%. The method further comprises thinning the high-k dielectric layer to a second thickness. Another inventive aspect relates to a semiconductor device comprising a high-k dielectric layer as fabricated by the method. | 10-30-2008 |
20080263530 | METHOD AND SYSTEM FOR AUTOMATED CODE CONVERSION - A method and system for converting application code into optimized application code or into execution code suitable for execution on a computation engine with an architecture comprising at least a first and a second level of data memory units are disclosed. In one aspect, the method comprises obtaining application code, the application code comprising data transfer operations between the levels of memory units. The method further comprises converting at least a part of the application code. The converting of application code comprises scheduling of data transfer operations from a first level of memory units to a second level of memory units such that accesses of data accessed multiple times are brought closer together in time than in the original code. The converting of application code further comprises, after the scheduling of the data transfer operations, deciding on layout of the data in the second level of memory units to improve the data layout locality such that data which is accessed closer together in time is also brought closer together in the layout than in the original code. | 10-23-2008 |
20080252293 | DETECTION OF RESONANT TAGS BY ULTRA-WIDEBAND (UWB) RADAR - A detection system having a receiver for detecting a material having a magnetic resonance response to illumination by pulses of ultra-wideband (UWB) electromagnetic radiation is disclosed. The receiver comprises a detector for detecting the pulses after they have interacted with the material, and a discriminator arranged to identify in the detected pulses the magnetic resonance response of the material. By scanning an item tagged with a tag having a material having a magnetic resonant response, by illuminating the item with UWB pulses and identifying in detected pulses the magnetic resonance response of the material, items can be located, imaged, or activated. The magnetic resonance response of the tag can cause activation of the tag. The tag can have a magnetic resonance response arranged to provide an identifiable magnetic resonance signature such that different tags can be identified and distinguished by their signatures. | 10-16-2008 |
20080247468 | METHOD AND SYSTEM FOR PERFORMING RATE CONTROL ADAPTED TO CHANNEL CONDITIONS - A method and system for determining in real time the instantaneous output rate of a low delay video frame encoder/application for encoding a video frame to be transmitted are disclosed. The video frame encoder provides its output for wireless transmission over a telecommunication channel. In one aspect, a method comprises providing an estimate of the instantaneous channel conditions under which the video frame will be transmitted. The method further comprises determining the instantaneous output rate by selecting a high output rate when the channel conditions considered acceptable and selecting a low output rate when the channel conditions are considered unacceptable. | 10-09-2008 |
20080224224 | TUNNEL FIELD-EFFECT TRANSISTOR WITH GATED TUNNEL BARRIER - A tunnel field effect transistor (TFET) is disclosed. In one aspect, the transistor comprises a gate that does not align with a drain, and only overlap with the source extending at least up to the interface of the source-channel region and optionally overlaps with part of the channel. Due to the shorter gate, the total gate capacitance is reduced, which is directly reflected in an improved switching speed of the device. In addition to the advantage of an improved switching speed, the transistor also has a processing advantage (no alignment of the gate with the drain is necessary), as well as a performance improvement (the ambipolar behavior of the TFET is reduced). | 09-18-2008 |
20080224036 | METHOD AND DEVICE TO QUANTIFY ACTIVE CARRIER PROFILES IN ULTRA-SHALLOW SEMICONDUCTOR STRUCTURES - A method and device for determining, in a non-destructive way, at least the active carrier profile from an unknown semiconductor substrate are disclosed. In one aspect, the method comprises generating 2 | 09-18-2008 |
20080219573 | SYSTEM AND METHOD FOR MOTION DETECTION AND THE USE THEREOF IN VIDEO CODING - A system and method for motion detection and the use thereof in video coding are disclosed. In one aspect, a method of defining a region of motion within a video frame in a sequence of video frames comprises loading a current video frame and at least one reference video frame from the sequence, the reference video frame being different from the current video frame. The method further comprises applying filtering operations on the current and the reference video frame in order to obtain at least two scales of representation of the current and the reference video frame. The method further comprises determining for each of the scale representations a video-frame like representation of the structural changes between the current and the reference video frame. The method further comprises combining the video-frame like representations of different scales. The method further comprises determining one or more regions of motion from the combination. | 09-11-2008 |
20080214013 | Method for Removal of Bulk Metal Contamination from III-V Semiconductor Substrates - The invention provides a single-step method for removing bulk metal contamination from III-V semiconductor substrates. The method comprises immersing a metal contaminated III-V semiconductor substrate in a mixture of sulfuric acid and peroxide with a volume ratio of sulfuric acid to peroxide (e.g., hydrogen peroxide) between about 3:1 and about 9:1. After treating the III-V semiconductor substrates with the sulfuric acid-peroxide mixture, the bulk metal contamination may be substantially removed from the substrate while a surface roughness of the substrate after treatment of below about 0.5 nm RMS (2 μm×2 μm) is obtained. The invention further provides a method for manufacturing a semiconductor device by removing bulk metal contamination according to the single-step method of the invention before performing processing steps for forming the semiconductor device. | 09-04-2008 |