ATI Technologies, Inc. Patent applications |
Patent application number | Title | Published |
20130147814 | DYNAMIC LOAD BALANCING IN MULTIPLE VIDEO PROCESSING UNIT (VPU) SYSTEMS - Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames. | 06-13-2013 |
20120274655 | ANTIALIASING SYSTEM AND METHOD - A system and method for improved antialiasing in video processing is described herein. Embodiments include multiple video processors (VPUs) in a system. Each VPU performs some combination of pixel sampling and pixel center sampling (also referred to as multisampling and supersampling). Each VPU performs sampling on the same pixels or pixel centers, but each VPU creates samples positioned differently from the other VPUs corresponding samples. The VPUs each output frame data that has been multisampled and/or supersampled into a compositor that composites the frame data to produce an antialiased rendered frame. The antialiased rendered frame has an effectively doubled antialiasing factor. | 11-01-2012 |
20120215996 | WRITE DATA MASK METHOD AND SYSTEM - In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface. | 08-23-2012 |
20120120079 | COMPOSITING IN MULTIPLE VIDEO PROCESSING UNIT (VPU) SYSTEMS - The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels. | 05-17-2012 |
20120098840 | APPLYING NON-HOMOGENEOUS PROPERTIES TO MULTIPLE VIDEO PROCESSING UNITS (VPUs) - A multiprocessor system includes a plurality of special purpose processors that perform different portions of a related processing task. A set of commands that cause each of the processors to perform the portions of the related task are distributed, and the set of commands includes a predicated execution command that precedes other commands within the set of commands. It is determined whether commands subsequent to the predicated execution command are intended to be executed by a first processor or a second processor based on information in the predicated execution command and the set of commands includes all commands to be executed by each processor. | 04-26-2012 |
20100085365 | Dynamic Load Balancing in Multiple Video Processing Unit (VPU) Systems - Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames. | 04-08-2010 |
20100045871 | VIDEO LUMINANCE CHROMINANCE SEPARATION - The invention provides techniques for separating luma and chroma signal components in a composite SECAM video signal. During reception, the SECAM video signal is split into luma and chroma output. The amplitude of the chroma carrier is monitored during reception. If the chroma carrier amplitude is greater than a threshold, the value of the chroma output can be reduced. Also, if the chroma carrier amplitude is greater than another threshold, a portion of the chroma carrier can be added to the luma; or the trap band of the band-trap filter for extracting luma from the composite video can be reduced. The respective amount of the reduction in the chroma output and the increase in the luma output are independently determined but both may proportional to the magnitude of the deviation in the chroma carrier amplitude from the different thresholds. | 02-25-2010 |
20100013840 | Compositing in Multiple Video Processing Unit (VPU) Systems - Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels. | 01-21-2010 |
20090295995 | RAPID CHANNEL SIGNAL IDENTIFICATION - An apparatus, for use in a receiver configured to receive electronic signals, for identifying digital signals that are available for reception, includes a timing recovery device configured to receive an incoming signal, related to a transmitted signal, the incoming signal having a first symbol rate, and to re-sample the incoming signal to provide a second symbol rate, and an analyzer that is in communication with the timing recovery device and that is configured to make a determination as to whether a difference between the second symbol rate and a third symbol rate of a transmitter providing the transmitted signal is within an acceptable tolerance and to use the determination in an analysis of whether the transmitted signal is available for reception. | 12-03-2009 |
20090262864 | SYMMETRICAL DATA SIGNAL PROCESSING - In a digital communications receiver configured to receive, via a communications channel, a received first signal representing a sequence of symbols, each symbol being encoded to be representative of data bits, a method of processing the received signal includes adjusting a magnitude, filtering, and applying cyclic prefix restoration, to the received signal to produce a second signal, converting the second signal from time domain to frequency domain to produce a frequency domain signal, and determining a first quantity of values representing a first portion of the symbols by evaluating a relationship of channel values representing characteristics of the communications channel and a second quantity of values representing a portion of the frequency domain signal, the first quantity being smaller than the second quantity. | 10-22-2009 |
20090254699 | Synchronous dynamic random access memory interface and method - A memory interface allows access to SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n (n>1) column memory addresses from the received column address. The interface accesses the synchronous dynamic memory to read or write n bursts of data at the n column memory addresses. Preferably, the SDRAM is clocked at n times the rate of the interconnected memory accessing device, and the memory units. The data units in the n bursts preferably have one n | 10-08-2009 |
20090125747 | Asymmetrical IO Method and System - An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins. | 05-14-2009 |
20090125702 | SIMD processor and addressing method - A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. Each register set includes a pointer register, and a scale register. An address generator forms effective addresses from a selected register set's pointer register and scale register; and an offset. For example, the effective memory address may be formed by multiplying the scale value by an offset value and summing the pointer and the scale value multiplied by the offset value. | 05-14-2009 |
20090091569 | Apparatus and Method for Processing Pixel Depth Information - An apparatus for rendering an image includes a command binning module. The command binning module generates binned image information by classifying command information into bins that each correspond to a display tile of an image to be rendered. The command binning module generates image depth information for each display tile based on the binned command information. | 04-09-2009 |
20090086865 | Differential Signal Comparator - A differential signal comparator includes an input circuit operative to provide an absolute input current difference value that is associated with the absolute difference of differential input signal levels, and a reference circuit operative to provide an absolute reference current difference value that is associated with the absolute difference of the reference signal levels. Current comparison of the absolute input current difference value with the absolute reference current difference value identify whether an input differential signal is bigger than the reference noise level and should be processed, or an input differential signal is smaller than the reference noise level and should not be processed. | 04-02-2009 |
20080288663 | METHOD AND SYSTEM FOR HANDLING ERRORS - In accordance with a specific aspect of the present disclosure, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized and written to an output buffer location. | 11-20-2008 |
20080231482 | METHODS AND APPARATUS FOR PROCESSING VARIABLE LENGTH CODED DATA - An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes. | 09-25-2008 |
20080197477 | Flip-Chip Grid Ball Array Strip and Package - The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units. The use of a retention wall of a stiffener layer over an expensive substrate layer allows for the use of disposable edges around the strip including indexing holes or other holding mechanisms. What is also contemplated is a method of manufacture of a compact strip, matrix, or array comprised of a plurality of integrated circuit packages where no waste or additional cuts are needed to produce individual integrated circuit packages. | 08-21-2008 |