Marvell International Ltd. Patent applications |
Patent application number | Title | Published |
20160140989 | READ ASSEMBLY, DATA STORAGE SYSTEM, AND METHODS OF USING THE SAME - In various embodiments, a read assembly for reading a dual-layered medium may be provided. The dual-layered medium may include a servo layer and a data layer over the servo layer. The read assembly may include a data read head configured to read the data layer. The read assembly may also include a servo read head configured to read the servo layer. | 05-19-2016 |
20150206552 | Data Recording Medium and Method for Generating a Reference Clock Signal - Various embodiments provide a recording medium. The recording medium may include a dedicated servo layer for providing servo information. The dedicated servo layer may include a plurality of tracks. A first track may include a first servo signal. A second track may include a second servo signal. The first servo signal and the second servo signal may include a plurality of common transitions. The transitions may be provided at a pre-determined frequency. | 07-23-2015 |
20150200860 | METHOD AND APPARATUS FOR PACKET CLASSIFICATION - Aspects of the disclosure provide a method for packet classification. The method includes storing, in a computer memory of a network device, characteristic signatures of packet flows for network applications. The characteristic signature includes a pattern of two or more packet attributes of packets in packet flows for a network application. Then, the method includes receiving a stream of network packets at the network device, identifying one or more packet flows in the stream of network packets, processing the packets, at a packet processor, to obtain packet attributes of packets in the respective packet flows, and identifying a packet flow as being associated with a given network application when the packet attributes of packets in the packet flow match the characteristic signature of the given network application. | 07-16-2015 |
20150179198 | RECORDING MEDIUM, A DATA STORAGE APPARATUS AND A METHOD OF PREPARING A RECORDING MEDIUM - In the present disclosure, a recording medium and a method of preparing a recording medium is provided. In a recording medium, a first annular servo track can be provided on a first layer of the recording medium, and second annular servo track can be provided on the first layer of the recording medium. The second annular servo track can be adjacent to the first annular servo track. In the recording medium, the first annular servo track and the second annular servo track are magnetically polarized and are magnetically opposing in polarity. A corresponding method of preparing a recording medium is provided. | 06-25-2015 |
20150163156 | NETWORK PROCESSOR UNIT AND A METHOD FOR A NETWORK PROCESSOR UNIT - A method of and a network processor unit for processing of packets in a network, the network processor comprising: communication interface configured to receive and transmit packets; at least one processing means for processing packets or parts thereof; an embedded switch configured to switch packets between the communication interface and the processing means; and wherein the embedded switch is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means for processing thereof, to receive the processed first part of the packet from the processing means, and to transmit the processed first part of the packet. | 06-11-2015 |
20140269247 | METHOD AND APPARATUS TO COMPENSATE FOR NONLINEAR ECHO IN AN OUTPUT OF A CURRENT SOURCE - A compensator generating a compensation signal to compensate for nonlinear echo in an output of a current source. The nonlinear echo is a result of transitioning the current source between an ON state and an OFF state. The compensator includes driving, weighting, function, and compensating circuits. The driving circuit receives a first signal that is based on the output of the current source. The weighting circuit is configured to generate a second signal based on weighted versions of the first signal. The function circuit, based on the second signal, (i) updates each of multiple functions, and (ii) selects a first function. The driving circuit generates a driving signal based on the first function selected by the function circuit. The compensating circuit generates the compensation signal based on the driving signal to compensate for the nonlinear echo provided by the output of the current source. | 09-18-2014 |
20140258550 | AUTOMATIC AD-HOC NETWORK CREATION AND COALESCING USING WPS - A device previously configured as a registrar and that has established an independent ad-hoc network is automatically discovered by another device also previously configured as a registrar. To form an ad-hoc wireless network between these two devices, each device periodically enters a scanning mode to scan for and intercept beacons transmitted by the other device. Upon such interception, one of the devices becomes an enrollee in accordance with a predefined condition and in response to a user selected option. Subsequently, the enrollee modifies its beacons to include an attribute, such as the MAC address, associated with the other device. After intercepting the modified beacon, the remaining registrar prompts it user to decide whether to allow the enrollee to join the registrar's network. If the user responds affirmatively, a handshake is performed between the two devices and a subsequent attempt is made by the enrollee to join the registrar's network. | 09-11-2014 |
20140247835 | SYSTEM AND METHOD FOR MODIFYING, IN A PROCESSING PIPELINE, A LENGTH OF A DATA PACKET IN A DATA BLOCK WITHOUT MODIFYING A LENGTH OF THE DATA BLOCK - A system including a receiver and a processing pipeline. The receiver is configured to generate a data block by encapsulating a data packet in a header portion and a tail portion that do not include valid information bits. The processing pipeline is configured to, in a first processing stage, store the data block, and store, separately from the data block, additional information associated with the data block. The processing pipeline is further configured to, without modifying a length of the data block, either add bits to the header portion or the tail portion to increase the length of the data packet or subtract bits from the data packet to decrease the length of the data packet, and modify the additional information in accordance with the bits added to the header portion or the tail portion or the bits subtracted from the data packet. | 09-04-2014 |
20140235301 | CONFIGURABLE DC-DC CONVERTER - A method includes, in a mobile communication terminal that is powered by a DC-DC converter and is operated by a user in accordance with multiple possible usage scenarios, determining a usage scenario according to which the terminal currently operates. One or more parameters of operation for the DC-DC converter are derived from the usage scenario. The DC-DC converter is configured to supply electrical power to the terminal using the derived parameters of operation. | 08-21-2014 |
20140169382 | Packet Forwarding Apparatus and Method - A network device includes a plurality of physical ports configured to be coupled to one or more networks, and a processor device configured to process packets. The processor device includes a processor configured to implement a logical port assignment mechanism to assign source logical port information to a data packet received via a source physical port of the plurality of physical ports. The source logical port information is assigned based on one or more characteristics of the data packet, and the source logical port information corresponds to a logical entity that is different from any physical port. The processor device also includes a forwarding engine processor configured to determine one or more egress logical ports for forwarding the data packet, map the egress logical port(s) to respective egress physical port(s) of the plurality of physical ports, and forward the data packet to the egress physical port(s) based on the mapping. | 06-19-2014 |
20140155068 | ADAPTIVE RE-ESTABLISHMENT OF DATA SESSIONS - A method includes, in a mobile communication terminal, holding a definition of multiple re-establishment modes, each re-establishment mode defining a respective criterion for selecting a base station with which to re-establish a failed data session. Success statistics of one or more of the re-establishment modes in a given geographical region are collected in the terminal. In response to a failure in a data session occurring while the terminal is in the given geographical region, a re-establishment mode is selected from among the multiple re-establishment modes based on the success statistics, and the data session is re-established using the selected re-establishment mode. | 06-05-2014 |
20140146835 | 64B/66B CODEC FOR ETHERNET APPLICATIONS - Aspects of the disclosure provide a codec that transforms input data into a codeword. The codeword includes a header portion and a payload portion. The codec modifies the payload portion of the codeword based on a type control block that is included in the payload portion of the codeword. Specifically, the codec modifies a control block in the payload portion to create a reference block, which provisions for data blocks to be inserted in the codeword subsequent to the reference block. Thus, by modifying the payload portion of the codeword, the codec eliminates any wasted data bytes thereby achieving optimal usage of the payload bandwidth. | 05-29-2014 |
20140146827 | NETWORK PROCESSOR UNIT AND A METHOD FOR A NETWORK PROCESSOR UNIT - A method of and a network processor unit for processing of packets in a network, the network processor comprising: communication interface configured to receive and transmit packets; at least one processing means for processing packets or parts thereof; an embedded switch configured to switch packets between the communication interface and the processing means; and wherein the embedded switch is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means for processing thereof, to receive the processed first part of the packet from the processing means, and to transmit the processed first part of the packet. | 05-29-2014 |
20140133854 | VERSATILE OPTICAL NETWORK INTERFACE METHODS AND SYSTEMS - Methods and systems for implementing versatile optical terminals that detect optical transmission protocols and subsequently adapt to the correct protocol are disclosed. In an embodiment, an interface device for providing an interface for a first network with a passive optical network (PON) is disclosed. The interface device includes a protocol detection circuit for determining whether optical communication signals received from the PON conform to a first optical communication protocol, and a switchover control circuit that reconfigures the interface device to work with a second optical communication protocol when the received optical communication signals do not conform to the first optical communication protocol. | 05-15-2014 |
20140115254 | ACCESS SCHEDULER - Embodiments of the present invention provide a system for scheduling memory accesses for one or more memory devices. This system includes a set of queues configured to store memory access requests, wherein each queue is associated with at least one memory bank or memory device in the one or more memory devices. The system also includes a set of hierarchical levels configured to select memory access requests from the set of queues to send to the one or more memory devices, wherein each level in the set of hierarchical levels is configured to perform a different selection operation. | 04-24-2014 |
20140105603 | Systems and Methods for Advanced Power Management for Optical network Terminal Systems on Chip - Systems and methods are provided for customer premises equipment (CPE) on a passive optical network (PON). A system includes a packet processor having at least an active mode and a sleep mode, the packet processor configured to processes streams of data packets received in a data plane from an optical line terminal (OLT) through the PON when in an active mode and to enter the sleep mode when not receiving data packets in the data plane. A system further includes a micro-controller, separate from the packet processor, configured to receive from an OLT operation and management (OAM) messages that are transmitted in a control plane, and to process the OAM messages by, selectively transmitting to a central office, without waking up the packet processor, an acknowledgement message, or waking up the packet processor to receive data packets in the data plane. | 04-17-2014 |
20140105064 | METHOD AND APPARATUS FOR PATH INDICATION - Aspects of the disclosure provide a method for generating a Layer 2 path indication by a processor. The method includes receiving, by the processor, a request for providing a Layer 2 path indication between a first host and a second host in a network. Nodes in the network are configured to form a plurality of sub-networks to enable data transfer from one host to another host within a sub-network via a Layer 2 path formed of a sequence of intermediate nodes in the same sub-network. The method further includes identifying, by the processor, a sub-network within the network to which the first host and the second host belong, and determining, by the processor, within the sub-network a sequence of intermediate nodes on a path for Layer 2 data transfer between the first host and the second host. | 04-17-2014 |
20140089597 | Caching Based on Spatial Distribution of Accesses to Data Storage Devices - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for quantifying a spatial distribution of accesses to storage systems and for determining spatial locality of references to storage addresses in the storage systems, are described. In one aspect, a method includes determining a measure of spatial distribution of accesses to a data storage system based on multiple distinct groups of accesses to the data storage system, and adjusting a caching policy used for the data storage system based on the determined measure of spatial distribution. | 03-27-2014 |
20140086087 | SYSTEM AND METHOD FOR THROUGHPUT ENHANCEMENT - A method in a first node of a network comprises computing a packet duration when using a first unicast profile with a first type preamble and a packet duration when using a second unicast profile with a second type preamble; comparing the computed packet durations so as to determine one from the first and second unicast profiles which yields a shorter duration; and sending the packet to a second node by using the determined unicast profile. | 03-27-2014 |
20140071782 | Circuits, Architectures, Apparatuses, Systems, Algorithms, and Methods for Memory with Multiple Power Supplies and/or Multiple Low Power Modes - Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory. The method generally includes operating peripheral circuitry at a first voltage from a first power rail, operating a memory array at the first voltage or a second voltage, the memory array being coupled to a second power rail, coupling the first and second power rails during standard operating mode when the memory array operates at the first voltage, otherwise not coupling the first and second power rails, and reducing leakage in the memory array during a leakage reduction mode by reducing a voltage differential between a ground plane in the memory array and the second power rail. | 03-13-2014 |
20140035093 | Integrated Circuit Interposer and Method of Manufacturing the Same - Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate. A second integrated circuit portion is disposed on a second location of the single semiconductor substrate, where the second integrated circuit portion is electrically isolated from the first integrated circuit portion along a first axis. The first and second integrated circuit portions are configured to provide an electrical coupling to two or more corresponding top die integrated circuits across a second axis that is perpendicular to the first axis. | 02-06-2014 |
20140029681 | CONTROL MODE PHY FOR WLAN - In a method for generating a physical layer (PHY) data unit for transmission via a communication channel, information bits to be included in the PHY data unit are encoded using a forward error correction (FEC) encoder. Also, the information bits are encoded according to a block coding scheme, where m copies of each bit are included in the information bits, and one or more bits in the m copies of each bit are flipped. The information bits are mapped to a plurality of constellation symbols, and a plurality of orthogonal frequency division multiplexing (OFDM) symbols are generated to include the plurality of constellation symbols. The PHY data unit is generated to include the plurality of OFDM symbols. | 01-30-2014 |
20130326530 | METHOD FOR PACKET FLOW CONTROL USING CREDIT PARAMETERS WITH A PLURALITY OF LIMITS - The present invention relates to a processor and a method for processing a data packet, the method including steps of decreasing a value of a first credit parameter when the data packet is admitted to a processor at least partly based on the value of the first credit parameter and a first limit of the first credit parameter, and increasing the value of the first credit parameter, in dependence on a data storage level in a buffer in which the data packet is stored before being admitted to the processor, the value of the first credit parameter not being increased, so as to become larger than a second limit of the first credit parameter, when the buffer is empty. | 12-05-2013 |
20130315050 | CHANNEL SOUNDING AND ESTIMATION STRATEGIES FOR ANTENNA SELECTION IN MIMO SYSTEMS - A method of antenna selection, in a MIMO system in which a transmitter having a first plurality of RF chains communicates with a receiver having a second plurality of RF chains, includes transmitting consecutive sounding packets produced by the first plurality of RF chains. The consecutive sounding packets each include a training symbol, and collectively sound a full-size channel for the MIMO system. The method also includes receiving channel state information for each of a plurality of scaled sub-channel estimates determined at the receiver. The channel state information includes at least one of respective gain factors that were applied to the consecutive sounding packets received at the receiver and respective scaling factors that were applied to sub-channel estimates determined at the receiver. The method also includes adjusting power levels applied to the first plurality of RF chains in response to receiving the channel state information. | 11-28-2013 |
20130282927 | SCSI I/O COMMAND AGGREGATION - The present disclosure includes systems and techniques relating to input/output (I/O) command aggregation for Small Computer System Interface (SCSI) enabled devices. In some implementations, a method can comprise receiving a first command for a target device, wherein the first command includes a first memory address and a first data transfer count; receiving a second command for the target device, wherein the second command includes a second memory address and a second data transfer count, and wherein the first and second commands are entirely read commands or entirely write commands; aggregating the first and second memory addresses and the first and second data transfer counts into consolidated command information; generating a packet command that includes a packet tag and a data size corresponding to the consolidated command information; communicating the packet command to the target device; in response to receiving a transfer ready notification from the target device, communicating the consolidated command information to the target device; and communicating additional information to the target device. | 10-24-2013 |
20130259017 | Physical Layer Frame Format for WLAN - In a method for generating a data unit conforming to a first communication protocol, a first field and a second field to be included in a preamble of the data unit are generated. The first field includes a first set of one or more information bits that indicate a duration of the data unit and is formatted such that the first field allows a receiver device that conforms to a second communication protocol to determine the duration of the data unit. The second field includes a second set of one or more information bits that indicate to a receiver device that conforms to the first communication protocol that the data unit conforms to the first communication protocol. The first field and the second field are modulated using a modulation scheme specified for a field corresponding to the first field and the second field, respectively, by the second communication protocol. | 10-03-2013 |
20130258845 | METHOD AND APPARATUS FOR SCHEDULING PACKETS FOR TRANSMISSION IN A NETWORK PROCESSOR HAVING A PROGRAMMABLE PIPELINE - A network processor includes an arbitration device, a processing device, and a pipeline. The arbitration device receives a first packet and a second packet. The second packet includes a first control message. The pipeline includes access devices, where the access devices include first and second access devices. The pipeline, based on a clock signal, forwards the first and second packets between successive ones of the access devices. The arbitration device: sets a timer based on at least one of (i) an amount of time for data to travel between the first and second access devices, or (ii) a number of pipeline stages between the first and second access devices; adjusts a variable based on (i) the clock signal, and (ii) transmission of the first packet from the arbitration device to the pipeline; and based on the timer and the variable, schedules transmission of the second packet through the pipeline. | 10-03-2013 |
20130227202 | IMPLEMENTING RAID IN SOLID STATE MEMORY - The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving a request for data stored in a solid state memory, and identifying a logical block grouping for logical data blocks of the requested data, the logical data blocks corresponding to the solid state memory, and the logical block grouping comprising at least one physical data storage block from two or more solid state physical memory devices. The method also includes reading the stored data and a code stored in the identified logical block grouping, and comparing the code to the stored data to assess the requested data. | 08-29-2013 |
20130223252 | MITIGATION OF FALSE PDCCH DETECTION - A method includes receiving in a communication terminal a signal, which is transmitted in multiple links and which includes a control channel transmitted in an assigned sequence of the links. One or more candidate sequences of the links, which are likely to be the assigned sequence, are identified. For at least, one candidate sequence, a verification is made whether the candidate sequence is the assigned sequence, by re-encoding decoded bits of the candidate sequence to produce regenerated symbols and comparing the regenerated symbols to respective received symbols from which the decoded bits were decoded. The control channel is decoded from the candidate sequence in response to verifying that the candidate sequence is the assigned sequence. | 08-29-2013 |
20130217386 | PARALLEL MULTI-RAT PLMN SEARCH - A method includes, in a mobile communication terminal, receiving signals in a frequency band. One or more lists of entries are generated based on the received signals, each entry specifying a respective frequency channel suspected of containing a carrier of a respective Radio Access Technology (RAT). At least some of the entries are scanned in accordance with a scanning order that alternates from a first RAT to a second RAT before scanning all the entries of the first RAT. For each scanned entry, detection is made whether the respective frequency channel actually contains the carrier of the respective RAT. The detection of the carriers in the frequency band is output. | 08-22-2013 |
20130201886 | RATE MATCHING FOR A WIRELESS COMMUNICATIONS SYSTEM - Apparatuses and methods are provided for generating a plurality of redundancy versions using various rate matching algorithms. In some embodiments, a rate matcher is provided that allocates systematic and parity bits to the redundancy versions in a manner that allows all of these bits to be transmitted in at least one redundancy version. In some embodiments, the rate matcher uses a first puncturing algorithm to generate both a first redundancy version and a third redundancy version, but allocates a different proportion of the systematic bits to these redundancy versions. In these embodiments, the second redundancy version may include only bits that were not transmitted in the first redundancy version. | 08-08-2013 |
20130201853 | Spectrum estimation for low-load LTE signals - A method includes receiving a signal in a communication terminal. A power spectral density, which the signal would have under full-load conditions of a transmitter transmitting the signal, is estimated based on the received signal. An operation is performed in the communication terminal using the estimated power spectral density. | 08-08-2013 |
20130155146 | DEVICE FOR SERVICING AN INK JET PRINT HEAD ON A HAND HELD PRINTER - A hand-held printer that includes an inkjet array having a plurality of inkjets is disclosed. The hand-held printer may include an inkjet cap sized to cooperatively engage the inkjet array, wherein the inkjet cap is movable between and open position and a closed position, and a plurality of wipers carried by the inkjet cap, wherein each of the plurality of wipers is configured to engage one of the plurality of inkjets as the inkjet cap moves from the open position to the closed position; and wherein each of the plurality of wipers includes a gasket configured to form a seal adjacent to one of the plurality of inkjets. | 06-20-2013 |
20130142030 | FREQUENCY DOMAIN ECHO AND NEXT CANCELLATION - A cancellation system is disclosed for processing incoming and outgoing signals in a transform domain to create a cancellation signal for reducing or removing unwanted interference. Data is ordered based on Good-Thomas indexing into a two dimensional array in a buffer. The two dimensional array may have l | 06-06-2013 |
20130134905 | COLOR MIXING SYSTEM WITH BUCK-BOOST AND FLYBACK TOPOLOGIES - A system includes a first solid-state lamp that generates a first illuminated output having a first color. A second solid-state lamp generates a second illuminated output having a second color. The second illuminated output is mixed with the first illuminated output to generate a third illuminated output having a third color. An inductor or a transformer includes a primary coil and a bias coil. A first circuit includes the primary coil and a first switch. The first circuit supplies power to the first solid-state lamp. A second circuit includes the bias coil and a second switch. The second circuit supplies power to the second solid-state lamp. A control module alters the third color including controlling (i) a state of the first switch to adjust current supplied to the first solid-state lamp, and (ii) a state of the second switch to adjust current supplied to the second solid-state lamp. | 05-30-2013 |
20130115941 | COEXISTENCE SYSTEM AND METHOD FOR WIRELESS NETWORK DEVICES - A network interface including a radio frequency (RF) system and a media access controller (MAC). The RF system wirelessly communicates with an access point (AP). The MAC includes client modules. A first client module transmits a first signal from a host to the AP via the RF system in accordance with a first wireless communication standard. A second client module transmits a second signal from the host to the AP via the RF system in accordance with a second wireless communication standard. The second client module determines a quality level of the second signal transmitted from the second client module to the AP, and based on the quality level of the second signal, hands off access to the RF system from the second client module to the first client module to allow the first client module to transmit the first signal to the AP via the RF system. | 05-09-2013 |
20130114548 | COEXISTENCE AND COLLOCATION OF REMOTE NETWORK AND LOCAL NETWORK RADIOS - A coexistent communication system of a first network device includes a remote network radio. The remote network radio has a remote transmission distance, operates based on remote network protocols, and communicates with a base station using a first communication link corresponding to a first frequency band. A local network radio has a local transmission distance and is collocated with the remote network radio. The local network radio operates based on local network protocols that are different than the remote network protocols and communicates with a second network device using a second communication link corresponding to a second frequency band. A control module at least one of schedules communication on the first communication link and the second communication link and adjusts a transmission parameter of one of the remote network radio and the local network radio. Transmission distance of the remote network radio is greater than transmission distance of the local network radio. | 05-09-2013 |
20130106638 | SCALABLE SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTER | 05-02-2013 |
20130080664 | SYSTEMS AND METHODS FOR CREATING BIDIRECTIONAL COMMUNICATION CHANNELS USING BLOCK DEVICES - A system includes an initiator device including an initiator interface. A target device includes a target interface that communicates with the initiator interface via a protocol. The protocol supports commands being sent from the initiator device to the target device. The protocol does not support commands being sent from the target device to the initiator device. The target interface is configured to send a command to the initiator device via the protocol. The initiator interface is configured to execute the command. | 03-28-2013 |
20130073922 | METHOD AND APPARATUS FOR IMPROVED PERFORMANCE OF ITERATIVE DECODERS ON CHANNELS WITH MEMORY - Systems and methods for improving the performance of iterative decoders on various channels with memory are disclosed. These systems and methods may reduce the frequency or number of situations in which the iterative decoder cannot produce decoded data that matches the data that was originally sent in a communications or data storage system. The iterative decoder includes a SISO channel detector and an ECC decoder and decodes the coded information according to at least one iterative decoding algorithm in regular decoding mode and/or at least one iterative decoding algorithm in error-recovery mode. | 03-21-2013 |
20130046886 | Controlling a Network Connection Status Indicator - This disclosure describes techniques for restricting activity of a status indicator if a received data unit is determined to be a protocol control unit that is selected for filtering. In one embodiment, a method is described that comprises receiving a data unit from a network, determining whether the received data unit is a protocol control unit, and restricting activity of a status indicator if the received data unit is determined to be the protocol control unit, or allowing activity of the status indicator if the received data unit is determined to be data other than the protocol control unit. | 02-21-2013 |
20130033249 | CONTROL OF DELIVERY OF CURRENT THROUGH ONE OR MORE DISCHARGE LAMPS - A process for controlling a current supplied to a load includes, in at least one aspect, detecting input to control a current supplied to a load operated by a driving signal, and in response to detecting the input, modifying the driving signal to control the current supplied to the load, wherein modifying the driving signal comprises alternately applying a first duty cycle and a second duty cycle to the driving signal. | 02-07-2013 |
20130010320 | USER INTERFACE FEEDBACK USING SCANNER LIGHT SOURCE - An image forming apparatus includes a scanning region and a user interface region adjacent to the scanning region. In the user interface, a first illuminated indicator corresponds to a function of the image forming apparatus. A light source is operable to illuminate an object in the scanning region. A first light conveying member is coupled to the illuminated indicator and operable to receive light from the light source. | 01-10-2013 |
20120327857 | SYSTEM AND METHOD FOR IDENTIFYING AN ACCESS POINT - An apparatus and method are disclosed to communicate, from a first device to a wireless device, information by which the wireless device may identify an access point as a potential network device. The information is encoded in a packet stream by the first device, and wirelessly communicated from the access point to the wireless device. The information may be encoded by varying a packet characteristic, such as packet length, that is preserved even if the packets are encoded by the access point. The information may include a beacon, a SSID and/or a key. | 12-27-2012 |
20120299995 | DEVICE FOR SERVICING AN INKJET PRINT HEAD ON A HAND HELD PRINTER - A hand-held printer that includes an inkjet array having a plurality of inkjets is disclosed. The hand-held printer may include an inkjet cap sized to cooperatively engage the inkjet array, wherein the inkjet cap is movable between and open position and a closed position, and a plurality of wipers carried by the inkjet cap, wherein each of the plurality of wipers is configured to engage one of the plurality of inkjets as the inkjet cap moves from the open position to the closed position; and wherein each of the plurality of wipers includes a gasket configured to form a seal adjacent to one of the plurality of inkjets. | 11-29-2012 |
20120233524 | LOW-DENSITY PARITY CHECK CODES FOR HOLOGRAPHIC STORAGE - Systems and methods for constructing low-density parity check codes for holographic storage are provided. The methods include selecting parameters of a low-density parity check code, determining the number of bit processing elements and the amount of memory in an accompanying decoder, and constructing a mother matrix representation of a quasi-cyclic parity check matrix. The low-density parity check codes are optimized for performance, memory considerations, and throughput. | 09-13-2012 |
20120213316 | PREAMBLE DETECTION WITH UNKNOWN CHANNEL - A system comprises a correlation module that correlates modulated signals with a plurality of preamble sequences and that generates correlation values. A control module selects a largest correlation value from said correlation values and detects one of said preamble sequences in said modulated signals upon determining that a magnitude of said largest correlation value is greater than or equal to a first predetermined threshold. | 08-23-2012 |
20120213048 | METHOD AND APPARATUS FOR DETECTING LAND PRE-PITS - Aspects of the disclosure provide a method for detecting land pre-pits. The method includes detecting, based on a land pre-pit threshold, a land pre-pit data stream from a signal responsive to land pre-pits on an optical medium, comparing a characteristic of the detected land pre-pit data stream in a specific number of wobble periods with a pre-determined land pre-pit characteristic in the specific number of wobble periods, and adjusting the land pre-pit threshold based on the comparison. | 08-23-2012 |
20120176876 | METHOD AND APPARATUS FOR DETECTING LAND PRE-PITS - Aspects of the disclosure provide a method for detecting land pre-pits. The method includes extracting a land pre-pit data stream from a signal responsive to land pre-pits on an optical medium based on a land pre-pit threshold, detecting a bit stream pattern from the land pre-pit data stream, comparing one or more bits in the land pre-pit data stream at locations relative to the bit stream pattern with pre-known bit information, and adjusting the land pre-pit threshold based on the comparison. | 07-12-2012 |
20120045140 | IMAGE PROCESSING APPARATUS HAVING CONTEXT MEMORY CONTROLLER - An apparatus for use in image processing is set forth that comprises a pixel processor, context memory, and a context memory controller. The pixel processor is adapted to execute a pixel processing operation on a target pixel using a context of the target pixel. The context memory is adapted to store context values associated with the target pixel. The context memory controller may be adapted to control communication of context values between the pixel processor and the context memory. Further, the context memory controller may be responsive to a context initialization signal or the like provided by the pixel processor to initialize the content of the context memory to a known state, even before the pixel processor has completed its image processing operations and/or immediately after completion of its image processing operations. In one embodiment, the pixel processor executes a JBIG coding operation on the target pixel. | 02-23-2012 |
20110298862 | DEVICE AND METHOD FOR SERVICING AN INKJET PRINT HEAD ON A HAND HELD PRINTER - A hand-held printer that includes an inkjet array having a plurality of inkjets is disclosed. The hand-held printer may include an inkjet cap sized to cooperatively engage the inkjet array, wherein the inkjet cap is movable between and open position and a closed position, and a plurality of wipers carried by the inkjet cap, wherein each of the plurality of wipers is configured to engage one of the plurality of inkjets as the inkjet cap moves from the open position to the closed position; and wherein each of the plurality of wipers includes a gasket configured to form a seal adjacent to one of the plurality of inkjets. | 12-08-2011 |
20110293024 | METHOD FOR INCREASING THE PERFORMANCE OF A COMMUNICATIONS SYSTEM ON A MEDIUM FORMED BY MULTIPLE CONDUCTORS - Method for increasing the performance of a communications system on a medium formed by multiple conductors which increases the performance of a communications system by means of the creation of numerous communication channels with a high degree of isolation between each other on the same physical medium formed by multiple conductors. The method can be extended to be used in various applications, such as the reuse of frequencies on the same channel, the increase of the capacity of the point-to-point links in a network and the improvement of performance and reliability when used with digital processing of signals for transmission or reception, among others. | 12-01-2011 |
20110131347 | DIRECT MEMORY ACCESS CONTROLLER WITH MULTIPLE TRANSACTION FUNCTIONALITY - A direct memory access controller is set forth. The direct memory access controller includes first and second registers storing various values that are used to set the parameters of DMA transfers that take place during a single data transaction. The first register stores a start address location value used to define a start address at which direct memory access transfers for the transaction are to begin. The second register stores a value used to end data transfers of the data transaction. The DMA controller also includes transfer control circuitry for executing the data transaction. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the values stored in the first and second registers. | 06-02-2011 |
20110010593 | SCAN ARCHITECTURE FOR FULL CUSTOM BLOCKS - A output storage latch within a combinational logic circuit may be adapted to form a scan flip-flop latch that supports both functional operation and scan chain testing of a combinational logic matrix included in the combinational logic circuit. A described master/slave clock approach allows the scan flip-flop latch to support receiving into a scan chain a sequence of test input data, execution of combinational logic matrix testing based on the test input data, and sequentially outputting test results to a test result register for comparison with expected results. The described scan flip-flop latch may be used along side unaltered output storage latches thereby allowing flexibility with respect to the number and placement scan chain test points within an integrated circuit. Use of the described dual-use scan flip-flop latch results in a less complex circuit design, reduced circuit area requirements and improved reliability. | 01-13-2011 |
20100277823 | MAGNETIC DISC CONTROLLER AND METHOD - A magnetic disk controller includes a first buffer that includes a first storage area that stores former portions of pieces of writing data, and a second storage area that stores latter portions of pieces of writing data; an encoding unit that encodes a former portion of the first piece of writing data; a second buffer that stores the encoded former portion of the first piece of writing data; and a buffer control unit that writes the encoded former portion of the first piece of writing data into a first sector of the magnetic disk. The encoding unit encodes the latter portion of the first piece of writing data. The second buffer stores the encoded latter portion of the first piece of writing data. The buffer control unit, writes the encoded latter portion of the first piece of writing data into the first sector of the magnetic disk. | 11-04-2010 |
20100277200 | SELF-CALIBRATING WRITER - In accordance with the invention, a method, system and apparatus are presented that matches the output impedance of a driver to the impedance of a transmission line. A method for matching the impedance between a driver and a transmission line, wherein the transmission line is between the driver and a load can include transmitting a first pulse from the driver to the load through the transmission line, wherein a first reflection from the transmitted first pulse occurs after a first time, measuring a second reflection from the transmitted first pulse after a second time, and adjusting the calibration of the driver in response to the measured second reflection. | 11-04-2010 |
20100264955 | METAL PROGRAMMABLE LOGIC AND MULTIPLE FUNCTION PIN INTERFACE - Some of the embodiments of the present invention provide an integrated circuit device including a first metal interconnect, an end of which is coupled to a core of the integrated circuit device, a second metal interconnect, an end of which is coupled to a first input/output (I/O) pin, and a third metal interconnect configured to be coupled to the first metal interconnect and to the second metal interconnect. Other embodiments are also described and claimed. | 10-21-2010 |
20100250821 | INTER-PROCESSOR COMMUNICATION LINK WITH MANAGEABILITY PORT - Manageability ports for inter-processor communication links, along with associated systems and methods, are generally provided. | 09-30-2010 |
20100250165 | Control of Delivery of Current Through One or More Discharge Lamps - Control of delivery of current through one or more discharge lamps. Methods include alternately switching on and off switching elements that control a fluorescent lamp, in response to receiving input, until the brightness of the lamp decreases to a threshold. Further, methods include providing control signals at complementary duty cycles to further decrease the brightness and alternating the duty cycles of the signals applied to the filaments of the fluorescent lamp. Methods include digitally comparing voltage signals supplied to a fluorescent lamp and the current drawn by the fluorescent lamp. | 09-30-2010 |
20100220243 | SYSTEMS AND METHODS FOR CALIBRATING POWER REGULATED COMMUNICATION CIRCUITRY - Systems and methods are provided for calibrating the control mechanism in a communication circuit to allow the communication circuit to maintain a desired output power level. The communication circuit includes a variable gain adjustment circuit and a power amplifier, which operate together to provide an output power level. A control circuit controls the variable gain adjustment circuit based on a default gain parameter, a high power threshold, and a low power threshold. A calibration circuit in the control circuit calibrates a default gain parameter to provide a desired output power. A power detector can detect the desired output power level to provide an output power measurement. The calibration circuit calibrates upper and lower power thresholds to provide an acceptable range of power variation around the output power measurement. | 09-02-2010 |
20090300325 | DATA PROCESSING SYSTEM, APPARATUS AND METHOD FOR PERFORMING FRACTIONAL MULTIPLY OPERATIONS - A data processing system, apparatus and method for performing fractional multiply operations is disclosed. The system includes a memory that stores instructions for SIMD operations and a processing core. The processing core includes registers that store operands for the fractional multiply operations. A coprocessor included in the processing core performs the fractional multiply operations on the operands and stores the result in a destination register that is also included in the processing core. | 12-03-2009 |
20090292976 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR IDENTIFICATION AND EVALUATION - Systems and methods are provided for implementing error identification and evaluation for a Reed-Solomon (RS) error-correction code (ECC) system. The BMA algorithm and/or list decoding may produce one or more error locator polynomials that are related to a decision-codeword. An accelerated Chien search can be used to more quickly evaluate the one or more error locator polynomial. If the accelerated Chien search identifies a valid error locator polynomial, a normal Chien search can be used to identify error locations, and Forney's algorithm or an equivalent technique can be used to evaluate the error values. A RS ECC decoder can include a computation circuit that evaluates an error locator polynomial or an error evaluator polynomial. The computation circuit can include computation components that receive the coefficients of the polynomials. | 11-26-2009 |
20090219096 | OPEN LOOP DC CONTROL FOR A TRANSIMPEDANCE FEEDBACK AMPLIFIER - A transimpedance amplifier having open-loop DC control is provided. The open-loop feedback control may provide a DC bias that is configurable based on the characteristics of an input device, such as, a photodiode or a magnetoresistor. The open-loop feedback control may provide quick recovery from voltage level variations and may provide stability for the amplifier. | 09-03-2009 |
20090083608 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR-CORRECTION DECODING - Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | 03-26-2009 |
20090063937 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR-CORRECTION DECODING - Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | 03-05-2009 |
20090055717 | ARCHITECTURE AND CONTROL OF REED-SOLOMON LIST DECODING - Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes. | 02-26-2009 |
20090049273 | PHYSICALLY-TAGGED CACHE WITH VIRTUAL FILL BUFFERS - A virtually indexed, physically-tagged cache is combined with one or more virtually-tagged fill-buffers. | 02-19-2009 |
20090037753 | Methods and apparatus to selectively power functional units - A processing engine fetches one or more lines of software instructions into an instruction cache. Based on the contents of the cache, potentially needed functional units are identified as functional units that are operable to execute at least one software instruction stored within the instruction cache. Unneeded functional units are identified as functional units that are not operable to execute a software instruction stored within the instruction cache. A power increase is initiated for selected ones of the potentially needed functional units that are determined to be in a low power state. A power decrease is initiated for selected ones of the unneeded functional units that are determined to be in an operable power state. | 02-05-2009 |
20090013131 | LOW POWER SEMI-TRACE INSTRUCTION CACHE - A semi-trace cache combines elements and features of an instruction cache and a trace cache. An ICache portion of the semi-trace cache is filled with instructions fetched from the next level of the memory hierarchy while a TCache portion is filled with traces gleaned either from the actual stream of retired instructions or predicted before execution. | 01-08-2009 |
20080282008 | System and Apparatus for Early Fixed Latency Subtractive Decoding - Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period. | 11-13-2008 |
20080279024 | PROGRAMMABLE BOOSTING AND CHARGE NEUTRALIZATION - A programmable capacitance circuit including an input node; an output node; and a plurality of capacitance stages. Each of the capacitance stages is coupled to the input node and the output node, and wherein each capacitance stage is configured to be switched into a circuit path between the input node and the output node. Each of the capacitance stages includes a capacitor, and a control transistor having a gate capacitance in series with the capacitor, wherein the gate capacitance is configured to be added to the capacitance of the capacitor between the input node and the output node. | 11-13-2008 |
20080270768 | Method and apparatus for SIMD complex Arithmetic - Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate real components for complex multiplication of first operand complex data and corresponding second operand complex data, a cross multiply and add instruction to generate imaginary components for complex multiplication of the first operand complex data and the corresponding second operand complex data, an add-subtract instruction to add real components of the first operand to imaginary components of the second operand and to subtract real components of the second operand from imaginary components of the first operand, and a subtract-add instruction to subtract the real components of the second operand from the imaginary components of the first operand and to add the real components of the first operand to the imaginary components of the second operand. | 10-30-2008 |
20080209187 | Storing and processing SIMD saturation history flags and data size - A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information. A first coprocessor instruction has a first format identifying a saturation operation, a first source having packed data elements and a second source having packed data elements. The saturating operation is executed on the packed data elements of the first and second sources. Saturation flags are stored in the Wireless Coprocessor Saturation Status Flag (wCSSF) register to indicate if a result of the saturating operation saturated. A second coprocessor instruction has a second format identifying a saturation history processing operation and a saturation data size. An operand for the processing operation is determined based on the saturation data size, and the processing operation is executed on the saturation flags and the operand for the saturation data size. Condition code flags are stored in a status register to indicate the result of processing operation. | 08-28-2008 |