National Institute of Advanced Ind. Sci & Tech Patent applications |
Patent application number | Title | Published |
20110063016 | METHOD FOR CONTROLLING INTER-COMPONENT PHASE DIFFERENCE SOLITON AND INTER-COMPONENT PHASE DIFFERENCE SOLITON CIRCUIT DEVICE - A control method is proposed that controls inter-component phase difference solitons by using splitting or fusion caused by the interaction between inter-component phase difference solitons themselves, without the need for application of external energy. By using a line structure ( | 03-17-2011 |
20100315861 | SRAM CELL AND SRAM DEVICE - In an SRAM cell including a first to a fourth semiconductor thin plates which stand on a substrate and are arranged in parallel to each other, on each of the four semiconductor thin plates being formed a first four-terminal double-gate FET with a first conductivity type; a second and a third four-terminal double-gate FETs which are connected in series with each other and have a second conductivity type; a fourth and a fifth four-terminal double-gate FETs which are connected in series with each other and have the second conductivity type; a sixth four-terminal double-gate FET with the first conductivity type, wherein the third and the fourth four-terminal double-gate FETs form select transistors, and the first, the second, the fifth and the sixth four-terminal double-gate FETs form a CMOS inverter, logic signal input gates of the first and the sixth four-terminal double-gate FETs are arranged on the side facing the second and the third semiconductor thin plates, respectively, while threshold voltage control gates of the second to the fifth four-terminal double-gate FETs are arranged on the sides facing each other and are commonly connected to a first bias line. Threshold voltage control gates of the first and the sixth four-terminal double-gate FETs are commonly connected to a second bias line. A word line, the first bias line and the second bias line are arranged orthogonally to the direction of arrangement of the first to the fourth semiconductor thin plates. | 12-16-2010 |
20090072244 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE, AND SILICON CARBIDE SEMICONDUCTOR DEVICE - The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carbide with an insulating film and provide the semiconductor device. The method for the fabrication of a silicon carbide semiconductor device includes the steps of performing thermal oxidation on the (000-1) plane of a silicon carbide semiconductor in a gas containing at least oxygen and moisture, thereby forming an insulating film in such a manner as to contact the (000-1) plane of the silicon carbide semiconductor, removing part of the insulating film, thereby forming an opening part therein, depositing contact metal on at least part of the opening part, and performing a heat treatment, thereby forming a reaction layer of the contact metal and silicon carbide, wherein the heat treatment is implemented in a mixed gas of an inert gas and hydrogen. | 03-19-2009 |
20090059646 | SEMICONDUCTOR INTEGRATED CIRCUIT - A field-effect transistor for nonvolatile memory holding use and a field-effect transistor for logical operation use are manufactured in the same structure on the same semiconductor substrate without separately providing manufacturing processes for the field-effect transistors for the two uses. Both a memory circuit and a logic circuit of a semiconductor integrated circuit are composed of n-channel and p-channel field-effect transistors including a memory holding material in a gate insulating structure. A logical operation state, a memory writing state and a nonvolatile memory holding state are electrically switched by controlling the level and application timing of a voltage to be applied between a gate conductor and a substrate region of the n-channel and p-channel field-effect transistors including the memory holding material in the gate insulating structure. | 03-05-2009 |
20080308840 | PHOTO-FIELD EFFECT TRANSISTOR AND INTEGRATED PHOTODETECTOR USING THE SAME - A photo-FET based on a compound semiconductor including a channel layer formed on a substrate constituting a current path between source and drain electrodes, serving as part of a photodiode and a photosensitive region. A back-gate layer that serving as a substrate-side depletion layer formation layer is disposed between the substrate and the channel layer, and applies to the channel layer a back-gate bias by photogenerated carriers upon illumination. A barrier layer is disposed on the front side of the channel layer that causes one of the photogenerated carriers to run through the channel layer and other of the photogenerated carriers to sojourn or be blocked off. A front-side depletion layer formation layer is disposed on the front side of the channel layer brings the front-side depletion layer into contact with the substrate-side depletion layer without illumination to close the current path in the channel layer, bringing the photo-FET to an off-state. | 12-18-2008 |