LINEAR TECHNOLOGY CORPORATION Patent applications |
Patent application number | Title | Published |
20160087531 | DCR INDUCTOR CURRENT-SENSING IN FOUR-SWITCH BUCK-BOOST CONVERTERS - An inductor current-sensing circuit for measuring a current in an inductor includes (a) a first RC network coupled between a first terminal of the inductor and a reference voltage source; and (b) a second RC network coupled between a second terminal of the inductor and the reference voltage source. The first RC network and the second RC network each have a time constant substantially equal to the ratio between the inductance and the DC resistance of the inductor. The inductor which current is being measured may be a primary inductor of a four-switch buck boost converter receiving an input voltage and providing an output voltage. | 03-24-2016 |
20160036455 | SYSTEM AND METHOD FOR CLOCK GENERATION WITH AN OUTPUT FRACTIONAL FREQUENCY DIVIDER - A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ). | 02-04-2016 |
20160035645 | EXPOSED, SOLDERABLE HEAT SPREADER FOR FLIPCHIP PACKAGES - A flipchip package may include a semiconductor die, a heat spreader, and encapsulation material. The semiconductor die may contain an electronic circuit and exposed electrical connections to the electronic circuit. The heat spreader may be thermally-conductive and may have a first outer surface and a second outer surface substantially parallel to the first outer surface. The first outer surface may be affixed to all portions of a silicon side of the semiconductor die in a thermally-conductive manner. The encapsulation material may be non-electrically conductive and may completely encapsulate the semiconductor die and the heat spreader, except for the second surface of the heat spreader. The second surface of the heat spreader may be solderable and may form part of an exterior surface of the flipchip package. | 02-04-2016 |
20160035644 | EXPOSED, SOLDERABLE HEAT SPREADER FOR INTEGRATED CIRCUIT PACKAGES - An integrated circuit package may include a semiconductor die, a heat spreader, and encapsulation material. The semiconductor die may contain an electronic circuit and exposed electrical connections to the electronic circuit. The heat spreader may be thermally-conductive and may have a first outer surface and a second outer surface substantially parallel to the first outer surface. The first outer surface may be affixed to all portions of a silicon side of the semiconductor die in a thermally-conductive manner. The encapsulation material may be non-electrically conductive and may completely encapsulate the semiconductor die and the heat spreader, except for the second surface of the heat spreader. The second surface of the heat spreader may be solderable and may form part of an exterior surface of the integrated circuit package. | 02-04-2016 |
20150341014 | Broadband Integrated RF/Microwave/Millimeter Mixer with Integrated Balun(s) - A broadband radio frequency, microwave, or millimeter mixer system may include a balun and a mixer. The balun may have an unbalanced port; a balanced port; a first and a second inductor tightly and inversely magnetically coupled to one another; and a third inductor which is not magnetically coupled to the first or the second inductors. The mixer may be connected to the balanced port of the balun. The balun, including its three inductors, and the mixer may all be integrated onto a single substrate that forms an integrated circuit. | 11-26-2015 |
20150332785 | CONFIGURING SIGNAL-PROCESSING SYSTEMS - A configurable signal-processing circuit may provide a plurality of selectable signal-processing operations. The configurable signal-processing circuit may have a configuration circuit that provides a configuration code that selects a first signal-processing operation from the plurality of selectable signal-processing operations based on a timing pattern for evaluating an input signal and outputting an output signal. | 11-19-2015 |
20150295589 | CONVERTING TIME-ENCODED SIGNAL INTO ANALOG OUTPUT - A converter may generate an analog output that is representative of a time-encoded signal. The circuit may include an input port receiving the time-encoded signal; a time-encoded to digital converter coupled to the input port; and a digital-to-analog converter coupled to the time-encoded to digital converter. | 10-15-2015 |
20150270013 | BOOTSTRAP SAMPLING CIRCUIT WITH ACCURATELY AVERAGING PRE-CHARGE CIRCUIT - A sampling circuit may include a sampling capacitance, an electronic sampling switch, and a switch controller. The electronic sampling switch may have a control input that controls whether the electronic sampling switch is in a sample state or a hold state. The electronic sampling switch may connect the sampling capacitance to an input signal while in the sample state and disconnect the sampling capacitance from the input signal while in the hold state. The switch controller may control the control input to the electronic sampling switch so as to cause the electronic sampling switch to be in the sample state during one period and the hold state during another period. While in the sample state, the switch controller may cause the impedance of the electronic sampling switch that is seen by the input signal to be substantially independent of the voltage of the input signal. The switch controller may include a pre-charge circuit that pre-charges the control input to the electronic sampling switch prior to each commencement of the sample state to approximately the average of the voltage of the input signal and the voltage on the sampling capacitance immediately prior to each commencement of the sample state. The amount of the pre-charging may be substantially independent of the voltage of the input signal. | 09-24-2015 |
20150256142 | EXPONENTIAL ROM TABLE TUNING USING TRIM FOR FREQUENCY AGILE ANALOG FILTERS - A tunable and trimmable analog filter may include a tunable analog filter and a trimming circuit. The tunable analog filter may set the frequency of a characteristic of the tunable analog filter based on a digital tuning signal that is indicative of a desired frequency of the characteristic. However, the tunable analog filter may contain components having values that deviate from specified values due to variations during manufacture of the tunable analog filter. The value deviations can cause the frequency of the characteristic not to precisely match the frequency indicated by the digital tuning signal. The trimming circuit may include a non-volatile memory that contains data. The trimming circuit may receive tuning information indicative of a desired frequency for the characteristic of the tunable analog filter. The trimming circuit may generate the digital tuning signal by trimming the tuning information to compensate for the deviations in component value and by using the data contained within the non-volatile digital memory. | 09-10-2015 |
20150207423 | PREDICTIVE AND REACTIVE CONTROL OF SECONDARY SIDE SYNCHRONOUS RECTIFIERS IN FORWARD CONVERTERS - A forward converter has a primary side containing a PWM controller for controlling switching of a power switch and has a secondary side coupled to the primary side via a transformer. The secondary side includes a forward transistor and a catch transistor. A secondary side switch controller controls switching of the forward transistor and the catch transistor without communication from the primary side. The secondary side switch controller detects the rising and falling of the voltages at the ends of the secondary winding to control the switching of the forward and catch transistors. A delay locked loop (DLL) is provided in the secondary side switch controller that turns on the catch transistor when the power switch is turned off and turns off the catch transistor at a predetermined time before the power switch is turned on. A separate circuit controls the catch transistor during a discontinuous mode. | 07-23-2015 |
20150145439 | PRE-CHARGING INDUCTOR IN SWITCHING CONVERTER TO ACHIEVE HIGH PWM DIMMING RATIO IN LED DRIVERS - In a method for controlling a current regulator for dimming an LED load, a dimming signal has a duty cycle that controls the LED ON-time and LED OFF time at a fixed frequency. The regulator is controlled by the dimming signal to only supply current to the LED load during the LED ON-time. The regulator includes an inductor. The inductor current at the end of an ON-time is detected and its value is stored. During the OFF-time, the inductor is pre-charged to the current level matching the stored value, while the regulator's feedback loop is frozen during the OFF-time to not change its feedback control signal. Upon the next ON-time, the regulator begins supplying current to the LED load with the pre-charged inductor current, so there is no initial decrease in the delivered LED current. Therefore, the current pulse magnitudes are constant even with very low duty cycles. | 05-28-2015 |
20150109161 | ISOLATED BOOTSTRAPPED SWITCH - A bootstrapped switch circuit capable of operating at input signals from far below the negative supply rail to far beyond the positive supply rail may include (a) a switch having a first terminal coupled to an input terminal, a second terminal coupled to an output terminal, and a control terminal; (b) a charge pump coupled to one or more clock signals and isolated from a timing circuit via a first capacitor and a second capacitor, the charge pump generating an output voltage; and (c) a logic circuit coupled to one or more clock signals and isolated from the timing control circuit via a third capacitor and a fourth capacitor, wherein the logic circuit provides a control signal to the control terminal of the switch that is derived from the output voltage of the charge pump. | 04-23-2015 |
20150048770 | ACCURATE CURRENT SENSING IN H-BRIDGE APPLICATIONS WITHOUT AMPLIFIER HAVING HIGH COMMON MODE REJECTION RATIO - A current sensing circuit may include a shunt resistance through which current to be sensed travels. A first and a second differential amplifier may each provide an amplified output of the voltage across the shunt resistance. A switching system may deliver a current sensing signal output based on the amplified output of the first differential amplifier when the common mode voltage across the shunt resistance is low and based on the amplified output of the second differential amplifier when the common mode voltage across the shunt resistance is high. The first differential amplifier may provide its lowest output DC offset voltage when the common mode voltage is low, while the second differential amplifier may provide its lowest output DC offset voltage when the common mode voltage is high. The first and second differential amplifiers may both have a low common mode voltage rejection ratio, such as a ratio of less than 40 db at the switching frequency of switches that control the current that is sensed. | 02-19-2015 |
20150021987 | POWER SUPPLY SYSTEM AND METHOD - A power control system includes an event data bus configured to carry event information. Several power supply managers are coupled to the same event bus. Each power supply manager has one or more point of load (POL) regulators assigned to it. Each power supply manager communicates event information with other POL power supply managers over the event data bus. | 01-22-2015 |
20150019884 | PD IN POE SYSTEM HAVING REDUNDANT PSE CHANNEL INPUTS - A Powered Device (PD) in a PoE system has two input channels, each being coupled to a separate Power Sourcing Equipment (PSE) for increased reliability. A first PD controller is coupled to the first channel to perform hand-shaking and closes a first Power Good (PWRGD) switch when the PoE voltage is detected on the first channel. A second PD controller is coupled to the second channel to perform hand-shaking and closes a second PWRGD switch when the PoE voltage is detected on the second channel. A diode bridge couples both channels to a single regulating power supply that supplies power to a load. Auxiliary switches are controlled by the PWRGD signals so that only the first channel or the second channel is coupled to the diode bridge in the event that both channels receive the respective PoE voltages. Therefore, hot standby is provided using only one power supply. | 01-15-2015 |
20140372773 | POWER OVER ETHERNET ON DATA PAIRS AND SPARE PAIRS - Power Sourcing Equipment (PSE) provides a PoE supply voltage over data wires to a Powered Device (PD). A PSE controller controls a first FET that couples the PoE voltage to the data wire pairs and controls a second FET that couples the data wire pairs to the spare wire pairs. Upon powering up, the PSE controller keeps the two FETs open and performs a detection routine on any devices connected to the data pairs and spare pairs. If a PoE-compatible PD is detected as being coupled to the data pairs, the first switch is closed. If it is determined that the PoE voltage should also be coupled to the spare pairs, the second FET is also closed. The method prevents the PoE voltage from being applied to the spare pairs when the device connected to the spare pairs is not PoE compatible and maintains backwards compliance with IEEE PoE PDs. | 12-18-2014 |
20140340248 | RESOLUTION-BOOSTED SIGMA DELTA ANALOG-TO-DIGITAL CONVERTER - A method and an ADC circuit use multiple SD modulations on an analog value and apply digital post-processing of the pulse density modulation (PDM) streams from the SD modulations obtaining a higher resolution in the digital output value for a given oversampling ratio. SD ADC does not face the constraint of conversion time doubling for each additional bit of resolution. In one implementation, an SD ADC includes conversions in SD phase and a resolution-boosting phase. During SD phase, MSBs of the digital output value are generated from the sampled analog value using a first SD conversion. At the end of SD phase, the sampled analog value is reduced to “residual quantization error,” which remains in a capacitor of an integrator of SD ADC. In resolution-boosting phase, the LSBs of the digital output value are generated from residual quantization error using a second SD conversion that provides at least the LSBs. | 11-20-2014 |
20140312989 | POLY-PHASE FILTER WITH PHASE TUNING - A poly-phase filter receives inphase input signals I and Ī and quadrature input signals Q and | 10-23-2014 |
20140312955 | BALUN MIXER CIRCUITS - A single-balanced balun mixer circuit includes a balun with a center tap connected to a differential pair with a tail resistor. The balun receives a first input signal and a second signal at the single-ended input terminal and the center tap, respectively. Such a balun mixer may be used as an up-converter mixer by supplying a baseband or intermediate signal at the center tap and a local oscillator (LO) signal at the single-ended input terminal. | 10-23-2014 |
20140312866 | LINEAR REGULATOR IC WITH VERSATILE GROUND PIN - A linear regulator integrated circuit may be formed having four external terminals including a voltage input (Vin) terminal, a voltage output (Vout) terminal, a Set terminal, and an operational amplifier (op amp) power terminal. A user connects an external resistor to the Set terminal for creating a reference voltage. An op amp controls a pass (or series transistor) to cause an output voltage at the Vout terminal to equal the reference voltage. The op amp has a first power supply terminal internally coupled to the Vin terminal and a second power supply terminal coupled to the op amp power terminal. The op amp power terminal allows a user to externally couple the op amp second power supply terminal to either the Vout pin (for high voltage applications), system ground (for medium voltage applications), or another voltage (to provide additional headroom in very low voltage applications). | 10-23-2014 |
20140312865 | VOLTAGE GENERATOR WITH CURRENT SOURCE COMPENSATED FOR AN ERROR CURRENT OPERABLE OVER A WIDE VOLTAGE RANGE - In one embodiment, a regulator circuit for generating a regulated output voltage Vout has an error amplifier using a pair of bipolar transistors at its front end. The error amplifier compares the regulated output voltage to a reference voltage Vref. A precision current source draws a first current through a user-selected set resistance to generate the desired Vref. The regulator circuit controls a power stage to cause Vout to be equal to Vref. The base current into one of the bipolar transistors normally distorts the current through the set resistance. A base current compensation circuit is coupled to the current source to adjust the first current by a value equal to the base current to offset the base current. Therefore, Vref is not affected by the base current. The error amplifier may be in a linear regulator or a switching regulator. The compensation circuit may be used in other applications. | 10-23-2014 |
20140306662 | VOLTAGE COMPENSATED ACTIVE CELL BALANCING - A monitoring device includes an input terminal configured to receive an input signal from a battery system management (BSM); an output terminal configured to output cell parameters used to determine an open cell voltage associated with one of a plurality of cells within the battery stack connected to the monitoring circuit based on the input signal received from the BSM; a processor; and a memory storing executable instructions for causing the processor to: measure a cell voltage associated with the one of the plurality of cells within the battery stack; measure a voltage drop associated with a measured balancing current; calculate the open cell voltage by adjusting the measured cell voltage based on the measured voltage drop; and balance the battery stack based on the calculated open cell voltage, wherein balancing and calculating the open cell voltage are performed concurrently. | 10-16-2014 |
20140281080 | ADDRESS TRANSLATION IN 12C DATA COMMUNICATIONS SYSTEM - A novel readdressing circuit is provided for supporting data communications over a data line and a clock line between at least one master device and multiple slave devices. For example, the master device and the multiple slave devices may be configured to communicate over an I2C bus including the data line and the clock line. The readdressing circuit has a data input node for receiving a data signal transferred over the data line and including an address word produced by the master device, and a data output node coupled to the multiple slave devices. The readdressing circuit also includes an address generator and an address transmit detections circuit. The address generator is configured for storing a multi-bit fixed offset value. The address generator is responsive to the address word at the data input node for generating multiple unique addresses for the multiple slave devices. The address transmit detection circuit is configured for enabling the address generator to generate the multiple unique addresses at the data output node when the address word is detected at the data input node, and for preventing an output signal of the address generator from being supplied to the data output node when no address word is detected at the data input node. | 09-18-2014 |
20140268909 | METHODS AND SYSTEMS FOR CONTROL OF DC-DC CONVERTERS - Switching regulator methods and systems for supplying output current at a regulated voltage level to a load. The regulator has a primary side that is galvanically isolated from a secondary side. The regulator includes a transformer having a primary winding on the primary side and a secondary winding on the secondary side, coupled to a load. A switch, coupled to the primary winding, controls current flow through the primary winding. A first feedback control loop, responsive only to primary side signal values, regulates a constant average voltage at the output node. An optional second feedback control loop, responsive only to primary side signal values, reduces voltage ringing at the output node. | 09-18-2014 |
20140266840 | OUTPUT STAGE WITH FAST FEEDBACK FOR DRIVING ADC - A driver for an analog-to-digital converter (ADC) has an overall feedback loop between its input and its output for maintaining overall accuracy, and a much faster feedback loop in its output stage that quickly compensates for output transients before the overall feedback loop can substantially react to the transients. Output voltage transients are created by the intermittent capacitive load of the ADC. The fast feedback loop can be made very fast since there are only a few components in the fast feedback path. The fast reduction of the output transients enables a shorter sampling time, leading to more accurate analog-to-digital conversion. The overall gain of the driver can be set to be greater than unity while still providing good output transient suppression. | 09-18-2014 |
20140266435 | TRANSLINEAR SLEW BOOST CIRCUIT FOR OPERATIONAL AMPLIFIER - A method of improving the slew rate of an amplifier is described where a differential pair of transistors receives a differential first control signal and second control signal. The tail current for the transistors is provided by a tail current regulator. The same control signals are applied to a slew boost controller, whose output increases as the differential between the control signals increase. The tail current regulator generates a bias signal that sets a minimum tail current. The tail current is controlled to be the minimum tail current until the slew boost output signal exceeds a threshold, whereupon the tail current increases in response to an increasing differential between the control signals. Common mode rejection is not adversely affected by the slew boost controller generating a slightly varying current under common mode conditions due to the minimum tail current. | 09-18-2014 |
20140266393 | BIPOLAR TRANSISTOR WITH LOWERED 1/F NOISE - In a bipolar transistor, a thin gate oxide, preferably less than 600 Å, is formed over the base surface region between the emitter and collector. A conductive gate, such as doped polysilicon, is then formed over the gate oxide and biased at the emitter voltage. In the example of a PNP transistor, when the emitter is forward biased with respect to the base to turn the transistor on, the gate is at a positive potential relative to the base. This causes the holes in the base conducting the emitter-collector current to be repelled away from the surface, and the electrons in the base to be attracted to the surface, so that more of the emitter-collector current flows deeper into the base. Thus, the effect of defects at the base surface is mitigated, and 1/f noise is reduced. The invention is equally applicable to PNP and NPN transistors. Other benefits result. | 09-18-2014 |
20140266108 | SINGLE SUPPLY AMPLIFIER WITH SWING TO GROUND - An amplifier circuit has a voltage input terminal, for receiving Vin, and a voltage output terminal, for outputting Vout. A feedback circuit controls Vout to match Vin. A differential input stage receives Vin and Vout and generates a first output signal. An output stage comprises a pull down circuit for Vout. A main MOSFET is controlled by the first output signal to pull down Vout to match Vin when Vout is above a threshold voltage Vtrans. An auxiliary MOSFET, in parallel with the main MOSFET, is controlled by the first output signal to pull down Vout to match Vin when Vout is below Vtrans. The main MOSFET is turned substantially off when Vout is below Vtrans. A headroom generator coupled between the Vout terminal and a drain of the auxiliary MOSFET allows the auxiliary MOSFET to operate in its active region and pull Vout to ground. | 09-18-2014 |
20140241400 | ROTATING 3-WIRE RESISTANCE TEMPERATURE DETECTION EXCITATION CURRENT SOURCES AND METHOD - In a temperature sensing circuit, a method for measuring a resistance of a RTD device to sense temperature includes (a) connecting a first terminal of the RTD device to a first current source and connecting a second terminal of the RTD device to a second current source; (b) measuring a first voltage across the RTD device; (c) connecting the second terminal of the RTD device to the first current source and connecting the first terminal of the RTD device to the second current source; (d) measuring a second voltage across the RTD device; and (e) deriving the resistance of the RTD device based on the first voltage measurement and the second voltage measurement. The RTD device may be connected in series with a sense resistor to ground. | 08-28-2014 |
20140240035 | SYNCHRONIZED CHARGE PUMP-DRIVEN INPUT BUFFER AND METHOD - An integrated circuit includes (a) an analog-to-digital converter operated according to a first clock signal; and (b) a charge pump circuit providing a negative power supply voltage to the integrated circuit, the charge pump circuit being operated according to a second clock signal having a frequency that is different from a frequency of the first clock signal, such that a noise level introduced by the charge pump into the analog-to-digital converter is less than the average noise level over a predetermined range of frequencies for the second clock signal. The integrated circuit may further include a clock divider circuit (e.g., a programmable clock divider) that generates both the first clock signal and the second clock signal. | 08-28-2014 |
20140239970 | THERMOCOUPLE OPEN-CIRCUIT DETECTION CIRCUIT AND METHOD - A method for detecting an open-circuit in an external thermocouple network includes these steps: (a) injecting a current pulse of a predetermined duration into the external thermocouple network; and (b) measuring the voltage across the pair of terminals after a time period following the predetermined duration. In one example, the time period is sufficiently long to allow the current pulse to dissipate from the external thermocouple circuit when a thermocouple in the external thermocouple network does not have an open circuit. The thermocouple network may include a resistor-capacitor network provided between the thermocouple and one of the terminals. | 08-28-2014 |
20140233288 | HIGH-FREQUENCY RMS-DC CONVERTER USING CHOPPER-STABILIZED SQUARE CELLS - An RMS-DC converter includes a chopper-stabilized square cell that eliminates offset, thus enabling high-bandwidth operation. The chopper-stabilized offset requires only a small portion of the circuitry (i.e., a single component square cell) which operates at high frequencies, and is amenable to using high-bandwidth component square cells. Using the chopping technique minimizes required device sizes without compromising an acceptable square cell dynamic range, thereby maximizing the square cell bandwidth. The RMS-DC converter consumes less power than conventional RMS-to-DC converters that requires a high-frequency variable gain amplifier. | 08-21-2014 |
20140191768 | METHOD AND SYSTEM FOR MEASURING THE RESISTANCE OF A RESISTIVE STRUCTURE - Method and system for measuring the resistance of a resistive structure having at least three nodes. A first calibration signal is determined by measuring a voltage at an output of the resistance structure when no calibration current is injected into a third node between the first and second nodes of the structure. A calibration current is then injected into the third node and a second calibration signal is determined. The absolute value of the difference between the first calibration signal and the second calibration signal is determined, the absolute value being proportional to a product of the resistance of the resistive structure and the calibration current. | 07-10-2014 |
20140191741 | LOW CURRENT DC-DC CONVERTER WITH INTEGRATED LOW CURRENT COULOMB COUNTER - A power supply system includes a regulator circuit responsive to an input signal at the input node for producing an output signal at the output node at a desired level. The regulator circuit has a controller, an inductive element and a first switch coupled to the inductor element and controlled by the controller to produce the output signal. Also, the power supply system includes a Coulomb counter for producing a Coulomb count signal proportional to the number of Coulombs passing from the input node to the output node. The Coulomb counter is enabled by an enabling signal representing a predetermined time period, for determining the number of Coulombs passing from the input node to the output node during that predetermined time period. | 07-10-2014 |
20140167715 | POWER CONVERTER FOR GENERATING BOTH POSITIVE AND NEGATIVE OUTPUT SIGNALS - A power converting system is responsive to an input signal to produce an output signal regulated with respect to the input signal. The power converting system has an input node for receiving the input signal, an output node for producing the output signal, and first and second inductive elements. The first inductive element has a first node coupled to the input node, the second inductive element has a first node coupled to the output node. A first switching element is coupled to a second node of the first inductive element. A first capacitive element is coupled between the second node of the first inductive element and a second node of the second inductive element. A control circuit is provided for controlling the first switching element. The control circuit is configured to set a duty cycle of the first switching element to a first value for providing the output signal of a first polarity in response to the input signal of the first polarity, and to set the duty cycle of the first switching element to a second value for providing the output signal of a second polarity in response to the input signal of the first polarity. | 06-19-2014 |
20140139198 | FEED FORWARD CURRENT MODE SWITCHING REGULATOR WITH IMPROVED TRANSIENT RESPONSE - A switching regulator circuit incorporates an offset circuit, connected in a control loop of the regulator circuit, that, in response to a signal indicating an imminent load current step, adjusts a duty cycle of a power switch for the current step prior to the regulator circuit responding to a change in output voltage due to the current step. In one embodiment, a load controller issues a digital signal shortly before a load current step. The digital signal is decoded and converted to an analog offset signal in a feedback control loop of the regulator to immediately adjust a duty cycle of the switch irrespective of the output voltage level. By proper timing of the offset, output voltage ripple is greatly reduced. The current offset may also be used to rapidly change the output voltage in response to an external signal requesting a voltage step. | 05-22-2014 |
20140132432 | ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented. | 05-15-2014 |
20140132431 | ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented. | 05-15-2014 |
20140132430 | ANALOG-TO-DIGITAL CONVERTER SYSTEM AND METHOD - An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented. | 05-15-2014 |
20140129850 | POLARITY CORRECTION BRIDGE CONTROLLER FOR COMBINED POWER OVER ETHERNET SYSTEM - A system for combining power to a load in a Powered Device (PD) using Power Over Ethernet (PoE) receives power from a first channel and power from a second channel, via four pairs of wires. A MOSFET bridge for each channel is initially disabled. A bridge controller IC simultaneously senses all the voltages and controls the bridge MOSFETs. The bridge controller IC also contains a first PoE handshaking circuit. A second PoE handshaking circuit is external to the bridge controller IC and operates independently. The body diodes in the MOSFET bridge initially couple the first channel to the second PoE handshaking circuit while isolating the second channel. The second handshaking circuit then couples the first channel to the load. The first handshaking circuit then carries out a PoE handshaking routine for the second channel. Ultimately, the bridge controller controls the bridge MOSFETs to couple both channels to the load. | 05-08-2014 |
20140111174 | Magnetic Field Cancellation in Switching Regulators - This invention uses new switching regulator structures to split single magnetic loops into multiple magnetic loops, with linked opposing magnetic fields, to cause a cancelling effect, resulting in a much lower overall magnetic field. This results in lower EMI. In one embodiment, synchronously switched transistors are divided up into parallel topside transistors and parallel bottomside transistors. The topside transistors are positioned to oppose the bottomside transistors, and bypass capacitors are connected between the pairs to create a plurality of current loops. The components are arranged to form a mirror image of the various current loops so that the resulting magnetic fields are in opposite directions and substantially cancel each other out. Creating opposite current loops may also be achieved by forming the conductors and components in a FIG. | 04-24-2014 |
20140111110 | PWM CONTROL FOR LEDS WITH REDUCED FLICKER WHEN USING SPREAD SPECTRUM SWITCHING FREQUENCIES - A technique to eliminate perceptible flickering by LEDs being dimmed by PWM pulses is disclosed. A controllable oscillator controls a switching frequency of a converter for supplying a regulated current or regulated voltage. The converter controls a first switch at a switching frequency. A varying second signal level is generated by a spread spectrum control (SSC) circuit for controlling the oscillator to vary the switching frequency during operation. A PWM dimming circuit generates a string of PWM pulses that control a switch in series with the LEDs. The SSC circuit is synchronized with the PWM pulses to generate the same second signal level at a start of each PWM pulse, such that the switching frequency of the converter is forced to be substantially the same at the start of each PWM pulse while the pulse widths are constant. The repeating driving current waveform eliminates perceptible flicker by the LEDs. | 04-24-2014 |
20140101349 | CONFIGURABLE SERIAL INTERFACE - Method and system for configuring a serial interface. The system includes one or more input nodes each coupled to a corresponding serial bus. One or more output nodes are coupled to a respective serial bus, each output node having a respective driver. A voltage detection circuit determines the voltage at a configuration node. Mode of serial bus operation is based on the voltage level detected at the configuration node. In at least one mode of serial bus operation, the configuration node is used as a mode select input and power source for at least one output driver. | 04-10-2014 |
20140097814 | SYSTEM AND METHOD FOR INPUT VOLTAGE REGULATION OF SWITCH MODE SUPPLIES IMPLEMENTING BURST MODE OPERATION - Switching regulator methods and systems are provided for supplying output current at a regulated voltage level to a load. Upon determining that the output current is not below a predetermined current threshold, the regulator is operated in a continuous mode. The input voltage is monitored. If the input voltage is not below a first input threshold level, the system remains in continuous mode. Otherwise, the system enters a burst mode in which the switch mode power supply is turned OFF, thereby reducing transistor gate charge losses. | 04-10-2014 |
20140097791 | AUTO RESONANT DRIVER FOR WIRELESS POWER TRANSMITTER SENSING REQUIRED TRANSMIT POWER FOR OPTIMUM EFFICIENCY - An auto-resonant driver for a transmitter inductor drives the inductor at an optimal frequency for maximum efficiency. The transmitter inductor is magnetically coupled, but not physically coupled, to a receiver inductor, and the current generated by the receiver inductor is used to power a load. The system may be used, for example, to remotely charge a battery (as part of the load) or provide power to motors or circuits. A feedback circuit is used to generate the resonant driving frequency. A detector in the transmit side wirelessly detects whether there is sufficient current being generated in the receiver side to achieve regulation by a voltage regulator powering the load. This point is achieved when the transmitter inductor peak voltage suddenly increases as the driving pulse width is ramped up. At that point, the pulse width is held constant for optimal efficiency. | 04-10-2014 |
20140062407 | MONITORING CELLS IN ENERGY STORAGE SYSTEM - A system for monitoring an energy storage system composed of multiple cells connected in series has a chain of monitors including at least first and second monitors. The first monitor is configured for monitoring at least a first cell in the energy storage system to produce first monitored data. The second monitor is configured for monitoring at least a second cell in the energy storage system to produce second monitored data. The first monitor is further configured for transferring the first monitored data to the second monitor for delivery to a controller. | 03-06-2014 |
20140022823 | Temperature Compensation of Output Diode in an Isolated Flyback Converter - An isolated flyback converter having temperature compensation (TC) uses primary side sensing and an output diode, the output diode having a variable voltage drop related to its temperature. A feedback voltage V | 01-23-2014 |
20140002043 | Current Mode Voltage Regulator With Auto-Compensation | 01-02-2014 |
20130320951 | EXPANDING DC/DC CONVERTER INTO MULTIPHASE DC/DC CONVERTER - A DC/DC converter configurable for operating as a multiphase DC/DC. A controller produces a master drive signal for controlling a primary power switch to produce the output DC signal at a desired level. Multiple secondary power stages are coupled between the input and the output nodes for producing an output DC signal. Each of the multiple secondary power stages has at least one secondary power switch responsive to the input DC signal for producing the output DC signal. An expander system configures the DC/DC converter for operation in a multiphase DC/DC conversion mode. The expander system is responsive to the master drive signal for producing multiple slave drive signals respectively supplied to the multiple secondary power stages for controlling secondary power switches. The slave drive signals have phases shifted with respect to the master drive signal and with respect to each other. | 12-05-2013 |
20130278453 | ANALOG-TO-DIGITAL CONVERTER SYSTEM AND METHOD - An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented. | 10-24-2013 |
20130271216 | High Side Current Sense Amplifier - A single stage current sense amplifier is described that generates a differential output that is proportional to a current through a sense resistor. The voltage across the sense resistor is Vsense. The current sense amplifier includes a differential transconductance amplifier having high impedance input terminals. An on-chip RC filter filters transients in the Vsense signal. A feedback circuit for each leg of the amplifier causes a pair of input transistors to conduct a fixed constant current irrespective of Vsense, which stabilizes the transconductance. A gain control resistor (Re) is coupled across terminals of the pair of input transistors and has Vsense across it. The current through the gain control resistor is therefore Vsensex1/Re. A level shifting circuit coupled to each of the input transistors lowers a common mode voltage at an output of the amplifier. Chopper circuits at the input and output cancel any offset voltages. | 10-17-2013 |
20130257538 | COMMON MODE INPUT CONTROL FOR SWITCHED CAPACITOR AMPLIFIER IN PIPELINE ANALOG-TO-DIGITAL CONVERTER - A common mode bias circuit may include a weak common mode bias generator and a common mode bias capacitance. During a first state of the common mode bias circuit, the weak common mode bias generator may be coupled to the common mode bias capacitance and may impart to them a predefined common mode signal level. During a second state of the common mode bias circuit, the common mode bias capacitance may be coupled to differential inputs of an amplifier in a manner that establishes an input common mode level for the amplifier. | 10-03-2013 |
20130235620 | Isolated Flyback Converter with Sleep Mode for Light Load Operation - A flyback converter uses primary side sensing to sense the output voltage for regulation feedback. A comparator on the primary side detects whether the output voltage has exceeded a predetermined regulated voltage by a first threshold to detect an over-voltage condition, resulting from a current generated by the converter exceeding the load current. Triggering of the comparator causes the converter to enter a non-switching sleep mode, whereby the output voltage droops over a period of time. When the output voltage has drooped below the predetermined regulated voltage by a second threshold, a synchronous rectifier is controlled to turn on, then off, to generate a pulse in the primary winding. Upon detection of the pulse, the sleep mode is terminated, and normal operation resumes until a regulated voltage is achieved or until the first threshold is again exceeded by the output voltage. | 09-12-2013 |
20130207629 | NEGATIVE SLOPE COMPENSATION FOR CURRENT MODE SWITCHING POWER SUPPLY - Generated are an error signal representative of a difference between a signal representative of the output voltage of a current mode switching power supply and a reference voltage, and a peak current threshold signal that is indicative of a peak current that should be reached in an inductor within the power supply during each cycle of a periodic clock signal and that has a level that is based on the error signal. A switch control signal regulates the voltage output of the power supply by closing and then opening a power switch during each cycle of the periodic clock signal. Timing of opening is based on the peak current threshold signal. Negative slope compensation causes the switch control circuit to delay opening the power switch during each cycle of the periodic clock signal in an amount that decreases with increasing duty cycles of the switch control signal. | 08-15-2013 |
20130194836 | Isolated Flyback Converter With Efficient Light Load Operation - A flyback converter uses primary side sensing to sense the output voltage for regulation feedback. Such sensing requires a predetermined minimum duty cycle even with very light load currents. Therefore, such a minimum duty cycle may create an over-voltage condition. In the flyback phase, after a minimum duty cycle of the power switch at light load currents, a synchronous rectifier turns off approximately when the current through the secondary winding falls to zero to create a discontinuous mode. If it is detected that there is an over-voltage, the synchronous rectifier is turned on for a brief interval to draw a reverse current through the secondary winding. When the synchronous rectifier shuts off, a current flows through the primary winding via a drain-body diode while the power switch is off. Therefore, excess power is transferred from the secondary side to the power source to reduce the over-voltage so is not wasted. | 08-01-2013 |
20130154373 | PRIMARY UNIT CONTROL OF RESONANT INDUCTIVE POWER TRANSFER SYSTEM FOR OPTIMUM EFFICIENCY - A circuit and method for wirelessly coupling an electrical energy between an electrical energy source and at least one load is provided. The circuit comprises a primary unit and at least one secondary unit. The primary unit includes an input node for receiving an input voltage produced by the energy source; a transmitter circuit including a transmitter coil configured to generate an electromagnetic field; and a regulator. The regulator is configured to sense a current consumption of the primary unit, determine a gradient of the current consumption with respect to different input voltages, and determine an optimal input voltage based on the gradient. The at least one secondary unit comprises a receiver circuit and a load. The receiver unit includes a coil that wirelessly and inductively couples with the electromagnetic field of the primary unit to receive power therefrom. The receiver unit further includes a regulator circuit configured to provide a constant power to an output node. | 06-20-2013 |
20130149981 | Second Order Intermodulation Canceller - A technique for cancelling out target IM2 components in a wireless receiver's mixer output is disclosed. A differential RF signal and a differential local oscillator (LO) signal are mixed by a mixer to demodulate the RF signal. A first common node signal is generated between a first resistor and a second resistor coupled across the mixer's differential output terminals. A second common node signal is generated between a third resistor and a fourth resistor coupled across the differential output terminals, where a capacitor is coupled between the second common node and a power supply terminal. The second common node signal provides a stable reference signal for IM2 components above a certain frequency. The two common node signals are subtracted to create a difference signal. The difference signal is scaled by a scaling factor obtained during calibration. The scaled difference signal is coupled to the mixer output to offset IM2 distortion. | 06-13-2013 |
20130124112 | Anemometer Detecting Thermal Time Constant of Sensor - An anemometer and method for analyzing fluid flow is described. In one embodiment, a transistor sensor is heated by applying power to cause its base-emitter junction to rise from an ambient first temperature to a second temperature. The power is removed, and the Vbe is measured at intervals as the junction cools. The Vbe equates to a temperature of the junction. The temperature exponentially decreases, and the time constant of the decay corresponds to the fluid flow velocity. A best fit curve analysis is performed on the temperature decay curve, and the time constant of the exponential decay is derived by a data processor. A transfer function correlates the time constant to the fluid flow velocity. The transistor is thermally coupled to a metal rod heat sink extending from the package, and the characteristics of the rod are controlled to adjust the performance of the anemometer. | 05-16-2013 |
20130113639 | SYSTEMS AND METHODS FOR RANDONMIZING COMPONENT MISMATCH IN AN ADC - Circuits and methods for converting a signal from analog to digital. A random number generator provides a random number to a memory. The memory is preconfigured to include codes of predetermined digital to analog (DAC) configurations that provide the maximum amount of DAC gradient suppression. At least one Flash reference generation DAC (FRGD) has an input coupled to the memory unit and an output providing a reference voltage level for its respective Flash comparator. The Flash comparators compare the analog input signal to their respective reference voltage and provide a digital output signal based on the comparison. | 05-09-2013 |
20130113275 | SWITCHING OF CONDUCTOR PAIR IN POWER OVER ETHERNET SYSTEM - Technique for providing power to a powered device (PD) over a cable having first and second sets of twisted pairs, such as signal pairs and spare pairs. Power Sourcing Equipment (PSE) circuitry is coupled via a first switch to the second set, e.g. to the spare pairs. A switch control circuit turns the first switch off to enable the PSE circuitry to perform a prescribed operation in connection with the PD over only the first set, e.g. over the signal pairs, and turns the first switch on to enable the PSE circuitry to perform the prescribed operation in connection with the PD over the first and second sets. | 05-09-2013 |
20130099746 | OPTIMIZED BI-DIRECTIONAL BALANCING METHOD AND SYSTEM - A battery balancing method and system which includes a plurality of cells connected in series, a balancer for each cell, a monitor configured to determine a state of charge (SOC) of each cell, and a microprocessor. The microprocessor iteratively calculates a SOC error for each cell, based on a theoretical balancing of the Min Q cell and the Max Q cell, until the SOC error is less than or equal to a first threshold; and iteratively re-calculates SOC error based on a net charge or discharge time for each balancer until the SOC error is less than or equal to a second threshold; and when the SOC error is less than or equal to the second threshold, instructs each balancer to physically balance each respective cell based on the respective calculated net charge or discharge time when the second threshold is met. | 04-25-2013 |
20130076309 | STACKABLE BI-DIRECTIONAL MULTICELL BATTERY BALANCER - A battery balancing system includes at least one sub-stack, each sub-stack comprising a plurality of cells connected in series. The system also includes a balancing module for each sub-stack comprising an independent bidirectional balancer for each cell in the sub-stack. The system includes a daisy chained stackable serial port. The balancing system senses a state of charge (SOC) of each cell in each sub-stack. The average SOC of the sub-stack is determined. For a weak cell, additional charge is provided from its respective sub-stack during the discharging of the battery. For a strong cell, additional charge is removed and provided to its respective sub-stack during discharging of the battery. Any number of sub-stacks can be stacked in series while maintaining the same serial control, allowing a theoretically unlimited number of cells to be supported from a single communication port without the need for additional digital isolators. | 03-28-2013 |
20130049715 | FEEDBACK CONTROL OF A DC/DC POWER CONVERTER - A current mode power conversion system and method operates in cycles. Each cycle includes an on time and an off time. The system includes an inductor connected to store energy during the on time of each cycle and use the energy during the off time of each cycle. The system provides a stable output voltage and a maximum-limited output current to a load during constant load conditions. The system comprises a feedback control linearly operable so as to control the output voltage across the load during constant load conditions, and non-linearly operable so as to control the output voltage across the load during certain detected changes in load conditions as a function of the derivative of the current in the inductor so as to speed up the transient response of the power conversion system when a fault condition exists. | 02-28-2013 |
20130049469 | POWER COMBINING IN POWER OVER ETHERNET SYSTEMS - A technique for combining power to a single load from multiple power supplies using power over Ethernet (PoE) is disclosed. Each power supply is coupled to associated power sourcing equipment (PSE) providing PoE, and each PSE has a current limit. The power supplies supply approximately the same voltage, but the output voltages are typically not exactly equal. All the power supplies are connected via diodes to a common load terminal. The power supply outputting the highest voltage first supplies power to the load terminal, since only its diode is forward biased, until a PoE current limit is reached. Then its duty cycle is limited. The load terminal voltage is then inherently lowered to cause the diode of the power supply with the next highest output voltage to connect it to the load to supply additional power to the load as the first power supply continues to supply its limited current. | 02-28-2013 |
20130044020 | RADAR SYSTEM AND METHOD FOR PROVIDING INFORMATION ON MOVEMENTS OF OBJECT'S SURFACE - A system for producing an output signal representing movement of an object's surface has a continuous wave (CW) signal source for producing an CW signal directed at the object's surface. The CW signal is produced at a first frequency. A receiving element receives a signal reflected from the object's surface when the CW signal hits this surface. A down-converting frequency mixer converts the received signal into a signal of a second frequency lower than the first frequency. The frequency mixer is configured to produce an output signal representing an amplitude-modulated (AM) component of the received signal and having a parameter representing movement of the object's surface. | 02-21-2013 |
20130043950 | COMMON MODE INPUT CONTROL FOR SWITCH CAPACITOR AMPLIFIER IN PIPELINE ANALOG-TO-DIGITAL CONVERTER - A common mode bias circuit may include a weak common mode bias generator and a common mode bias capacitance. During a first state of the common mode bias circuit, the weak common mode bias generator may be coupled to the common mode bias capacitance and may impart to them a predefined common mode signal level. During a second state of the common mode bias circuit, the common mode bias capacitance may be coupled to differential inputs of an amplifier in a manner that establishes an input common mode level for the amplifier. | 02-21-2013 |
20130036247 | I2C ISOLATED, BIDIRECTIONAL COMMUNICATION SYSTEM WITH ISOLATED DOMAIN CURRENT SOURCE PULL-UPS - This disclosure describes a circuit implementation providing the functions necessary to implement an isolated I | 02-07-2013 |
20130015830 | Switching Power Supply Having Separate AC And DC Current Sensing PathsAANM Zhang; JindongAACI FremontAAST CAAACO USAAGP Zhang; Jindong Fremont CA US - In a current mode controlled switching power supply, current through the inductor is sensed to determine when to turn off or on the switching transistors. The inductor current has a higher frequency AC component and a lower frequency DC component. The AC current feedback path, sensing the ramping ripple current, is separate from the DC current path, sensing the lower frequency average current. Separating the current sensing paths allows the signal to noise ratio of the AC sense signal to be increased and allows the switching noise to be filtered from the DC sense signal. The gain of the DC sense signal is adjusted so that the DC sense signal has the proper proportion to the AC sense signal. The AC sense signal and the DC sense signal are combined by a summing circuit. The composite sense signal is applied to a PWM comparator to control the duty cycle of the switch. | 01-17-2013 |
20120326909 | SIMULTANEOUSLY-SAMPLING SINGLE-ENDED AND DIFFERENTIAL TWO-INPUT ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter (ADC) system configured to receive a first and a second analog quantity and to provide a plurality of numerical parameters representative of the first and second analog quantities. The ADC system includes a first, a second, and a third ADC circuit, and a digital interface circuit. The first ADC circuit is configured to provide a first code representative of the first analog quantity and to provide a first analog residue quantity representative of the first analog quantity with respect to the first code. The second ADC circuit is configured to provide a second code representative of the second analog quantity and to provide a second analog residue quantity representative of the second analog quantity with respect to the second code. The third ADC circuit is configured to receive the first and second analog residue quantities, and to provide a third digital code representative of a difference of the first and second analog residue quantities. The digital interface circuit is configured to receive the first, second, and third codes, and to provide the plurality of numerical parameters representative of the first and second analog quantities. | 12-27-2012 |
20120313800 | SYSTEM AND METHODS TO IMPROVE THE PERFORMANCE OF SEMICONDUCTOR BASED SAMPLING SYSTEM - Circuits and methods that improve the performance of electronic sampling systems are provided. Impedances associated with sampling semiconductor switches are maintained substantially constant during sample states, at least in part, by compensating for encountered input signal variations in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch. | 12-13-2012 |
20120313670 | SYSTEM AND METHODS TO IMPROVE THE PERFORMANCE OF SEMICONDUCTOR BASED SAMPLING SYSTEM - Circuits and methods that improve the performance of electronic sampling systems are provided. Impedances associated with sampling semiconductor switches are maintained substantially constant during sample states, at least in part, by compensating for encountered input signal variations in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch. | 12-13-2012 |
20120313667 | SYSTEM AND METHODS TO IMPROVE THE PERFORMANCE OF SEMICONDUCTOR BASED SAMPLING SYSTEM - Circuits and methods that improve the performance of electronic sampling systems are provided. Impedances associated with sampling semiconductor switches are maintained substantially constant during sample states, at least in part, by compensating for encountered input signal variations in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch. | 12-13-2012 |
20120313666 | SYSTEM AND METHODS TO IMPROVE THE PERFORMANCE OF SEMICONDUCTOR BASED SAMPLING SYSTEM - Circuits and methods that improve the performance of electronic sampling systems are provided. Impedances associated with sampling semiconductor switches are maintained substantially constant during sample states, at least in part, by compensating for encountered input signal variations in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch. | 12-13-2012 |
20120299560 | Balancing Temperatures in A Multi-Phase DC/DC Converter - In one embodiment, a temperature compensation circuit is used in a peak current control multi-phased DC/DC converter. Each phase has a duty cycle needed to generate a regulated output voltage of the converter. The temperature for each phase in the converter is sensed to generate corresponding first signals for all the phases. The first signals are averaged to generate a second signal corresponding to the average temperature of all the phases. For each phase, a third signal is generated corresponding to the difference between the first signal and the second signal. The third signal is then used to adjust the duty cycle of each phase to control the temperature of each phase to be substantially equal to the average temperature. In the steady state, the output voltage of the converter will be the desired voltage and the temperatures of the phases will be balanced. | 11-29-2012 |
20120274496 | Current Steering Circuit with Feedback - A differential current steering (CS) circuit uses feedback from the differential output nodes A and B to cause current steering devices (e.g., MOSFETs) to effectively exhibit an infinite output impedance when conducting. Therefore, the signal on the output nodes A or B does not significantly change the voltage at the common node, This is particularly useful when the differential output nodes are connected to differential output buses in a digital-to-analog converter. The circuit dynamically cancels, though feedback, the signal induced at the common node by the signal present at the “steered” output node. Therefore, the CS circuit effectively presents an infinite output impedance between the common node and the output nodes. In some cases, it may be desirable to not create a substantially infinite output impedance for the CS circuit but control the impedance to a predefined level to counter other distortions in the system. | 11-01-2012 |
20120274360 | SWITCHED CAPACITANCE VOLTAGE DIFFERENTIAL SENSING CIRCUIT WITH NEAR INFINITE INPUT IMPEDANCE - A circuit may sense the differential voltage across two nodes that each have a non-zero common mode voltage. The circuit may have a positive input impedance that is imposed across the nodes. An impedance compensation circuit may generate a compensation current that is delivered to the nodes that substantially cancels the loading effect of the positive input impedance. The impedance compensation circuit may generate a negative input impedance that is imposed across the two nodes that is substantially the same as the positive input impedance. The impedance compensation circuit may instead be configured to deliver the compensation current to the nodes. | 11-01-2012 |
20120218022 | Accurate Current Sensing with Heat Transfer Correction - In one embodiment, a current sensing circuit corrects for the transient and steady state temperature measurement errors due to physical separation between a resistive sense element and a temperature sensor. The sense element has a temperature coefficient of resistance. The voltage across the sense element and a temperature signal from the temperature sensor are received by processing circuitry. The processing circuitry determines a power dissipated by the sense element, which may be instantaneous or average power, and determines an increased temperature of the sense element. The resistance of the sense element is changed by the increased temperature, and this derived resistance Rs is used to calculate the current through the sense element using the equation I=V/R or other related equation. The process is iterative to continuously improve accuracy and update the current. | 08-30-2012 |
20120207190 | Circuits For And Methods Of Accurately Measuring Temperature Of Semiconductor Junctions - A system for and method of providing a signal proportional to the absolute temperature of a semiconductor junction is provided. The system comprises: a preprocessing stage configured and arranged so as to process a signal from the semiconductor junction so as to produce a preprocessed signal including a resistance error term; and a temperature to voltage converter stage for converting the preprocessed signal to a voltage proportional to absolute temperature representing the absolute temperature of the semiconductor junction; wherein the system is configured and arranged so as to remove the resistance error term so as to produce a resistance error free signal representative of the semiconductor junction temperature. | 08-16-2012 |
20120206284 | INTERPOLATING DIGITAL-TO-ANALOG CONVERTER WITH SEPARATE BIAS CURRENT SOURCE FOR EACH DIFFERENTIAL INPUT TRANSISTOR PAIR - The most significant portion of a digital word may be converted into a high and a low analog voltage representative, respectively, of the highest and lowest possible values which a digital word could have with the most significant portion. An analog output may be produced by interpolating between the high and the low analog voltage in accordance with the value of the least significant portion of the digital word. A differential transconductance input stage may have pairs of differential input transistors. For each differential input transistor pair, a separate bias current circuit may provide a bias current to the differential input transistor pair, separate from the bias current provided to the other differential input transistor pairs. All bias current circuits may be identical in a linear interpolator. The transconductance input stage may have a gain of at least 20 dB and may result in an integral non-linearity in the analog output of no more than 0.08 times the weight of the least significant bit of the digital word. | 08-16-2012 |
20120161722 | SYSTEM AND METHOD FOR CHARGING CAPACITORS USING AUTOMATIC CELL BALANCING - A circuit for charging a capacitor block including series-connected capacitive elements has an input node for receiving an input, an output node coupled to the capacitor block, a third capacitive element connectable to the input node and the output node, and first and second switching circuitries coupled to the third capacitive element. A voltage sensor determines a relationship between first voltage at the first capacitive element and second voltage at the second capacitive element to separately control switching of the first and second switching circuitries in accordance with the relationship between the voltages. | 06-28-2012 |
20120139642 | Bias Point Setting for Third Order Linearity Optimization of Class A Amplifier - An actual linear amplifier distorts an input signal, such as an RF signal, and generates third order intermodulation (IM3) products. In an embodiment of a Class A amplifier, the linear amplifier is a bipolar, common emitter-configured (CE) transistor using a cascode transistor to provide a fixed collector bias voltage to the CE transistor. The CE transistor has a transconductance vs. base-emitter voltage (V | 06-07-2012 |
20120139629 | Third Order Intermodulation Cancellation by In-Line Generated Signal - An actual linear amplifier distorts an input signal, such as an RF signal, and generates third order intermodulation (IM3) products. A single-port predistortion circuit is connected at a single node of an input line to the amplifier via an AC coupling capacitor. The fundamental frequency of the input signal is applied to a forward biased diode junction. The current through the diode is applied to a second capacitor. The appropriate setting of a tuning device, such as a tunable resistor or a tunable capacitor, causes the predistortion circuit to invert the second harmonic generated by the diode. The inverted second harmonic signal is applied to the single node of the input line to add predistortion to the signal applied to the amplifier. The predistortion cancels or substantially reduces the IM3 products at the output of the amplifier. | 06-07-2012 |
20120139611 | HIGH DYNAMIC RANGE COULOMB COUNTER WHICH SIMULTANEOUSLY MONITORS MULTIPLE SENSE RESISTORS - A circuit may include a source of electrical energy and a plurality of current loads. Each load may be of a different amount. For each current load, a resistance may be in series between the source and the current load. The resistance may be weighted inversely proportional to the amount of the current load with respect to the other resistances. For each resistance, an integrator may generate an integrated output representative of an integration of the current traveling through the resistance. A summer may generate a summed output which is representative of the sum of each of the integrated outputs, weighted inversely proportional to the resistance that is associated with the integrated output. | 06-07-2012 |
20120026027 | A/D CONVERTER USING ISOLATION SWITCHES - In an A/D converter, isolation switches are used between the capacitors and the conversion switches. The conversion switches are those switches used to selectively couple the plates of the binary weighted capacitors to either Vref or 0 volts during the A/D conversion process. During sampling of the input voltage signal, the isolation switches are opened to isolate the conversion switches from the wide range of possible input voltages at the bottom plates of the capacitors. Therefore, the voltage across the conversion switches is substantially limited to Vref. Hence, the conversion switches can be very fast low voltage switches. After sampling of the input voltage, when the sampled input voltage is locked in, the conversion switches operate normally to selectively connect the capacitor plates to either Vref or 0 volts for successively approximating the input voltage, whereby a digital code representing the sampled input voltage is generated. | 02-02-2012 |
20120019228 | SYNCHRONOUS RECTIFIER CONTROL FOR SYNCHRONOUS BOOST CONVERTER - A synchronous boost DC/DC conversion system comprises an input for receiving a DC input voltage, an output for producing a DC output voltage, a power switch controllable to adjust an output signal of the conversion system, and an inductor coupled to the input. A synchronous rectifier is configurable to create a conduction path between the inductor and the output to provide the inductor discharge. A control circuit is provided for controlling the synchronous rectifier as the input voltage approaches the output voltage, so as to adjust average impedance of the conduction path over a discharge period of the inductor. | 01-26-2012 |
20120013389 | Capacitively Coupled Switched Current Source - In the preferred embodiment, a current source is switchable between two precisely defined output currents. A terminal of a coupling capacitor is coupled to the gate of an output MOSFET. The other terminal of the capacitor is switched between two reference voltages to toggle the MOSFET to output the selected one of the two currents. A switchable bias voltage source is coupled to the gate only during the on state of the MOSFET to set the gate voltage of the MOSFET. The current output of the current source is quickly and accurately changed. A reference MOSFET is not directly coupled to the output MOSFET, so there are no slow settling components coupled to the gate of the output MOSFET. | 01-19-2012 |
20120007649 | METHOD FOR CLAMPING A SEMICONDUCTOR REGION AT OR NEAR GROUND - A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio. | 01-12-2012 |
20120001649 | LEADFRAME CURRENT SENSOR - A current sensor is disclosed. The current sensor includes a leadframe having a die paddle, a portion of the die paddle being configured as a resistive element through which current can flow, and an integrated circuit (IC) die attached and thermally coupled to the die paddle. The IC die includes a current sensing module configured to measure a voltage drop across the resistive element and convert the voltage drop measurement to a current measurement signal and a temperature compensation module electrically coupled to the current sensing module. The temperature compensation module is configured to adjust the current measurement signal to compensate for temperature-dependent changes in the resistive element. The temperature compensation module includes a temperature-sensitive element, with a portion of the temperature-sensitive element located directly over a portion of the resistive element. | 01-05-2012 |
20110299304 | DC/DC CONVERTER WITH MAGNETIC FLUX DENSITY LIMITS - A DC/DC converter may include a power stage circuit, a pulse generator circuit, a flux density monitor, and power control logic. The power stage circuit includes an input, an output, and a transformer with a core. The power stage circuit may be configured to operate in a power transfer mode during which power is transferred from the input to the output and a reset mode during which flux density in the core of the transformer is reduced. The pulse generator circuit may be configured to generate pulses that regulate the output of the power stage circuit. The flux density monitor circuit may be configured to generate flux density information indicative of the flux density of the core of the transformer during both the power transfer mode and the reset mode. The power stage control logic may be configured to regulate the output of the power stage circuit based on the pulses and to prevent the core of the transformer from saturating based on the flux density information. | 12-08-2011 |
20110298473 | DYNAMIC COMPENSATION OF AGING DRIFT IN CURRENT SENSE RESISTOR - A current sense resistor circuit may include a primary current sense resistor that drifts with age. A secondary current sense resistor may drift with age in substantial unison with the primary current sense resistor. A calibration resistor may not drift with age in substantial unison with the primary current sense resistor. A compensation circuit may compensate for aging drift in the resistance of the primary current sense resistor based on a comparison of the calibration resistor with the secondary current sense resistor. The secondary current sense resistor may be in parallel with the primary current sense resistor, except when the compensation circuit is comparing the calibration resistor with the secondary current sense resistor. | 12-08-2011 |
20110285569 | A/D Converter with Compressed Full-Scale Range - An embodiment of an analog-to-digital converter system is described wherein an analog voltage signal Vin(t) is provided by an input amplifier. The analog signal Vin(t) has a predetermined full-scale range that is less wide than a reference voltage (Vref) range used by a downstream ADC to derive a first digital (numerical) representation D | 11-24-2011 |
20110241772 | ERROR AMPLIFIER FOR REGULATING SINGLE FEEDBACK INPUT AT MULTIPLE LEVELS - An error amplifier may be part of a voltage regulator and may include a single feedback input configured to receive a feedback signal. A single error output may be configured to provide an error output signal indicative of error in the feedback signal. A comparison circuit may be configured to provide an error signal to the single error output which is indicative of a difference between the feedback signal and whichever one of a set of reference signals is closest to the feedback signal. One or more of these reference signals may each be derived from an offset from a ground reference. One or more of the other reference signals may each be derived from an offset from a non-ground reference, such as a source of power for the error amplifier. The error amplifier may be on a single integrated circuit along with an associated driver circuit. | 10-06-2011 |
20110187573 | TIME-MULTIPLEXED RESIDUE AMPLIFIER - A system is configured and a method is provided for receiving an input ratio represented by a first input signal and a second input signal, and producing an output ratio represented by a first output signal and a second output signal. The system is constructed and the method is provided for alternately operating in at least two time periods, wherein in one time period the first input signal, a low accuracy amplifier, and the first output signal are selectively coupled, and in another time period the input signal, the low accuracy amplifier, a high accuracy attenuator, and the second output signal are selectively coupled so as to maintain the output ratio proportional to the input ratio. | 08-04-2011 |
20110156687 | EFFICIENCY MEASURING CIRCUIT FOR DC-DC CONVERTER WHICH CALCULATES INTERNAL RESISTANCE OF SWITCHING INDUCTOR BASED ON DUTY CYCLE - An efficiency measuring circuit may measure the efficiency of a DC-DC converter having a switching inductor with an internal DC resistance and a plurality of electronic switches that control current through the inductor. A duty cycle circuit may measure the duty cycle of current flowing through one of the electronic switches. A current sense circuit may measure the current flowing through one of the electronic switches. An inductor voltage sensor circuit may measure the voltage across the inductor. A computation circuit may compute the internal DC resistance of the switching inductor based in part on the duty cycle measured by the duty cycle circuit and the current measured by the current sense circuit. The computation circuit may also compute the efficiency of the DC-DC converter. | 06-30-2011 |
20110148379 | CLEAN TRANSITION BETWEEN CCM AND DCM IN VALLEY CURRENT MODE CONTROL OF DC-TO-DC CONVERTER - A valley current mode DC-to-DC converter may include an electronic control system configured to cause the DC-to-DC converter to operate under a continuous current mode and a discontinuous current mode. The electronic control system may include a current sensing system configured to sense current traveling through an inductance, a dual threshold generator configured to generate a first and a different second threshold, and a comparator system configured to compare current sensed by the current sensing system with the first threshold when the DC-to-DC converter is operating in the continuous current mode and with the second threshold when the DC-to-DC converter is operating in the discontinuous current mode. | 06-23-2011 |
20110148373 | CONTINUOUSLY SWITCHING BUCK-BOOST CONTROL - A buck-boost converter with a switch controller may cause switches A, B, C, and/or D to cyclically close such that switches B and C are closed during at least one interval of each cycle during both the buck and boost modes of operation. The switch controller may in addition or instead cause switches A, B, C, and/or D to cyclically close based on a control signal such that switches A and D are closed during an interval of each cycle and such that these intervals are never both simultaneously modulated by a small change in the control signal during any mode of operation. | 06-23-2011 |
20110101937 | Voltage Regulator with Virtual Remote Sensing - An automatic voltage compensation circuit in a voltage regulator compensates the output voltage for a voltage drop along lines leading to a remote load. A load capacitor is connected across the load for providing a low impedance across the load during a test phase of the regulator. In one embodiment, during the test phase, the load current is changed up or down a small percentage (e.g., 10%). As a result, the regulator voltage changes due only to the line resistance since the load is bypassed by the load capacitor. The voltage drop at full load current is then derived by detecting the change in regulator output voltage (a fractional voltage drop) and multiplying it. The normal mode is resumed, and the derived voltage drop is added to the regulator output by either compensating the feedback loop or by adding the voltage drop to the output of the regulator. | 05-05-2011 |
20110063760 | DC/DC Converter Overcurrent Protection - A DC/DC converter and a method protect a MOSFET driven by the converter from overcurrent conditions. No extra pins are required to sense the current, which saves IC package area and cost. | 03-17-2011 |
20110062932 | DC/DC CONVERTER HAVING A FAST AND ACCURATE AVERAGE CURRENT LIMIT - In order to overcome the three main obstacles to obtaining a fast and accurate average current limit in a DC/DC converter, three distinct improvements are provided which can work in concert to achieve the goal. Each of the three parts comprises significant new improvements, and their use together to create an average current limit is also believed to be novel. The first improvement relates to providing a bias signal control configured to apply a variable DC bias signal to the compensation ramp signal generated in the DC/DC converter so that the compensating ramp signal is biased to zero at the end of each ON-time for each cycle so that the peak current limit is independent of the duty cycle of the pulse width modulation signal during current limit conditions. A second improvement relates to modulating the clamp voltage that establishes the peak current limit as a function of ripple of the inductor current for each cycle of the pulse width modulation signal so as to reduce or cancel the effect of the inductor ripple current on the average output current during current limit conditions. The third improvement relates to adjusting the frequency of the pulse width modulation signal during current limit conditions as a function of both the input voltage and the output voltage of the DC/DC converter. | 03-17-2011 |
20110062929 | FEEDBACK CONTROL OF A DC/DC POWER CONVERTER - A current mode power conversion system and method are described that provide a stable output voltage and a maximum-limited output current to a load. The system comprises:
| 03-17-2011 |
20110042792 | FLEXIBLE CONTACTLESS WIRE BONDING STRUCTURE AND METHODOLOGY FOR SEMICONDUCTOR DEVICE - A semiconductor device such as a field-effect transistor, improved to reduce device resistance, comprises a leadframe which includes a die paddle integral with a first set of leads and a second set of leads that is electrically isolated from the first set, a semiconductor die having its lower surface positioned on, and electrically connected to, the die paddle, and a conductive layer on the upper surface of the die. At least one electrically conductive wire, preferably plural wires, extend laterally across the second surface of the semiconductor die, are in electrical contact with the conductive layer, and interconnect corresponding second leads on opposite sides of the die. The plural wires may be welded to leads in succession by alternate ball and wedge bonds on each lead. The conductive layer may be an aluminized layer on which is formed a thin layer a solderable material, such as tin. A solder is deposited on the tin layer, enmeshing the wires. The wires, which preferably are made of copper, then may be bonded to the electrically conductive layer by melting the solder paste, preferably by heating the leadframe, allowing the solder to reflow and wet the wires, and then cool to produce a low resistance mass between the leads. | 02-24-2011 |
20100301923 | MONOLITHIC VOLTAGE REFERENCE DEVICE WITH INTERNAL, MULTI-TEMPERATURE DRIFT DATA AND RELATED TESTING PROCEDURES - A testing procedure may determine whether a monolithic voltage reference device meets a temperature drift specification. A first non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a first non-room temperature which is substantially different than room temperature. First non-room temperature information may be stored in a memory within the monolithic voltage reference device which is a function of the first non-room temperature output voltage. A second non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a second non-room temperature which is substantially different than the room temperature and the first non-room temperature. Second non-room temperature information may be stored in the memory without destroying the first non-room temperature information which is a function of the second non-room temperature output voltage. A determination may be made whether the monolithic voltage reference device meets the temperature drift specification based on a computation that is a function of both the first non-room temperature information and the second non-room temperature information. | 12-02-2010 |
20100289547 | PULSE-WIDTH MODULATION (PWM) WITH INDEPENDENTLY ADJUSTABLE DUTY CYCLE AND FREQUENCY USING TWO ADJUSTABLE DELAYS - A pulse width modulation circuit may generate an adjustable output signal that periodically transitions between a first and a second state with an adjustable duty cycle. A first pulse generator circuit may be configured to generate a first pulse signal that periodically transitions at an adjustable delay with respect to a periodic reference signal. A second pulse generator circuit may be configured to generate a second pulse signal that periodically transitions at an adjustable delay with respect to the periodic reference signal. A logic circuit may be configured to generate the adjustable output signal based on both the first and the second pulse signals. | 11-18-2010 |
20100271245 | COMPLEX-ADMITTANCE DIGITAL-TO-ANALOG CONVERTER - A circuit includes a digital-to-analog converter configured to produce an analog output signal (1) proportional to a reference signal and (2) as a function of a digital input signal. The converter comprises a plurality of non-trivially complex admittances configured so that each non-trivially complex admittance can be selectively switched as a function of the digital input signal so as to be coupled between a reference terminal configured to receive a reference signal and an output terminal. The method comprises selectively switching non-trivially complex admittances as a function of the digital signal between a reference terminal and an output terminal. | 10-28-2010 |
20100264890 | Voltage and Current Regulators with Switched Output Capacitors For Multiple Regulation States - A device and method of providing any one of a plurality of desired levels of a regulated signal output to a load is described, wherein each desired level is a function of a corresponding reference signal. The device is configured and the method is designed to (1) store each desired level of the regulated signal output on a switchable storage device; and (2) selectively switch the correct storage device to the output when switching from one regulated state to another so as to establish the desired level of regulated signal output. | 10-21-2010 |
20100259192 | BUCK-MODE BOOST CONVERTER WITH REGULATED OUTPUT CURRENT - An LED driver circuit that includes a buck-mode boost converter that provides a regulated output current and that requires only a single connection to each channel of LEDs. The buck-mode boost controller may include a current regulator that includes an integrator. The current regulator may be configured to integrate a difference between a reference signal that is representative of the desired level of the average current through the electronic power switch and a detected signal that is representative of the actual current that is being delivered to the buck-mode boost circuit through the electronic power switch. The reference signal to the integrator may not change during operation of the buck-mode converter. The current regulator may be configured to deactivate the integrator and/or to disconnect the detected signal from the integrator while the electronic power switch is off. | 10-14-2010 |
20100244793 | AVERAGE INDUCTOR CURRENT MODE SWITCHING CONVERTERS - An average current mode switching converter is described for providing a regulated output current independent of load conditions, and a regulated output voltage as a function of the load connected to the converter. The converter comprises: an inductor; a modulator configured to provide a regulated current through the inductor; a feed back loop coupled between the inductor and the modulator for regulating the current through the inductor; and a precharger configured and arranged so as to provide and maintain a preset minimum current through the inductor independent of the load so as to improve the recovery time of the converter from a step in the desired regulated output current. Also disclosed is a method of providing a regulated output current independent of load conditions at the output of an average current mode switching converter, and a regulated output voltage as a function of the load connected to the output of converter. The method comprises: providing a regulated current through an inductor; and regulating the current through the inductor independent of the load so that a minimum current flows through the inductor so as to improve the recovery time of the converter from a step in the desired regulated output current. | 09-30-2010 |
20100225294 | INRUSH CURRENT CONTROL SYSTEM WITH SOFT START CIRCUIT AND METHOD - A method of and system for controlling the inrush current generated in a MOSFET of an inrush current control system, wherein the MOSFET includes a source, gate and drain. The dV/dt at the drain of the MOSFET is controlled so as to set the inrush current level as a function of dV/dt, independent of current limit without requiring a separate capacitor connected between the gate and drain of the MOSFET so that the MOSFET can turn on and off more quickly. | 09-09-2010 |
20100171475 | SWITCHING MODE CONVERTERS - A switch mode converter is configured to convert an input DC voltage applied at one level at the converter input to an output DC voltage at a second level at the converter output. The converter comprises: a switch configured to switch the input DC voltage on and off during each cycle of a plurality of cycles; energy storage configured to temporarily store energy from the input source voltage when the switch is on, and release energy when the switch is off during each cycle, wherein the input energy stored is equal to the energy released with each cycle and achieves equilibrium when the converter is operating into normal loads; and a reset mechanism configured to provide additional reset voltage during each cycle to achieve equilibrium when the converter is operating in a fault condition. | 07-08-2010 |
20100164597 | Bootstrap Transistor Circuit - A switch circuit is described, where a switch to be controlled is formed of two NMOS transistors having their source terminals connected together and their gate terminals connected together. Their drain terminals are the input and output terminals of the switch. A driver circuit controls a bootstrap circuit that is formed of a latching circuit and a capacitor. When the switch is in an off state, the driver circuit connects the capacitor to a charging voltage source for charging the capacitor to a bootstrap voltage, and applies a non-zero voltage across the latching circuit. When the driver circuit is controlled to turn on the switch, the driver circuit disconnects the capacitor from the charging voltage source, and the latching circuit becomes conductive and effectively connects the capacitor across the gate and source terminals of the switch to turn it on with the bootstrap voltage. The bootstrap voltage across the capacitor maintains the latching circuit in a latched conductive state. | 07-01-2010 |
20100141178 | DIMMER CONTROL LEAKAGE PULL DOWN USING MAIN POWER DEVICE IN FLYBACK CONVERTER - A flyback controller-may include a dimmer input configured to receive a chopped and rectified AC voltage. Each cycle of the signal may have an off period which is substantially attenuated but not always zero due to leakage of a dimmer control from which the chopped AC voltage originates, and an on period which substantially tracks the AC voltage. The ratio of the off period to the on period may be dependent upon a setting of the dimmer control. The flyback controller may include a control circuit configured to generate a switching signal based on the signal from the dimmer input. The switching signal may controllably oscillate between its on and off states during the on periods of the chopped and rectified AC voltage so as to controllably regulate current that is delivered by a secondary winding of a transformer in a flyback converter. The switching signal may be in the on state during the off periods of the chopped and rectified AC voltage, thereby preventing a voltage build up from the dimmer control leakage. | 06-10-2010 |
20100141177 | DIMMER-CONTROLLED LEDS USING FLYBACK CONVERTER WITH HIGH POWER FACTOR - A flyback controller generates a switching signal for controlling delivery of current into a primary winding of a transformer in a flyback converter. The controller may include an output current monitoring circuit configured to generate a signal representative of an average output current in a secondary winding of the transformer based on a peak input current in the primary winding and a duty cycle of current in the secondary winding. The flyback controller may generate a switching signal that causes a chopped AC voltage from a dimmer control to be converted by the flyback converter into an average output current from a secondary winding of the transformer that is DC isolated from the chopped AC voltage and that varies as a function of the setting of the dimmer control. The flyback controller may not utilize a signal from an opto-isolator. | 06-10-2010 |
20100141174 | CURRENT RIPPLE REDUCTION CIRCUIT FOR LEDS - A powered LED circuit may include a power supply configured to generate and deliver an output current at a controllable average value with a substantial ripple component, one or more LEDs connected together, and a ripple reduction circuit connected to the power supply and to the one or more LEDs. The ripple reduction circuit may have a current regulator connected in series with the one or more LEDs which is configured to substantially reduce fluctuations in the current which flows through the one or more LEDs due to the ripple component of the output current, but not fluctuations in the current which flows through the one or more LEDs due to changes in the average value of the output current. | 06-10-2010 |
20100141173 | LINEARITY IN LED DIMMER CONTROL - A flyback controller may generate a switching signal for controlling the delivery of input current into a primary winding of a transformer in a flyback converter that has a secondary winding in the transformer and that is driven by AC output from a dimmer control that is chopped at a phase angle based on a setting of the dimmer control. The flyback controller may include a tracking input configured to receive a dimmer output tracking signal that is representative of the instantaneous magnitude of the output from the dimmer control. The flyback controller may include an averaging circuit configured to average the dimmer output tracking signal so as to generate an average dimmer output signal that is representative of a time-averaged value of the dimmer output tracking signal. The flyback controller may be configured to cause the average output current in the secondary winding of the transformer to vary as a function of the average dimmer output signal when the phase angle exceeds a threshold. The flyback controller may be configured to generate the switching signal with a duty cycle that causes the luminance level of light produced by one or more LEDs to vary when the phase angle exceeds a threshold by what appears to the human eye to be a more linear function of the phase angle than if the luminance level actually varied as a linear function of the phase angle. | 06-10-2010 |
20100127755 | POWER MEASUREMENT CIRCUIT - A power measurement circuit and method are described. The circuit comprises: a transconductance rectifier arrangement including an input and configured to receive a periodically varying input voltage signal having an approximate 50% duty cycle; and an averaging filter for producing a time averaged DC output signal proportional to the mean square of the voltage at the input of the transconductance rectifier arrangement and representative of the average power of the input voltage signal within a range of voltages at the input. | 05-27-2010 |
20100127754 | POWER MEASUREMENT CIRCUIT - A power measurement circuit comprises: a transconductance rectifier arrangement including an input and configured to receive a sinusoidal input voltage signal; and an averaging filter for producing a time averaged DC output signal proportional to the mean square of the voltage at the input of the transconductance rectifier arrangement and representative of the average power of the input voltage signal within a range of voltages at the input. | 05-27-2010 |
20100123444 | ACCELERATED RESPONSE TO LOAD TRANSIENTS IN PFM DC-TO-DC CONVERTERS - A pulse generator circuit in a DC-to-DC converter may be configured to generate pulses that have a frequency that increases in response to increases in the load on the DC-to-DC converter. The pulse generator circuit may be configured to cause each pulse to have a constant width. When the pulse reaches the end of the constant width and the magnitude of the current through an inductance in the converter is less than a threshold value, however, the pulse generator may be configured to extend the pulse until the magnitude of the current through the inductance reaches the threshold value. The pulse generator circuit may be configured to prematurely terminate each pulse if and at such time as the load voltage exceeds a target value by approximately half of the peak-to-peak voltage of the ripple component plus the noise component margin. | 05-20-2010 |
20090322575 | SINGLE PASS INL TRIM ALGORITHM FOR NETWORKS - A single-pass method of trimming a network, and a network manufactured according to the method, uses the assumption that the peak INL value is minimized by trimming all the structures in the network to a same target value based upon the boundary conditions of the discretely adjustable elements that make up the structures. Using this assumption, the number of targets that need to be simulated, can be greatly reduced making estimation of peak INL possible in a reasonable amount of testing or manufacturing time. The trim algorithm produces results that are optimum or substantially close to optimum and is guaranteed not to deteriorate the Peak INL compared to the untrimmed Peak INL. An auto-calibration system using the trim method is also provided so that the method can be used in a product in real time if desired. | 12-31-2009 |
20090121770 | METHOD FOR CLAMPING A SEMICONDUCTOR REGION AT OR NEAR GROUND - A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio. | 05-14-2009 |
20090058380 | MULTIPLE OUTPUT AMPLIFIERS AND COMPARATORS - An amplifier/comparator includes a multitude of output stages all sharing the same input stage. One or more of the output stages are amplification stages and have compensated output signals. A number of other output stages are not compensated and provide comparison signals. Each uncompensated output stage is adapted to switch to a first state if it detects a first input signal as being greater than a second signal, and further to switch to a second state if it detects the first input signal as being smaller than the second signal. By varying the channel-width (W) to channel-length (L) ratio (W/L) of the transistors disposed in the output stages, the trip points of the comparators and/or the electrical characteristics of the amplifiers are selectively varied. | 03-05-2009 |