VANGUARD INTERNATIONAL SEMICONDUCTOR Patent applications |
Patent application number | Title | Published |
20120025308 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE, METHOD FOR FABRICATING BIPOLAR-CMOS-DMOS - A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions. | 02-02-2012 |
20100207207 | SEMICONDUCTOR STRUCTURE - The invention provides a semiconductor structure. A first type body doped region is deposited on a first type substrate. A first type heavily-doped region having a finger portion with an enlarged end region is deposited on the first type body doped region. A second type well region is deposited on the first type substrate. A second type heavily-doped region is deposited on the second type well region. An isolation structure is deposited between the first type heavily-doped region and the second type heavily-doped region. A gate structure is deposited on the first type substrate between the first type heavily-doped region and the isolation structure. | 08-19-2010 |
20100148253 | HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH SCHOTTKY DIODES - High voltage semiconductor devices with Schottky diodes are presented. A high voltage semiconductor device includes an LDMOS device and a Schottky diode device. The LDMOS device includes a semiconductor substrate, a P-body region in a first region of the substrate, and an N-drift region in the second region of the substrate with a junction therebetween. A patterned isolation region defines an active region. An anode electrode is disposed on the P-body region. An N | 06-17-2010 |
20090236665 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode. | 09-24-2009 |
20090140370 | SEMICONDUCTOR DEVICE - A semiconductor device is described. The semiconductor device comprises a protected device in a protected device area of a substrate. An electrostatic discharge power clamp device comprising an outer first guard ring and an inner second guard ring is in a guard ring area of the substrate, enclosing the protected device. The first guard ring comprises a first well region having a first conductive type. A first doped region having the first conductive type and a second doped region having a second conductive type are in the first well region. The second guard ring comprises a second well region having a second conductive type. A third doped region has the second conductive type in the second well region. An input/output device is in a periphery device area, coupled to the electrostatic discharge power clamp device. | 06-04-2009 |
20090053891 | Method for fabricating a semiconductor device - A method for fabricating a semiconductor device for preventing a poisoned via is provided. A substrate with a conductive layer formed thereon is provided. A composite layer is formed over the substrate and the conductive layer, wherein the composite layer comprises a dielectric layer and a spin-on-glass layer. A via hole is formed through the composite layer, wherein the via hole exposes a surface of the conductive layer. A protection layer is formed on a sidewall of the via hole so as to prevent out-gassing from the spin-on-glass layer. A barrier layer is formed on the protection layer and the conductive layer within the via hole. And a metal layer is deposited on the barrier layer within the via hole to fill the via hole. | 02-26-2009 |