SKYMEDI CORPORATION Patent applications |
Patent application number | Title | Published |
20150349805 | Method of Handling Error Correcting Code in Non-volatile Memory and Non-volatile Storage Device Using the Same - A method of handling an error correcting code (ECC) in a non-volatile memory includes performing a first ECC operation on data codes to generate first parity codes; compressing the first parity codes to generate compressed parity codes; performing a second ECC operation on the compressed parity codes to generate additional parity codes; and writing the data codes, the compressed parity codes and the additional parity codes into a memory unit of the non-volatile memory. | 12-03-2015 |
20150120988 | Method of Accessing Data in Multi-Layer Cell Memory and Multi-Layer Cell Storage Device Using the Same - A method of accessing data in a multi-layer cell (MLC) memory includes using single-layer cell (SLC) configuration to transfer a portion of a plurality of memory units in the MLC memory to an SLC area to form a plurality of MLC memory units and a plurality of SLC memory units; storing data in the plurality of SLC memory units when the data is assigned to be stored in an MLC memory unit; mapping the MLC memory unit to the SLC memory units; reading the data by obtaining the data in the SLC memory units corresponding to the MLC memory unit; and reallocating the SLC memory units to use MLC configuration when an update of data is involved in the MLC memory unit or a new data is assigned to be stored in at least one of the SLC memory units. | 04-30-2015 |
20150103593 | Method of Writing Data in Non-Volatile Memory and Non-Volatile Storage Device Using the Same - A method of writing data in a non-volatile memory includes writing data from a first memory unit to a second memory unit of the non-volatile memory; checking a health of the second memory unit to generate a health result; and reserving the data in the first memory unit and mapping information corresponding to the first memory unit when the health result indicates that the second memory unit is unhealthy. | 04-16-2015 |
20140344502 | Method of Accessing On-Chip Read Only Memory and Computer System Thereof - A method of accessing an on-chip read only memory (ROM) includes dividing a frequency of a system clock by a specific divisor, in order to generate a ROM clock; combining a specific number of adjacent addresses into a combined address, wherein the specific number is determined according to the specific divisor; inserting a first stall signal into a real output data, wherein a length of the first stall signal is determined in order to meet a timing requirement for accessing the on-chip ROM; generating an output data of the on-chip ROM according to the combined address, wherein a width of the output data is extended by a specific multiple which is determined according to the specific number; and generating a first delay corresponding to the length of the first stall signal in the address. | 11-20-2014 |
20140331024 | Method of Dynamically Adjusting Mapping Manner in Non-Volatile Memory and Non-Volatile Storage Device Using the Same - A method of dynamically adjusting a mapping manner for a non-volatile memory includes mapping a plurality of logical addresses to a plurality of physical addresses by a first mapping unit; storing data in the non-volatile memory by the first mapping unit; and mapping at least one logical address to at least one physical address by a second mapping unit according to the stored data. | 11-06-2014 |
20140328127 | Method of Managing Non-Volatile Memory and Non-Volatile Storage Device Using the Same - A method of managing a non-volatile memory where the non-volatile memory comprises a plurality of memory blocks and each of the plurality of memory blocks includes a plurality of memory pages includes partitioning a memory page among the plurality of memory pages into a plurality of clusters; and writing data and a mapping information corresponding to the data into different clusters of the plurality of clusters. | 11-06-2014 |
20140325294 | SYSTEM AND METHOD OF ENHANCING DATA RELIABILITY - In a system and method of enhancing data reliability, a reference value associated with error count is obtained, and an error count of data stored in a buffer is obtained whenever an event is triggered. An accumulated value associated with error counts is acquired when the recorded error count is greater than an error threshold value. System slowdown is performed when the accumulated value is greater than a predetermined value. | 10-30-2014 |
20140297921 | Method of Partitioning Physical Block and Memory System Thereof - A method of partitioning a physical block in a memory includes: determining a sub-block size according to a data length of a sequential write and a block size; partitioning the physical block into sub-blocks, each having a size equal to the sub-block size; and mapping logical blocks to the sub-blocks. | 10-02-2014 |
20140237143 | Debugging Fixture - A fixture, for connecting a host device and a universal serial bus (USB) device, the fixture comprises a plurality of connectors; a plurality of first signal pins, located at first ends of the plurality of connectors for connecting to the host device; and a plurality of second signal pins, located at second ends of the plurality of connectors for connecting to the USB device; wherein a first part of the plurality of connectors are used for transmitting signals between the host device and the USB device in a USB mode; wherein a second part of the plurality of connectors are retained in a specified state for providing a control signal to control the USB device to enter an operating mode. | 08-21-2014 |
20140207998 | SYSTEM AND METHOD OF WEAR LEVELING FOR A NON-VOLATILE MEMORY - In an architecture of wear leveling for a non-volatile memory composed of plural storage units, a translation layer is configured to translate a logical address provided by a host to a physical address of the non-volatile memory. A cold-block table is configured to assign a cold block or blocks in at least one storage unit, the cold block in a given storage unit having an erase count being less than erase counts of non-cold blocks in the given storage unit. The logical addresses and the associated physical addresses of the cold blocks are recorded in the cold-block table, thereby building a cold-block pool composed of the cold blocks. | 07-24-2014 |
20140201253 | Delay Device, Method, and Random Number Generator Using the Same - A delay device for generating a signal for a random component in a random number generator is disclosed. The delay device includes a delay module, for generating a plurality of delayed signals, wherein each delayed signal has a delay time and the delay time is different from each other; a first multiplexer, coupled to the delay module, for outputting a delayed signal among the plurality of delayed signals as a delayed trigger signal to control the random component to generate a random bit; and a delay selector, coupled to the first multiplexer, for generating a selecting signal to control the first multiplexer to select to output the delayed signal as the delayed trigger signal. | 07-17-2014 |
20140198460 | Micro Secure Digital Adapter - A micro secure digital (SD) adapter, for adapting a micro SD card to an SD interface, the micro SD adapter comprising a micro SD slot, for disposing the micro SD card; a pin module, comprising a plurality of signal pins, a first ground pin, and a second ground pin; a plurality of connectors, for conducting the plurality of signal pins and the first ground pin to the micro SD card according to a pin configuration of the micro SD card when the micro SD card is disposed in the micro SD slot; and a conducting module, electrically connected between a terminal of a first connector corresponding to the first ground pin and the second ground pin. | 07-17-2014 |
20140195701 | TIME-SHARING BUFFER ACCESS SYSTEM - A time-sharing buffer access system manages a buffer among plural master devices. Plural buffer handling units are operable to associatively couple the master devices, respectively, and a first end of each buffer handling unit is used to independently transfer data to or from the associated master device. A second end of each buffer handling unit is coupled to a buffer switch. A time slot controller defines a time slot, during which one of the buffer handling units is selected by the buffer switch such that data are only transferred between the selected buffer handling unit and the buffer. | 07-10-2014 |
20140181621 | METHOD OF ARRANGING DATA IN A NON-VOLATILE MEMORY AND A MEMORY CONTROL SYSTEM THEREOF - A method of arranging data in a non-volatile memory and an associated memory control system are disclosed. A data area is divided into a plurality of valid data divisions, each having a link header followed by associated data and error correction code (ECC). At least one linking parameter is set in each said link header, and at least one obsolete data division including a bad column or columns is set, each said obsolete data division being flexible in size. Valid data divisions are linked and the obsolete data divisions are skipped, when accessing the non-volatile memory, according to the at least one linking parameter. | 06-26-2014 |
20140163716 | BRIDGE DEVICE, AUTOMATED PRODUCTION SYSTEM AND METHOD THEREOF FOR STORAGE DEVICE - A bridge device for manufacturing a storage device, including a first transmission interface, a second transmission interface, a mode select unit, a power control unit, and a bridge controller is provided. The mode select unit generates a mode select signal responsive to a manufacturing process command. The power control unit controls powering operation of the storage device. The bridge controller receives the manufacturing process command through the first transmission interface. When the bridge controller detects the presence of the storage device, drives the power control unit turning off the storage device. After a first predetermined period, the bridge controller drives the mode select unit transmitting the mode select signal to the storage device through unused pin of the second transmission interface. The bridge controller drives the power control unit turning on the storage device after a second predetermined period to have the storage device entering a predefined mode. | 06-12-2014 |
20140137128 | Method of Scheduling Tasks for Memories and Memory System Thereof - A method of scheduling a plurality of tasks for a plurality of memories in a memory system is disclosed. The method includes classifying each task among the plurality of tasks to a task type among a plurality of task types, disposing a plurality of task queues according to the plurality of task types wherein each task queue stores tasks to be executed within the plurality of tasks, assigning a priority for each task type among the plurality of task types, disposing at least one execution queue; and converting a first task stored in a first task queue among the plurality of task queues into at least one command to be stored in a first execution queue among the at least one execution queue, wherein the at least one command is executed according to the priority of a first task type corresponding to the first task queue. | 05-15-2014 |
20140089564 | METHOD OF DATA COLLECTION IN A NON-VOLATILE MEMORY - A method of data collection is performed in a non-volatile memory that has a number of blocks and each block has multiple pages. A timestamp is recorded associated with a data written to the non-volatile memory. Some of the written data are moved from a plurality of different pages respectively to a first block according to the timestamps associated with the plurality of written data stored in the plurality of different pages. | 03-27-2014 |
20140055940 | MEMORY DEVICE - A memory device includes a control board and a conductive housing. In one embodiment, a circuit ground in the control board is electrically coupled to the conductive housing to make a common ground contact. In another embodiment, differential impedances at different locations of a conductor are controllably maintained within a specified range by adjusting width of the conductor and/or spacing between the adjacent conductors of a differential pair. | 02-27-2014 |
20140032813 | METHOD OF ACCESSING A NON-VOLATILE MEMORY - A method of accessing a non-volatile memory is disclosed. Original bits of data are duplicated on a bit level to generate a plurality of duplicated bits corresponding to each original bit. At least one shielding bit is provided between the duplicated bits corresponding to different original bits. The duplicated bits and the at least one shielding bit are programmed to the non-volatile memory. The original bits are generated or determined according to the duplicated bits. | 01-30-2014 |
20130332644 | METHOD OF INITIALIZING A NON-VOLATILE MEMORY SYSTEM - A method of initializing a non-volatile memory system is disclosed. System data are written to a non-volatile memory based on a formula rule at a factory, and a number of copies of the system data are written to the non-volatile memory. The system data are searched in the non-volatile memory according to the formula rule and a selected data access mode. At least one operating parameter of the selected data access mode is reconfigured, followed by checking if the searched system data are successfully read. The system data are utilized to set the at least one operating parameter of the non-volatile memory system when the searched system data are successfully read from the non-volatile memory. | 12-12-2013 |
20130295996 | OPERATING METHOD, APPARATUS, AND MEMORY MODULE INTEGRATED WITH WIRELESS COMMUNICATION COMPONENT - Disclosed herein is related to an operating method, and a memory module with wireless communication component. An exemplary example of the invention describes the memory module providing a control unit which coupled to both a wireless communication component such as an NFC chip, and anon-volatile memory unit. The memory module exemplarily uses an eMMC bus to interconnect a cellular phone system and the control unit. It is advantaged that when any data required to be transmitted between the NFC chip and the cellular phone system, a partition is specified to the chip according a partition table for further access task. | 11-07-2013 |
20130250682 | METHOD OF PROGRAMMING A MULTI-BIT PER CELL NON-VOLATILE MEMORY - A method of programming a multi-bit per cell non-volatile memory is disclosed. In one embodiment, the non-volatile memory is read to obtain a first data of a most-significant-bit (MSB) page on a current word line that succeeds in data reading, wherein the current word line follows a preceding word line on which data reading fails. At least one reference voltage is set. The MSB page on the current word line is secondly programmed with a second data according to the reference voltage, the second data being different from the first data. | 09-26-2013 |
20130241505 | VOLTAGE REGULATOR WITH ADAPTIVE MILLER COMPENSATION - A voltage regulator with adaptive Miller compensation includes a first amplifier and a second amplifier. An adaptive compensation circuit includes serially connected compensation capacitor and a compensation transistor coupled to the second amplifier. A bias circuit generates a proper bias control voltage to dynamically control the adaptive compensation circuit in a manner that the adaptive compensation transistor operates in a deep triode region with weakly-inverted channel or strongly-inverted channel. An output circuit generates an output voltage according to which the feedback voltage is generated. The resistance of the compensation transistor varies according to a load of the voltage regulator under control of the bias control voltage. The bias circuit generates a mirror current that copies at least a portion of a current flowing in the output circuit, and the bias control voltage is then generated according to the mirror current. | 09-19-2013 |
20130211568 | AUTOMATAED MASS PRODCUTION METHOD AND SYSTEM THEREOF - An exemplary embodiment of the present disclosure illustrates an automated mass production method, adapted for an automated mass production system in manufacturing at least an electronic device having a storage unit, the method includes steps of: determining a protocol type of the Auto Handler to select one of the agents; establishing a first communication protocol communication between the MP tool module and the selected agent; establishing a second communication protocol communication between the selected agent and the Auto Handler; the Auto Handler outputting a processing command to the selected agent; the selected agent converting the processing command into a MP tool module executable MP tool instruction; and the selected agent outputting the corresponding MP tool instruction to the MP tool module so as to have the MP tool module executed the MP tool instruction to automatically perform a corresponding mass production process to the electronic device. | 08-15-2013 |
20130185491 | MEMORY CONTROLLER AND A METHOD THEREOF - A memory controller includes a mixed buffer and an arbiter. The mixed buffer includes at least one single-port buffer and at least one multi-port buffer for managing data flow between a host and a storage device. The arbiter determines an order of access to the mixed buffer among a plurality of masters. The data to be written or read are partitioned into at least two parts, which are then moved to the single-port buffer and the multi-port buffer, respectively. | 07-18-2013 |
20130179749 | METHOD AND SYSTEM OF DYNAMIC DATA STORAGE FOR ERROR CORRECTION IN A MEMORY DEVICE - A method of dynamic data storage for error correction in a memory device is disclosed. Data for storage is received, the received data is encoded and error correction code (ECC) is generated. The encoded data is stored in the memory device that includes a plurality of pages each having a plurality of data partitions. More corrected errors a marked page has, a smaller portion with a space of at least one datum of each of the corresponding data partitions associated with the marked page is allocated to store the encoded data, while a size of the ECC is fixed, thereby increasing capability of correcting errors in the marked page. | 07-11-2013 |
20130169246 | LINEAR VOLTAGE REGULATING CIRCUIT ADAPTABLE TO A LOGIC SYSTEM - A linear voltage regulating circuit adaptable to a logic system is disclosed. A first linear voltage regulator receives an input voltage and a first reference voltage. A second linear voltage regulator has a load driving capability lower than the first linear voltage regulator, and the second linear voltage regulator receives the input voltage and a second reference voltage. An output node of the first linear voltage regulator and an output node of the second linear voltage regulator are directly connected at a single common output node. A single common capacitor is connected between the common output node and a ground. | 07-04-2013 |
20130151752 | BIT-LEVEL MEMORY CONTROLLER AND A METHOD THEREOF - The present invention is directed to a bit-level memory controller and method adaptable to managing defect bits of a non-volatile memory. A bad column management (BCM) unit retrieves a bit-level mapping table, in which defect bits are respectively marked, based on which the BCM unit constructs a bit-level script (BLS) that contains a plurality of entries denoting defect-bit groups respectively. An internal buffer is configured to store data managed by the BCM unit according to the BLS. | 06-13-2013 |
20130044542 | METHOD OF SORTING A MULTI-BIT PER CELL NON-VOLATILE MEMORY AND A MULTI-MODE CONFIGURATION METHOD - A method of sorting a multi-bit per cell non-volatile memory includes programming and reading to test an n-bit-per-cell (n-bpc) non-volatile memory, which has a plurality of m-bpc pages, where m is a positive integer from 1 through n. If the m-bpc page fails the test, counting a block associated with the failed m-bpc page to (m-1)-bpc blocks, wherein each said m-bpc page is subjected to at most one time of programming and reading. When m is equal to 1, the 0-bpc block corresponds to a bad block. | 02-21-2013 |
20130042051 | PROGRAM METHOD FOR A NON-VOLATILE MEMORY - A program method for a non-volatile memory is disclosed. At least two blocks in the non-volatile memory are configured as 1-bit per cell (1-bpc) blocks. The data of the configured blocks are read and written to a target block in such a way that the data of each said configured block are moved to pages of a same significant bit. In another embodiment, the data of the configured blocks excluding one block are read and written to the excluded block. | 02-14-2013 |
20130019046 | DATA TRANSMITTING DEVICE AND SYSTEM FOR PORTABLE DEVICE AND METHOD THEREOFAANM SHIEH; Yeong-RueyAACI Hsinchu CityAACO TWAAGP SHIEH; Yeong-Ruey Hsinchu City TWAANM Cho; Shih-KengAACI Hsinchu CityAACO TWAAGP Cho; Shih-Keng Hsinchu City TWAANM Liu; Hsu-PinAACI Hsinchu CityAACO TWAAGP Liu; Hsu-Pin Hsinchu City TWAANM Hsu; Wei-ShuAACI Hsinchu CityAACO TWAAGP Hsu; Wei-Shu Hsinchu City TWAANM Lin; Chi-HanAACI Hsinchu CityAACO TWAAGP Lin; Chi-Han Hsinchu City TWAANM Wang; Yu-ShiangAACI Hsinchu CityAACO TWAAGP Wang; Yu-Shiang Hsinchu City TW - A data transmitting method for communicating one of a plurality of portable devices with a host computer via a data transmitting device having a plurality of USB connector is disclosed. In one embodiment of the present invention, the method includes the following steps: firstly, a switch circuit is configured in one of the portable devices. Then, the portable device having the switch circuit is coupled with the data transmitting device. Afterward, a data transmission path between the host computer and the portable device having the switch circuit is connected by the switch circuit to transmit data between the portable device having the switch circuit and the host computer, or the data transmission path between the USB connector, which is not connecting with the portable device having the switch circuit, and the host computer is connected by the switch circuit. | 01-17-2013 |
20120243310 | METHOD OF PROGRAMMING A MULTI-BIT PER CELL NON-VOLATILE MEMORY - A method of programming a multi-bit per cell non-volatile memory is disclosed. In one embodiment, the non-volatile memory is read to obtain a first data of a most-significant-bit (MSB) page on a current word line that succeeds in data reading, wherein the current word line follows a preceding word line on which data reading fails. At least one reference voltage is set. The MSB page on the current word line is secondly programmed with a second data according to the reference voltage, the second data being different from the first data. | 09-27-2012 |
20120233401 | EMBEDDED MEMORY SYSTEM - An embedded memory system is disclosed. A main interface is configured to communicate with an electronic system via a main bus. A memory-sharing auxiliary interface is configured to communicate with the electronic system via a memory-sharing auxiliary bus. An arbiter is configured to arbitrate among the main interface, the memory-sharing auxiliary interface, a primary memory, and a secondary memory. Accordingly, the electronic system is capable of sharing either the primary memory or the secondary memory via the memory-sharing auxiliary interface and the memory-sharing auxiliary bus, and the embedded memory system is capable of sharing a system memory of the electronic system via the memory-sharing auxiliary interface and the memory-sharing auxiliary bus. | 09-13-2012 |
20120233394 | MEMORY CONTROLLER AND A CONTROLLING METHOD ADAPTABLE TO DRAM - A memory controller and controlling method adaptable to a dynamic random access memory (DRAM) are disclosed. A DRAM controller is configured to manage flow of data to and from the DRAM. A write buffer is controlled by the DRAM controller to temporarily store an entry of data to be written to the DRAM. The data to be written is stored in the write buffer if the write buffer is empty, and the stored data and a succeeding data to be written are both written to the DRAM. | 09-13-2012 |
20120210038 | EXTERNAL BRIDGE SYSTEM - An external bridge system includes a host interface, a first device interface and a second device interface, which uses a communication protocol different from that of the first device interface. A bridge controller translates signals compliant with the communication protocol of a host to or from signals compliant with the communication protocol of the first or second device. | 08-16-2012 |
20120096280 | SECURED STORAGE DEVICE WITH TWO-STAGE SYMMETRIC-KEY ALGORITHM - A secured storage device uses a user key set by user to encrypt a primary key that is for encryption or decryption of user data, to produce a first encrypted data. In the secured storage device, neither the primary key nor the user key is stored, but the first encrypted data, and a secondary key and a second encrypted data produced from the secondary key encrypted with the user key for verifying the password inputted by user are stored. Therefore, even though a storage medium in the secured storage device is detached and read, the primary key and the user key cannot be obtained by a third party for reading out any encrypted user data from the secured storage device. | 04-19-2012 |
20120079289 | SECURE ERASE SYSTEM FOR A SOLID STATE NON-VOLATILE MEMORY DEVICE - A secure erase system for a solid state memory device is disclosed. A memory area provides a data block for storing data and a key block for storing at least one key. A translation unit maps a logical address to a physical address associated with the memory area. An encryption unit encrypts plaintext data to be written to the memory area with the associated key and decrypts the encrypted data to be read by a host with the associated key. The key associated with a logical erase group to be secure erased is deleted after receiving a command requesting to erase the data associated with the logical erase group. | 03-29-2012 |
20120008387 | METHOD OF TWICE PROGRAMMING A NON-VOLATILE FLASH MEMORY WITH A SEQUENCE - A method of twice programming a multi-bit per cell non-volatile memory with a sequence is disclosed. At least one page at a given word line is firstly programmed with program data by a controller of the non-volatile memory, and at least one page at a word line preceding the given word line is secondly programmed with the same program data by the controller. | 01-12-2012 |
20110283164 | CONFIGURABLE CODING SYSTEM AND METHOD OF MULTIPLE ECCS - A configurable coding system and method of multiple error correcting codes (ECCs) for a memory device or devices are disclosed. The system includes an ECC codec that selectively performs different error corrections with different parameters. The system also includes means for providing a selected parameter to the ECC codec for initializing the ECC codec. The parameter used for initializing the ECC codec is an error-free parameter. | 11-17-2011 |
20110246855 | Method and Apparatus of Generating a Soft Value for a Memory Device - A method and apparatus of generating the soft value for a memory device is disclosed. Memory read-related parameters are set, and data are read out of the memory device according to the set parameters. The data reading is performed for pre-determined plural iterations, thereby obtaining the soft value according to the read-out data and the set parameters. | 10-06-2011 |
20110131459 | Memory Device with Protection Capability and Method of Accessing Data Therein - The present invention is directed to a memory device with protection capability and a method of accessing data therein. A spreader encrypts input user data according to an entered password, and the encrypted data is then stored in a storage area. A despreader performs reverse process of the spreader on the stored data according to the entered password. | 06-02-2011 |
20110072191 | Uniform Coding System for a Flash Memory - A uniform coding system for a flash memory is disclosed. A statistic decision unit determines a coding word according to a plurality of inputs. An inverse unit controllably inverts input data to be encoded. The input data are then encoded into encoded data according to a statistic determined by the statistic decision unit. | 03-24-2011 |
20110055659 | Method and System of Dynamic Data Storage for Error Correction in a Memory Device - A method of dynamic data storage for error correction in a memory device is disclosed. Data for storage is received, and the received data is then encoded and associated error correction code (ECC) is generated. The encoded data is stored in a portion of a data partition of the memory device, wherein percentage of the stored data in the data partition is determined according to an amount of corrected errors associated with the data partition or is predetermined. | 03-03-2011 |
20110041040 | Error Correction Method for a Memory Device - An error correction method for a memory device is disclosed. A base reading of a memory device is performed, and an error correction code (ECC) decoding is performed on the data read out of the memory device. The memory device is further read when the result of the ECC decoding is not strongly determined, wherein extra information acquired in the further reading of the memory device is used in the ECC decoding. | 02-17-2011 |
20110038209 | Method and System for Adaptively Finding Reference Voltages for Reading Data from a MLC Flash Memory - A method and system for adaptively finding reference voltages for reading data from a multi-level cell (MLC) flash memory is disclosed. According to one embodiment, a first total number of cells of the flash memory above a first threshold voltage in a shifted threshold voltage distribution is provided. Search to find a second threshold voltage such that a second total number of the cells above the second threshold voltage is approximate to the first total number. An initial reference voltage or voltages of the initial threshold voltage distribution are shifted with an amount approximate to a voltage difference between the second threshold voltage and the first threshold voltage, thereby resulting in a new reference voltage or voltages for reading the data from the MLC flash memory. | 02-17-2011 |
20110038205 | Method Of Reducing Bit Error Rate For A Flash Memory - A method of reducing coupling effect in a flash memory is disclosed. A neighboring page is read, and a flag is set active if the neighboring page is an interfering page. Data are read from the neighboring page at least two more times using at least two distinct read voltages respectively. The threshold-voltage distributions associated with an original page and the neighboring page are transferred according to the read data and the flag. | 02-17-2011 |
20100321997 | Method And System For Obtaining A Reference Block For A MLC Flash Memory - A method and system for obtaining a reference block on which reference voltages may be found for a MLC flash memory are disclosed. A first block and a second block are provided in the flash memory. A memory controller alternatively controls one of the first and the second blocks to act as the reference block and the other one as a cycle block in a respective period, during which the reference block stays idle and the cycle block is subjected to program/erase cycles. | 12-23-2010 |
20100115213 | MEMORY APPARATUS AND MEMORY MANAGEMENT METHOD OF THE SAME - A method of memory management for an apparatus having a non-volatile memory and a volatile memory includes the steps of forming a tree structure of entries in the volatile memory, in which the tree structure has a left branch and a right branch, and a difference of heights of the left branch and the right branch is equal to or less than one; and accessing an entry in the volatile memory through the tree structure. | 05-06-2010 |
20100088458 | OPERATION METHOD OF MEMORY - An operation method of a memory includes the steps of calculating an offset of sequential write commands and the beginning of pages of a block of a non-volatile memory; shifting the block by the offset; and directly writing data from a host to the pages except the first and last pages of the block by the sequential write commands. In an embodiment, the pages are logical pages providing optimal writing efficiency and are determined before calculating the offset. The step of shifting the block by the offset is to increase corresponding logical block addresses (LBA) in the pages by the offset. | 04-08-2010 |
20100030933 | NON-VOLATILE MEMORY STORAGE DEVICE AND OPERATION METHOD THEREOF - A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged. | 02-04-2010 |
20090287893 | METHOD FOR MANAGING MEMORY - A method is employed to manage a memory, e.g., a flash memory, including a plurality of paired pages. Each paired page includes a page and a respective risk zone. For each write command, at least one unwritten page is selected for writing new data. For each unwritten page whose risk zone includes at least one written page, each written page is copied or backed up, and the new data is written to the unwritten page. For each unwritten page whose risk zone lacks a written page, the new data is written to the unwritten page. In an embodiment, the written page is copied only if the unwritten page and the written page are operated by different write commands. | 11-19-2009 |
20090259819 | METHOD OF WEAR LEVELING FOR NON-VOLATILE MEMORY - A method of wear leveling for a non-volatile memory is performed as follows. First, the non-volatile memory is divided into a plurality of zones including at least a first zone and a second zone. The first zone is written and/or erased in which one or more logical blocks have higher writing hit rate, and therefore the corresponding physical blocks in the first zone will be written more often. The next step is to find one or more free physical blocks in second zone. The physical blocks of the first zone are replaced by the physical blocks of the second zone if the number of write and/or erase to the first zone exceeds a threshold number. The replacement of physical blocks in the first zone by the physical blocks in the second zone may include the steps of copying data from the physical blocks in the first zone to the physical block in the second zone, and changing the pointer of logical blocks to point to the physical blocks in the second zone. | 10-15-2009 |
20090254729 | METHOD OF WEAR LEVELING FOR A NON-VOLATILE MEMORY - According to the method of wear leveling for a non-volatile memory of the present invention, the non-volatile memory is divided into a plurality of windows, and a mapping table is built in which the logical block addresses having frequently accessed data are allocated equally to the plurality of windows. The logical block addresses may store a File Allocation Table (FAT) or a directory table; therefore the windows they locate will be written or erased more frequently. In an embodiment, the logical block addresses having frequently accessed data are allocated on a one-to-one basis to the plurality of windows. For example, the plurality of windows may comprise Windows | 10-08-2009 |
20090249140 | METHOD FOR MANAGING DEFECT BLOCKS IN NON-VOLATILE MEMORY - A method for managing defect blocks in a non-volatile memory essentially comprises the steps of detecting defect blocks in the non-volatile memory, storing addresses of the defect blocks in a table block of the non-volatile memory, and setting the non-volatile memory to be read-only if the quantity of defect blocks in the non-volatile memory exceeds a threshold and no free blocks remain in the non-volatile memory. In a preferred embodiment, the free pages in the defect block continue to be programmed before setting the non-volatile memory to be read-only. | 10-01-2009 |
20090198944 | SEMICONDUCTOR MEMORY DEVICE - An adaptive semiconductor memory device is used for being inserted into a host for storage. The semiconductor memory device comprises a non-volatile memory and a switch. The switch can be a logical switch or a physical switch that controls the semiconductor memory device to be in compliance with either a first specification version or a second specification version of the semiconductor memory device. The second specification version in comparison with the first specification version is used for higher capacity applications. | 08-06-2009 |
20090198919 | A Non-Volatile Memory Device, and Method of Accessing a Non-Volatile Memory Device - A non-volatile memory device, and a method for accessing the non-volatile memory device are provided. The non-volatile memory device is connected to a host via a bus. The non-volatile memory device comprises an MCU. By independently processing the particular commands using only the auxiliary circuit, the MCU can cease to operate, thus saving power. By setting the bus into power saving mode when the non-volatile memory device is busy, the host and the non-volatile memory device would not communicate mutually, thus, saving power. | 08-06-2009 |
20090198882 | METHOD OF WEAR LEVELING FOR NON-VOLATILE MEMORY AND APPARATUS USING THE SAME - A method of wear leveling for a non-volatile memory is disclosed. A non-volatile memory is divided into windows and gaps, with each gap between two adjacent windows. The windows comprise physical blocks mapped to logical addresses, and the gaps comprise physical blocks not mapped to logical addresses. The windows are shifted through the non-volatile memory in which the mapping to the physical blocks in the window to be shifted is changed to the physical blocks in the gap. | 08-06-2009 |
20090043945 | Non-Volatile Memory System and Method for Reading Data Therefrom - A non-volatile memory system and a method for reading data therefrom are provided. The data comprises a first sub-data and a second sub-data. The non-volatile memory system comprises a first storage unit and a second storage unit, adapted for storing the two sub-data respectively. The first storage unit reads a first command from the controller, and stores the first sub-data temporarily as the first temporary sub-data according to the first command. The second storage unit reads a second command from the controller, and stores the second sub-data temporarily as the second temporary sub-data according to the second command. The first temporary sub-data is read from the first storage unit. Then, the first storage unit reads a third command from the controller. The second temporary sub-data is also read from the second storage unit while reading the third command. The time for reading data from the non-volatile memory system is reduced. | 02-12-2009 |