Semiconductor Manufacturing International Corporation Patent applications |
Patent application number | Title | Published |
20140117218 | METHOD AND APPARATUS FOR MONITORING ELECTRON BEAM CONDITION OF SCANNING ELECTRON MICROSCOPE - A method and an apparatus for monitoring an electron beam condition of an SEM are provided. The SEM includes an electron gun and an electromagnetic lens system. The method includes acquiring quality parameters of an input electron beam, wherein the input electron beam is provided by the electron gun to the electromagnetic lens system, acquiring a current set of operation parameters of the electromagnetic lens system, calculating quality parameters of an output electron beam of the electromagnetic lens system, based on the quality parameters of the input electron beam and one or more operation parameters of the current set of operation parameters, and determining, based on the quality parameters of the output electron beam, whether calibration of the SEM is required. | 05-01-2014 |
20130171742 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a miniaturized semiconductor device so as to form MTJ elements therein include the steps of depositing a magnetic tunnel junction (MTJ) precursor layer on a substrate and planarizing the precursor layer; forming a sacrificial and patternable dielectric layer on the MTJ precursor layer; patterning the sacrificial dielectric layer in accordance with predetermined placements and shapes of a to-be-formed hard mask, the patterning forming corresponding openings in the sacrificial dielectric layer; depositing an etch-resistant conductive material such as Cu in the openings for example by way of plating, and selectively removing the sacrificial dielectric layer so as to leave behind the etch-resistant conductive material in the form of a desired hard mask. Using the hard mask to etch and thus pattern the MTJ precursor layer so as to form MTJ elements having desired locations, sizes and shapes. | 07-04-2013 |
20130168872 | VIA ARRANGEMENT AND SEMICONDUCTOR DEVICE WITH THE VIA ARRANGEMENT - A semiconductor device may include a first line of vias including a first via and a second via immediately adjacent to the first via. The semiconductor device may further include a second line of vias arranged immediately adjacent to and parallel to the first line of vias, the second line of vias including a third via immediately adjacent to the first via and the second via, the second line of vias further including a fourth via immediately adjacent to the third via, the first via, and the second via. The shortest distance between the second via and the fourth via may be greater than the shortest distance between the first via and the second via. | 07-04-2013 |
20130168747 | Semiconductor Device and Method for Manufacturing A Semiconductor Device - The present invention discloses a method for manufacturing a semiconductor device. According to the method provided by the present disclosure, a dummy gate is formed on a substrate, removing the dummy gate to form an opening having side walls and a bottom gate, a dielectric material is formed on at least a portion of the sidewalls of the opening and the bottom surface of the opening, and a pre-treatment is performed to a portion of the dielectric material layer on the sidewalls of the opening, and thus the properties of the dielectric material is changed, and then the pre-treated dielectric material on the sidewalls of the opening is removed by a selective process. The semiconductor device manufactured by using the method of the present disclosure is capable of effectively reducing parasitic capacitance. | 07-04-2013 |
20130168633 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A device that may be used for a phase change random access memory in a semiconductor device and a manufacturing method thereof are provided. The device includes a phase change unit and two sidewall electrodes respectively located on two opposite sidewalls of the phase change unit. The phase change unit includes a three layer structure, in which a phase change material layer is positioned between a top insulating material layer and a bottom insulating material layer. The first sidewall electrode and the second sidewall electrode are in contact with two opposite end faces of the phase change material layer. The contact area between electrode and phase change material is reduced, thereby obtaining a relatively small drive current and meeting a demand that the integrated level of such a device is increasingly enhanced. | 07-04-2013 |
20130134485 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions. | 05-30-2013 |
20130099193 | Phase Change Memory and Manufacturing Method Therefor - The present invention discloses a phase change memory and a manufacturing method thereof. The phase change memory according to the present invention uses top electrodes provided on the top of storage nodes to heat the storage nodes such that a phase change layer in the storage nodes undergoes a phase change. In the phase change memory of embodiments of the present invention, the contact area between the top electrode and the storage node is relatively small, which is good for phase change. Moreover, each column of storage nodes is connected by the same linear top electrode, which can improve photo alignment shift margin. | 04-25-2013 |
20130082015 | ELASTIC RETENTION WHEELS AND WAFER ADAPTER CONTAINING THE SAME WHEELS - An elastic retention wheel and a wafer adapter containing this wheel are disclosed. The elastic retention wheel comprises: a rim; a retention main body positioned within the rim; and a plurality of spokes. Each spoke is positioned in a space between the rim and the retention main body. One end of each spoke is coupled to the retention main body, and the other end is coupled to the rim. A sliding rail can be provided on an inner side of the rim, and the spoke's other end can slide with the sliding rail. When the elastic retention wheel is stressed by a non-uniform or excessive external force, these spokes provide enhanced support from the rim's inner side, or at least partially disperse the non-uniform external force applied to the elastic retention wheel. Thereby, the elastic retention wheel is largely kept from over-deformation or cracking. | 04-04-2013 |
20130075688 | Semiconductor Memory Device and Manufacturing Method Thereof - A semiconductor memory device includes a first insulating portion. The semiconductor memory device further includes a phase-change material element that contacts the first insulating portion. The semiconductor memory device further includes an electrode that contacts a side surface of the phase-change material element, the side surface of the phase-change material element being not parallel to a top surface of the electrode. The semiconductor memory device further includes a second insulating portion surrounding the phase-change material element. | 03-28-2013 |
20090033354 | Multi-purpose poly edge test structure - Multi-purpose poly edge test structure. According to an embodiment, the present invention provides a test structure. The test structure includes a doped silicon substrate, the doped silicon substrate being grounded, the doped silicon substrate including a first gate structure and a second gate structure, the first and second gate structures overlaying the doped silicon substrate. The test structure also includes a first conducting pad being electrically coupled to the first gate structure. The test structure also includes a second conducting pad being electrically coupled to the second gate structure. | 02-05-2009 |