STMicroelectronics S.A. Patent applications |
Patent application number | Title | Published |
20160097898 | PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING AT LEAST ONE COPLANAR WAVEGUIDE - An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via. | 04-07-2016 |
20160087594 | ELECTRONIC DEVICE FOR A RADIOFREQUENCY SIGNAL RECEPTION CHAIN, COMPRISING A LOW-NOISE TRANSIMPEDANCE AMPLIFIER STAGE - An electronic device includes a transimpedance amplifier stage having an amplifier end stage of the class AB type and a preamplifier stage coupled between an output of a frequency transposition stage and an input of the amplifier end stage. A self-biased common-mode control stage is configured to bias the preamplifier stage. The preamplifier stage is formed by a differential amplifier with an active load that is biased in response to the self-biased common-mode control stage. | 03-24-2016 |
20160078963 | PROGRAMMING OF ANTIFUSE CELLS - For programming an antifuse memory, the power consumption of the memory is assessed during programming mode. The power consumption is compared with a threshold. When the threshold is exceeded, indicative of successful programming of the antifuse memory cell, the programming mode is terminated. | 03-17-2016 |
20160049992 | HIGH DATA RATE SERIAL LINK - A data transmission circuit transmits a data signal over a transmission line. A digital to analog converter (DAC) operates to receive N-bit input digital values for conversion to corresponding ones of 2 | 02-18-2016 |
20160049189 | METHOD OF MINIMIZING THE OPERATING VOLTAGE OF AN SRAM CELL - An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively. | 02-18-2016 |
20150311277 | PMOS TRANSISTOR WITH IMPROVED MOBILITY OF THE CARRIERS - A substrate includes an active region oriented along a crystallographic face (100) and limited by an insulating region. A MOS transistor includes a channel oriented longitudinally along a crystallographic direction of the <110> type. A basic pattern made of metal and formed in the shape of a T is electrically inactive and situated over an area of the insulating region adjacent a transverse end of the channel. A horizontal branch of the T-shaped basic pattern is oriented substantially parallel to the longitudinal direction of the channel. | 10-29-2015 |
20150270447 | METHOD OF OPTIMIZING THE QUANTUM EFFICIENCY OF A PHOTODIODE - A photodiode has an active portion formed in a silicon substrate and covered with a stack of insulating layers successively including at least one first silicon oxide layer, an antireflection layer, and a second silicon oxide layer. The quantum efficiency of the photodiode is optimized by: determining, for the infrared wavelength, first thicknesses of the second layer corresponding to maximum absorptions of the photodiode, and selecting, from among the first thicknesses, a desired thickness, eox | 09-24-2015 |
20150270192 | INTEGRATED CIRCUIT CHIP ASSEMBLED ON AN INTERPOSER - A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device. | 09-24-2015 |
20150249179 | PHOTODETECTOR ON SILICON-ON-INSULATOR - A photodetector is formed in a silicon-on-insulator (SOI) type semiconductor layer. The photodetector includes a first region and a second region of a first conductivity type separated from each other by a central region of a second conductivity type so as to define a phototransistor. A transverse surface of the semiconductor layer is configured to receive an illumination. The transverse surface extends orthogonally to an upper surface of the central region. | 09-03-2015 |
20150206662 | METHOD FOR PRODUCING A CAPACITOR - A method for producing a capacitor stack in one portion of a substrate, the method including: forming a cavity along a thickness of the portion of the substrate from an upper face of the substrate, depositing a plurality of layers contributing to the capacitor stack onto the wall of the cavity and onto the surface of the upper face, and removing matter from the layers until the surface of the upper face is reached. The forming of the cavity includes forming at least one trench and, associated with each trench, at least one box. The at least one trench includes a trench outlet that opens into the box. The box includes a box outlet that opens at the surface of the upper face, and the box outlet being shaped to be larger than the trench outlet. | 07-23-2015 |
20150155319 | METHOD FOR PRODUCING AN INTEGRATED IMAGING DEVICE WITH FRONT FACE ILLUMINATION COMPRISING AT LEAST ONE METAL OPTICAL FILTER, AND CORRESPONDING DEVICE - An integrated imaging device supports front face illumination with one or more photosensitive regions formed in a substrate. A lower dielectric region is provided over the substrate, the lower dielectric region having an upper face. A metal optical filter having a metal pattern is provided on the upper face (or extending into the lower dielectric region from the upper face). An upper dielectric region is provided on top of the lower dielectric region and metal optical filter. The lower dielectric region is at least part of a pre-metal dielectric layer, and the upper dielectric region is at least part of a metallization layer. | 06-04-2015 |
20150155175 | METHOD FOR THE METALLIZATION OF A POROUS MATERIAL - Metallization method for a porous material including deposition of a metallic material in the liquid phase using a solution containing metal ions, the conditions consisting of the solution temperature, the pH of the solution, and the concentration of metal ions in solution being chosen to result in a deposition rate of the metallic material less than or equal to 0.1 nm/min. | 06-04-2015 |
20150155170 | METHOD OF FABRICATING A SEMICONDUCTOR SUBSTRATE ON INSULATOR - A method for producing a microelectronic device provided with different strained areas in the superficial layer of a semi-conductor on insulator type substrate comprising amorphizing a region of said superficial layer and then a lateral recrystallization of said region from crystalline areas adjoining this region ( | 06-04-2015 |
20150137133 | FORMING OF A HEAVILY-DOPED SILICON LAYER ON A MORE LIGHTLY-DOPED SILICON SUBSTRATE - A method of forming a heavily-doped silicon layer on a more lightly-doped silicon substrate including the steps of depositing a heavily-doped amorphous silicon layer; depositing a silicon nitride layer; and heating the amorphous silicon layer to a temperature higher than or equal to the melting temperature of silicon. | 05-21-2015 |
20150116029 | EXTENDED-DRAIN MOS TRANSISTOR IN A THIN FILM ON INSULATOR - An extended-drain transistor is formed in a semiconductor layer arranged on one side of an insulating layer with a semiconductor region being arranged on the other side of the insulating layer. The semiconductor region includes a first portion of a first conductivity type arranged in front of the source and at least one larger portion of the gate and a second portion of a second conductivity type arranged in front of at least the larger portion of the extended drain region, each of the first and second portions being coupled to a connection pad. | 04-30-2015 |
20150097241 | METHOD FOR RELAXING THE TRANSVERSE MECHANICAL STRESSES WITHIN THE ACTIVE REGION OF A MOS TRANSISTOR, AND CORRESPONDING INTEGRATED CIRCUIT - The transverse mechanical stress within the active region of a MOS transistor is relaxed by forming an insulating incursion, such as an insulated trench, within the active region of the MOS transistor. The insulated incursion is provided at least in a channel region of the MOS transistor so as to separate the channel region into two parts. The insulated incursion is configured to extend in a direction of a length of the MOS transistor. The insulated incursion may further extend into one or more of a source region or drain region located adjacent the channel region of the MOS transistor. | 04-09-2015 |
20150091116 | PROCESS FOR FORMING A STACK OF DIFFERENT MATERIALS, AND DEVICE COMPRISING THIS STACK - A stack of layers defines a filter and is formed by copper on hydrogenated silicon nitride supported by a carrier. The filter includes a layer of hydrogenated silicon nitride, a layer of silicon oxide on the layer of hydrogenated silicon nitride and a layer of copper on the layer of silicon oxide. The layer of hydrogenated silicon nitride may have, in a vicinity of its upper side, a ratio of a number of silicon atoms per cubic centimeter to a number of nitrogen atoms per cubic centimeter lower than 0.8 (or even lower than 0.6), with a number of silicon-hydrogen bonds smaller than or equal to 6×10 | 04-02-2015 |
20150091089 | AIR-SPACER MOS TRANSISTOR - A MOS transistor has a gate insulator layer that is made of a material of high dielectric constant deposited on a substrate. The gate insulator layer extends, with a constant thickness, under and beyond a gate stack. Spacers of low dielectric constant are formed on either side of the gate stack and vertically separated from the substrate by the extension of the gate insulator layer beyond the sides of the gate stack. The spacers of low dielectric constant are preferably air spacers. | 04-02-2015 |
20150086154 | OVERVOLTAGE PROTECTION COMPONENT AND AN ASSEMBLY OF INTEGRATED CIRCUIT CHIPS HAVING SAID OVERVOLTAGE PROTECTION COMPONENT - A device includes integrated circuit chips mounted on one another. At least one component for protecting elements of a second chip is formed in a first chip. The chips may be of the SOI type, with the first chip including a first SOI layer having a first thickness and the second chip including a second SOI layer having a second thickness smaller than the first thickness. The first chip including the component for protecting may include an optical waveguide with the component for protecting formed adjacent the optical waveguide. | 03-26-2015 |
20150076573 | METHOD FOR PRODUCING AN OPTICAL FILTER IN AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT - An integrated circuit includes a substrate and an interconnect part above the substrate, and further includes a photosensitive region in the substrate. A filter is provided aligned with the photosensitive region. The filter is formed by at least one layer of filter material. In one implementation for front side illumination, the layer of filter material is positioned above the photosensitive region between the interconnect part and the substrate. In another implementation for back side illumination, the layer of filter material is positioned below the photosensitive region opposite the interconnect part. The layer of filter material is configured such that a product of the thickness of the layer of filter material and the imaginary part of the refractive index of the layer of filter material is above 1 nm. | 03-19-2015 |
20150075749 | INTEGRATED CIRCUIT CHIP COOLING DEVICE - An integrated circuit chip cooling device includes a network of micropipes. A first pipe portion and a second pipe portion of the network are connected by at least one valve. The valve is formed of a bilayer strip. In response to change in temperature, the shape of the bilayer strip changes to move the valve from a substantially closed position to an open position. In one configuration, the change is irreversible. In another configuration, the change is reversible in response to an opposite change in temperature. | 03-19-2015 |
20150054042 | PHOTODIODE OF HIGH QUANTUM EFFICIENCY - A photodiode includes at least one central pad arranged on a light-receiving surface of a photodiode semiconductor substrate. The pad is made of a first material and includes lateral sidewalls surrounded by a spacer made of a second material having a different optical index than the first material. The lateral dimensions of the pad are smaller than an operating wavelength of the photodiode. Both the first and second materials are transparent to that operating wavelength. The pads and spacers are formed at a same time gate electrodes and sidewall spacers of MOS transistors are formed. | 02-26-2015 |
20150053924 | SPAD PHOTODIODE OF HIGH QUANTUM EFFICIENCY - A SPAD-type photodiode has a semiconductor substrate with a light-receiving surface. A lattice formed of interlaced strips made of a first material covers the light receiving surface. The lattice includes lattice openings with lateral walls covered by a spacer made of a second material. Then first and second materials have different optical indices, and further each optical index is less than or equal to the substrate optical index. A pitch of the lattice is of the order of a magnitude of an operating wavelength of the photodiode. The first and second materials are transparent at that operating wavelength. The lattice is made of a conductive material electrically coupled to an electrical connection node (for example, a bias voltage node). | 02-26-2015 |
20150053923 | BACK SIDE ILLUMINATION PHOTODIODE OF HIGH QUANTUM EFFICIENCY - A back side illumination photodiode includes a light-receiving back side surface of a semiconductor material substrate. An area of the light-receiving back side surface includes a recess. The recess is filled with a material having an optical index that is lower than an optical index of the semiconductor material substrate. Both the substrate and the filling material are transparent to an operating wavelength of the photodiode. The recess may be formed to have a ring shape. | 02-26-2015 |
20150050001 | COPLANAR WAVEGUIDE - A coplanar waveguide electronic device is formed on a substrate. The waveguide includes a signal ribbon and a ground plane. The signal ribbon is formed of two or more signal lines of a same level of metallization that are electrically connected together. The ground plane is formed of an electrically conducting material which includes rows of holes. | 02-19-2015 |
20150044841 | METHOD FOR FORMING DOPED AREAS UNDER TRANSISTOR SPACERS - Method for fabricating a transistor comprising the steps consisting of:
| 02-12-2015 |
20150044828 | RECRYSTALLIZATION OF SOURCE AND DRAIN BLOCKS FROM ABOVE - A Method for manufacturing a transistor comprising:
| 02-12-2015 |
20150041943 | METHOD FOR FABRICATING A THICK MULTILAYER OPTICAL FILTER WITHIN AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUIT COMPRISING A THICK MULTILAYER OPTICAL FILTER - A multilayer optical filter is provided for an integrated circuit including a substrate and a metallization layer interconnection part. The optical filter is formed from a first filter part located within the interconnection part and positioned over a photosensitive region of the substrate. The optical filter further includes a second filter part positioned above the first filter part and the interconnection part. The first and second filter parts each include a metal layer. The first and second filter parts are separated from each other as a function of a wavelength in vacuum of an optical signal to be filtered and received by the photosensitive region. | 02-12-2015 |
20150028488 | METHOD FOR MANUFACTURING A CONDUCTING CONTACT ON A CONDUCTING ELEMENT - The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element. | 01-29-2015 |
20140376852 | ELECTRO-OPTICAL PHASE SHIFTER HAVING A LOW ABSORPTION COEFFICIENT - A semiconductor electro-optical phase shifter may include a central zone configured to be placed in an optical waveguide and doped at a first conductivity type, a first lateral zone adjacent a first face of the central region and doped at a second conductivity type, and a second lateral zone adjacent a second face of the central zone and doped at the second conductivity type. | 12-25-2014 |
20140370668 | METHOD OF MAKING A TRANSITOR - The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack. | 12-18-2014 |
20140370666 | METHOD OF MAKING A SEMICONDUCTOR LAYER HAVING AT LEAST TWO DIFFERENT THICKNESSES - A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions. | 12-18-2014 |
20140361440 | PROCESS FOR PRODUCING AT LEAST ONE THROUGH-SILICON VIA WITH IMPROVED HEAT DISSIPATION, AND CORRESPONDING THREE-DIMENSIONAL INTEGRATED STRUCTURE - A method for producing at least one through-silicon via inside a substrate may include forming a cavity in the substrate from a first side of the substrate until an electrically conductive portion is emerged onto. The method may also include forming an electrically conductive layer at a bottom and on walls of the cavity, and at least partly on a first side outside the cavity. The process may further include at least partially filling the cavity with at least one phase-change material. Another aspect is directed to a three-dimensional integrated structure. | 12-11-2014 |
20140355925 | POSITIVE COEFFICIENT DYNAMIC ELECTRO-OPTICAL PHASE SHIFTER - A semiconductor electro-optical phase shifter may include an optical action zone configured to be inserted in an optical waveguide, and a bipolar transistor structure configured so that, in operation, collector current of the bipolar transistor structure crosses the optical action zone perpendicular to the axis of the optical waveguide. | 12-04-2014 |
20140354276 | INTEGRATED HALL EFFECT SENSOR - The generation of a Hall voltage within a semiconductor film of an integrated Hall effect sensor uses the flow of a current within the semiconductor film when subjected to a magnetic field. The film is disposed on top of an insulating layer, referred to as buried layer, which is itself disposed on top of a carrier substrate containing a buried electrode that is situated under the insulating layer. A biasing voltage is applied to the buried electrode. | 12-04-2014 |
20140347907 | ELECTRONIC COMPONENT INCLUDING A MATRIX OF TCAM CELLS - Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of one of the reference data words; the cells of a given column are dedicated to the comparison of the same bit of the input data word; each cell incorporates: two memory points storing the data representing the reference data bit; a comparison circuit connected to the memory points, with a comparison point of which the potential represents the comparison if the input data bit and the data stored in the memory points, and also incorporating a common comparison circuit to which are connected the comparison circuits of all or part of the cells of a given column; the comparison circuit incorporates terminals to which the bit from the input data word and its complement are applied. | 11-27-2014 |
20140347906 | TCAM MEMORY CELL AND COMPONENT INCORPORATING A MATRIX OF SUCH CELLS - A ternary content-addressable cell is configured to compare an input binary data item present on an input terminal with two reference binary data items, and to output a match signal on a match line. The cell includes: a first storage circuit (storing a potential representing the first reference binary data item) and a second storage cell (storing a potential representing the second reference binary data item). A comparison circuit is connected to the first and second storage circuits and to the input terminal SL. A comparison node presents a potential representing the comparison of the input binary data item with the first and second reference data items. The comparison node is connected to an output stage, and the output stage is connected to the match line. The signal on the match line is based on the potential of the comparison node. | 11-27-2014 |
20140341499 | DUAL STATIC ELECTRO-OPTICAL PHASE SHIFTER HAVING TWO CONTROL TERMINALS - A semiconductor electro-optical phase shifter comprises a central zone (I | 11-20-2014 |
20140341498 | STATIC ELECTRO-OPTICAL PHASE SHIFTER HAVING A DUAL PIN JUNCTION - A semiconductor electro-optical phase shifter may include a first optical action zone having a minimum doping level, a first lateral zone and a central zone flanking the first optical action zone along a first axis, doped respectively at first and second conductivity types so as to form a P-I-N junction between the first lateral zone and the central zone. The phase shifter may include a second optical action zone having a threshold doping level, and a second lateral zone flanking the second optical action zone with the central zone along the first axis doped at the first conductivity type so as to form a P-I-N junction between the second lateral zone and the central zone. | 11-20-2014 |
20140335663 | METHOD OF MAKING A TRANSITOR - A method for manufacturing a transistor includes forming a stack of semiconductor on insulator type layers including at least one substrate, surmounted by a first insulating layer and an active layer to form a channel for the transistor; forming a gate stack on the active layer; producing a source and a drain including forming, on either side of the gate stack, cavities by at least one step of etching the active layer, the first insulating layer, and part of the substrate selectively to the gate stack to remove the active layer, the first insulating layer, and a portion of the substrate outside regions situated below the gate stack; forming a second insulating layer on the bared surfaces of the substrate, to form a continuous insulating layer with the first insulating layer; baring of the lateral ends of the channel; and the filling of the cavities by epitaxy. | 11-13-2014 |
20140325181 | HIERARCHICAL RECONFIGURABLE COMPUTER ARCHITECTURE - A reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels include a first level including a first computation block including a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting mechanism, each computing node including an input port, a functional unit and an output port, the first connecting mechanism capable of connecting each output port to the input port of each other computing node; and a second level including a second computation block including a second data input, a second data output and a plurality of the first computation blocks interconnected by a second connecting means for selectively connecting the first data output of each of the first computation blocks and the second data input to each of the first data inputs and for selectively connecting each of the first data outputs to the second data output. | 10-30-2014 |
20140287705 | Method for Processing a Frequency-Modulated Analog Signal and Corresponding Device - A method and corresponding device for processing a frequency-modulated analog signal are disclosed. The signal includes a number of symbols belonging to a set of M symbols respectively associated with at least one frequency of a set of M frequencies. The method includes a phase of reading each symbol of the signal that includes a sampling of a signal portion corresponding to the duration of a symbol and delivering N samples (M being less than N). M individual discrete Fourier transform processing operations are performed on the N samples. Each individual processing operation is associated with each of the frequencies. The M individual processing operations deliver M processing results. The value of the symbol can be determined from the M processing results. | 09-25-2014 |
20140246723 | METHOD FOR MANUFACTURING A FIN MOS TRANSISTOR - A method for manufacturing a fin MOS transistor from an SOI-type structure including a semiconductor layer on a silicon oxide layer coating a semiconductor support, this method including the steps of: a) forming, from the surface of the semiconductor layer, at least one trench delimiting at least one fin in the semiconductor layer and extending all the way to the surface of the semiconductor support; b) etching the sides of a portion of the silicon oxide layer located under the fin to form at least one recess under the fin; and c) filling the recess with a material selectively etchable over silicon oxide. | 09-04-2014 |
20140241657 | OPTICAL MODULATOR WITH AUTOMATIC BIAS CORRECTION - An optical modulator uses an optoelectronic phase comparator configured to provide, in the form of an electrical signal, a measure of a phase difference between two optical waves. The phase comparator includes an optical directional coupler having two coupled channels respectively defining two optical inputs for receiving the two optical waves to be compared. Two photodiodes are configured to respectively receive the optical output powers of the two channels of the directional coupler. An electrical circuit is configured to supply, as a measure of the optical phase shift, an electrical signal proportional to the difference between the electrical signals produced by the two photodiodes. | 08-28-2014 |
20140241102 | DUAL CLOCK EDGE TRIGGERED MEMORY - A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock. | 08-28-2014 |
20140235186 | RADIO FREQUENCY SIGNAL TRANSMISSION METHOD AND DEVICE - A method for generating a radio frequency signal, wherein a signal to be transmitted is decomposed into a weighted sum of periodic basic signals of different frequencies. | 08-21-2014 |
20140233671 | SIGNAL GENERATION DEVICE - A device for generating a signal, including: a balun; and a circuit capable of summing up, on a first access terminal of the balun, currents representative of signals received on first input terminals of the device, and on a second access terminal of the balun, currents representative of signals received on second input terminals of the device. | 08-21-2014 |
20140232575 | Method and Device for use with Analog to Digital Converter - According to one mode of implementation, a method includes an estimation including on the one hand a correlation processing involving at least one part of the sampled signal, at least one part of at least one first signal gleaned from a derived signal representative of a temporal derivative of the sampled signal and at least one part of N partial filtered signals respectively representative of N weighted differences between N pairs of bracketing versions flanking the sampled signal, N being greater than or equal to 1. On the other hand, the estimation includes a matrix processing on the results of this correlation processing. Correction processing of the M−1 trains involves respectively M−1 second signals gleaned from the derived signal and the suite of M−1 shift coefficients. | 08-21-2014 |
20140217520 | AIR-SPACER MOS TRANSISTOR - A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion. | 08-07-2014 |
20140210071 | INTEGRATED STRUCTURE WITH IMPROVED HEAT DISSIPATION - An integrated structure includes a support supporting at least one chip and a heat dissipating housing, attached to the chip. The housing is thermally conductive and has a thermal expansion compatible with the chip. The housing may further including closed cavities filled with a phase change material. | 07-31-2014 |
20140206295 | Radio Frequency Splitter - A multichannel splitter formed from 1 to 2 splitters. An input terminal of a first 1 to 2 splitter defines an input of the multichannel splitter. The 1 to 2 splitters are electrically series-connected. First respective outputs of the 1 to 2 splitters define output terminals of the multichannel splitter. | 07-24-2014 |
20140197448 | Bidirectional Semiconductor Device for Protection against Electrostatic Discharges - An integrated circuit is produced on a bulk semiconductor substrate in a given CMOS technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate thyristors coupled in parallel and head-to-tail. Each thyristor has a pair of electrode regions. The two thyristors respectively have two separate gates and a common semiconductor gate region. The product of the current gains of the two transistors of each thyristor is greater than 1. Each electrode region of at least one of the thyristors has a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the thyristor an intrinsic triggering voltage less than the breakdown voltage of a transistor to be protected, and produced in the CMOS technology. | 07-17-2014 |
20140183685 | IMAGE SENSOR - An image sensor arranged inside and on top of a semiconductor substrate, having a plurality of pixels, each including: a photosensitive area, a read area, and a storage area extending between the photosensitive area and the read area; at least one first insulated vertical electrode extending in the substrate between the photosensitive area and the storage area; and at least one second insulated vertical electrode extending in the substrate between the storage area and the read area. | 07-03-2014 |
20140170834 | METHOD FOR MANUFACTURING A HYBRID SOI/BULK SEMICONDUCTOR WAFER - A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings. | 06-19-2014 |
20140167527 | Method and Device for Management of an Electrical Power-Up of a Sector of an Electronic Circuit - A chain of switches is connected between a first power supply line coupled to a first voltage and a second power supply line coupled to the sector. These switches are controllable by a control signal. The control signal is propagated from a first end of the first chain towards a second end of the first chain without control of the switches during this first propagation. The control signal is then propagated in the reverse direction from the second end towards the first end with a control of the switches during this second propagation starting from a group of at least one switch situated at the second end. There is a detection of the arrival of the control signal at the first end of the chain at the end of its propagation in the reverse direction. | 06-19-2014 |
20140167167 | CMOS CELL PRODUCED IN FD-SOI TECHNOLOGY - An integrated cell may include an nMOS transistor, and an pMOS transistor. The cell may be produced in fully depleted silicon-on-insulator technology, and it is possible for the substrates of the transistors of the cell to be biased with the same adjustable biasing voltage. | 06-19-2014 |
20140167116 | HETEROJUNCTION BIPOLAR TRANSISTOR - The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches,=; and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess. | 06-19-2014 |
20140156248 | TRANSIENT SIMULATION METHOD FOR A PHOTODIODE - A simulation method for a P-I-N junction photodiode uses a model that may include a diode model configured to characterize electrical behavior of the P-I-N junction photodiode, and an input for applying a fictitious electrical signal representing optical power received by the P-I-N junction photodiode. A current source model may be coupled to the diode model and may have a transient response to a variation of the fictitious electrical signal, based upon a sum of a first first-order transient response with a time constant based upon to a transit time of carriers in a depletion region of the P-I-N junction, and a second first-order transient response with a time constant based upon a diffusion time of carriers outside of the depletion region. The first and second responses may be respectively weighted by a length of the depletion region and a length of the P-I-N junction outside the depletion region. | 06-05-2014 |
20140153078 | SIMULATION METHOD FOR AN OPTICAL MODULATOR - A simulation model is for an optical modulator that may include an optical phase shifter in a semiconductor material structure between two sections of an optical waveguide. The semiconductor material structure may include one of a P-N and P-I-N junction in a plane parallel to an axis of the optical waveguide. The model may include a diode configured to characterize an electrical behavior of the one of the P-N and P-I-N junction such that a change in a global refractive index of the optical phase shifter is expressed, by a coefficient, based upon an amount of charges in the one of the P-N and P-I-N junctions and raised to a power. The coefficient and the power may be empirical values based upon the semiconductor material and a wavelength. | 06-05-2014 |
20140151561 | TERAHERTZ IMAGER WITH GLOBAL RESET - A pixel circuit including: a detection circuit having first and second transistors coupled in series between differential output nodes of an antenna, wherein the antenna is configured to be sensitive to terahertz radiation; a capacitor coupled to an intermediate node between the first and second transistors; and control circuitry coupled to control nodes of the first and second transistors, the control circuitry being configured for selectively applying to the control nodes one of: a gate biasing voltage for biasing the control nodes of the first and second transistors during a detection phase of the pixel circuit; and a reset voltage for resetting a voltage stored by the capacitor. | 06-05-2014 |
20140145897 | ANTENNA CIRCUIT USING MULTIPLE INDEPENDENT ANTENNAS SIMULTANEOUSLY THROUGH A SINGLE FEED - An antenna circuit includes a first antenna tuned to a first fundamental frequency and a second antenna tuned to a second fundamental frequency different from the first fundamental frequency. A first filter has a first terminal connected to the first antenna and attenuates the frequency components outside of a band defined by the first fundamental frequency or its harmonics. A second filter has a first terminal coupled to the second antenna and attenuates the frequency components outside of a band defined by the second fundamental frequency or its harmonics. A passive recombination element couples the second terminals of the two filters to a common terminal. | 05-29-2014 |
20140132338 | METHOD FOR PROVIDING A SYSTEM ON CHIP WITH POWER AND BODY BIAS VOLTAGES - Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected. | 05-15-2014 |
20140126647 | METHOD AND DEVICE FOR IMAGE INTERPOLATION SYSTEMS BASED ON MOTION ESTIMATION AND COMPENSATION - A motion estimation method and device are provided for processing images to be inserted, between a preceding original image and a following original image, into a sequence of images. Each image is divided into pixel blocks associated with motion vectors. For a current block of an image being processed, motion vectors associated with blocks of the image being processed and/or associated with blocks of a processed image are selected. Candidate vectors are generated from selected motion vectors. An error is calculated for each candidate vector. A penalty is determined for a subset of candidate vectors on the basis of the values of the pixels of the pixel block in the preceding original image from which the candidate motion vector points to the current block and/or on the basis of the values of the pixels of the pixel block in the following original image to which the candidate motion vector points from the current block. | 05-08-2014 |
20140124866 | INTEGRATED CIRCUIT COMPRISING A MOS TRANSISTOR HAVING A SIGMOID RESPONSE AND CORRESPONDING METHOD OF FABRICATION - An integrated circuit may include at least one MOS transistor having a sigmoid response. The at least one MOS transistor may include a substrate, a source region, a drain region, a gate region, and insulating spacer regions on either side of the gate region. The substrate may include a first region situated under the gate region between the insulating spacer regions. At least one of the source and drain regions may be separated from the first region of the substrate by a second region of the substrate situated under an insulating spacer region, which may be of a same type of conductivity as the first region of the substrate. | 05-08-2014 |
20140103972 | DUTY CYCLE PROTECTION CIRCUIT - A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal. | 04-17-2014 |
20140091881 | PASSIVE FILTER - A passive filter may include at least one elliptical filter unit and at least one asymmetric rejection filter unit coupled in series with the elliptical filter unit. The at least one asymmetric rejection filter unit may have a frequency response curve that includes a dip with different attenuations on either side, and an overshoot upon exiting the dip at the side with the lower attenuation. | 04-03-2014 |
20140091846 | INTEGRATED COMPARATOR WITH HYSTERESIS, IN PARTICULAR PRODUCED IN AN FD SOI TECHNOLOGY - A comparator circuit includes an input differential amplifier circuit generating an output signal and an inverting output circuit generating a complemented output signal. The differential amplifier circuit is formed of a differential pair of input transistors and a pair of diode connected load transistors. The comparator circuit is integrated in a silicon on insulator type structure. A hysteresis-creating circuit is formed by coupling one or more of the output signal and complemented output signal to a substrate region (in the silicon on insulator type structure) associated with one or more of the differential pair of input transistors and pair of diode connected load transistors. The differential amplifier circuit may further include auxiliary transistors coupled to the diode connected load transistors and the hysteresis-creating circuit may further couple one or more of the output signal and complemented output signal to the substrate region associated with the auxiliary transistor. | 04-03-2014 |
20140089885 | ELECTRONIC CIRCUIT DESIGN METHOD - A first assembly of critical cells is to be monitored. An equivalent capacitance of output cells coupled to the critical path is determined. Logic level inputs of the critical cells for signal propagation are also determined. A second assembly of control logic cells is provided which copies the first assembly in terms of number of cells, type of cells and cell connection such that each of the control cells is a homolog of a corresponding critical cell. Charge cells are provided at the outputs of the control cells having an equivalent capacitance in accordance with the determined capacitance of the output cells. For each control cell, logic levels are asserted in accordance with the determined configuration of the critical path. A signal generator applies a signal the input of the second assembly and a signal receiver is coupled to the output of the second assembly. | 03-27-2014 |
20140075726 | METHOD FOR MANUFACTURING BAW RESONATORS ON A SEMICONDUCTOR WAFER - A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator. | 03-20-2014 |
20140070893 | High Frequency Oscillator - A frequency oscillator includes a ring oscillator having N inverters coupled in series, where N is an odd integer equal to three or more. A first filter is coupled between an output node of a first of the inverters and an output line of the frequency oscillator. A second filter is coupled between an output node of a second of the inverters and the output line of the frequency oscillator. | 03-13-2014 |
20140070331 | METAL OXIDE SEMICONDUCTOR (MOS) DEVICE WITH LOCALLY THICKENED GATE OXIDE - A method of fabricating a semiconductor device including providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized, which also oxidizes at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure. | 03-13-2014 |
20140070103 | Terahertz Imager - A terahertz imager includes an array of pixel circuits. Each pixel circuit has an antenna and a detector. The detector is coupled to differential output terminals of the antenna. A frequency oscillator is configured to generate a frequency signal on an output line. The output line is coupled to an input terminal of the antenna of at least one of the pixel circuits. | 03-13-2014 |
20140061723 | MOS TRANSISTOR - A MOS transistor including a U-shaped channel-forming semiconductor region and source and drain regions having the same U shape located against the channel-forming region on either side thereof, the internal surface of the channel-forming semiconductor region being coated with a conductive gate, a gate insulator being interposed. | 03-06-2014 |
20140035644 | ADAPTIVE MULTI-STAGE SLACK BORROWING FOR HIGH PERFORMANCE ERROR RESILIENT COMPUTING - Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput. | 02-06-2014 |
20140032188 | METHOD FOR DETERMINING A MATHEMATICAL MODEL OF THE ELECTRIC BEHAVIOR OF A PN JUNCTION DIODE, AND CORRESPONDING DEVICE - The electric behavior of a reverse-biased PN junction diode is modeled by measuring the value of voltage V present across the diode and the value of the corresponding current I running through this diode, the voltage V varying within a range of values including the value of diode breakdown voltage. A representation of a function | 01-30-2014 |
20140015002 | MOS TRANSISTOR ON SOI PROTECTED AGAINST OVERVOLTAGES - A MOS transistor protected against overvoltages formed in an SOI-type semiconductor layer arranged on an insulating layer itself arranged on a semiconductor substrate including a lateral field-effect control thyristor formed in the substrate at least partly under the MOS transistor, a field-effect turn-on region of the thyristor extending under at least a portion of a main electrode of the MOS transistor and being separated there-from by said insulating layer, the anode and the cathode of the thyristor being respectively connected to the drain and to the source of the MOS transistor, whereby the thyristor turns on in case of a positive overvoltage between the drain and the source of the MOS transistor. | 01-16-2014 |
20130321057 | INTEGRATED CIRCUIT COMPRISING AT LEAST ONE DIGITAL OUTPUT PORT HAVING AN ADJUSTABLE IMPEDANCE, AND CORRESPONDING ADJUSTMENT METHOD - An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors. | 12-05-2013 |
20130313724 | SHIELDED COPLANAR LINE - In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench. | 11-28-2013 |
20130300458 | Clock Signal Synchronization Circuit - A circuit for detecting a time skew, including: at least two comparators; a first set of paths respectively connecting a first source of a first signal to said comparators; and a second set of paths respectively connecting a second source of a second signal to said comparators, each comparator detecting a possible skew between said first and second signals. | 11-14-2013 |
20130295734 | METHOD FOR FORMING GATE, SOURCE, AND DRAIN CONTACTS ON A MOS TRANSISTOR - A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer. | 11-07-2013 |
20130292824 | CONNECTION OF A CHIP PROVIDED WITH THROUGH VIAS - A chip provided with through vias wherein the vias are formed of an opening with insulated walls coated with a conductive material and filled with an easily deformable insulating material, elements of connection to another chip being arranged in front of the easily deformable insulating material. | 11-07-2013 |
20130273440 | HOUSING, IN PARTICULAR FOR A BIOFUEL CELL - A housing includes a body with a first silicon element and a second porous silicon element, at least one first cavity provided in the porous silicon element, a first electrically conducting contact area electrically coupled to at least a portion of at least one internal wall of the at least one first cavity, and a second electrically conducting contact area electrically coupled to a different portion of the at least one internal wall of the second porous silicon element of the at least one first cavity, wherein the two contact areas are electrically isolated from each other. | 10-17-2013 |
20130270649 | BIPOLAR TRANSISTOR MANUFACTURING METHOD - A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench. | 10-17-2013 |
20130264677 | METHOD FOR PRODUCING AN ELECTRONIC DEVICE BY ASSEMBLING SEMI-CONDUCTING BLOCKS AND CORRESPONDING DEVICE - At least three electrically conducting blocks are disposed within an isolating region; and at least two of them are mutually separated and capacitively coupled by a part of the isolating region. At least two of them, being semiconductor, have opposite types of conductivity or identical types of conductivity, but with different concentrations of dopants, and these are in mutual contact by one of their sides. The mutual arrangement of these blocks within the isolating region, their type of conductivity and their concentration of dopants form at least one electronic module. Some of the blocks define input and output blocks. | 10-10-2013 |
20130262057 | SCR SIMULATION MODEL - A model for simulating the electrical behavior of a thyristor includes a model of an NPN bipolar transistor whose emitter forms the cathode of the thyristor and the base forms a low-side control terminal of the thyristor, and a model of a PNP bipolar transistor whose emitter forms the anode of the thyristor and the base forms a high-side control terminal of the thyristor, the collector of the PNP transistor being connected to the low-side control terminal and the collector of the NPN transistor being connected to the high-side control terminal. The transistor models are present a small signal behavior over the entire range of anode currents of the thyristor, whereby the transistor models exhibit a gain drop when the anode current exits the small signal range. | 10-03-2013 |
20130234218 | METAL OXIDE SEMICONDUCTOR (MOS) DEVICE WITH LOCALLY THICKENED GATE OXIDE - A method of fabricating a semiconductor device including providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized, which also oxidizes at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure. | 09-12-2013 |
20130223138 | SECURE NON-VOLATILE MEMORY - A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope. | 08-29-2013 |
20130214976 | METHOD FOR LOCALIZING AN OBJECT - A method for localizing an object, including the acts of: transmission of a first signal by a first transmitter assigned to the object and of a second signal by at least one second transmitter; reception of the first and of the second signal by at least three receivers; in each receiver and for the first and the second signal: a) generation of a first and of a second reference signal; b) correlation between the first signal and the first reference signal and between the second signal and the second reference signal; c) interpolation of samples resulting from the correlation; d) deduction of the propagation time of the first and of the second signal; e) calculation of the difference between the propagation times of the first and of the second signal; and, by triangulation, deduction of the position of the object. | 08-22-2013 |
20130214326 | Bidirectional Semiconductor Device for Protection Against Electrostatic Discharges, Usable on Silicon on Insulator - A device includes, within a layer of silicon on insulator, a central semiconductor zone including a central region having a first type of conductivity, two intermediate regions having a second type of conductivity opposite to that of the first one, respectively disposed on either side of and in contact with the central region in order to form two PN junctions, two semiconductor end zones respectively disposed on either side of the central zone, each end zone comprising two end regions of opposite types of conductivity, in contact with the adjacent intermediate region, the two end regions of each end zone being mutually connected electrically in order to form the two terminals of the device. | 08-22-2013 |
20130201771 | Volatile Memory with a Decreased Consumption - A volatile memory including volatile memory cells adapted to the performing of data write and read operations. The memory cells are arranged in rows and in columns and, further, are distributed in separate groups of memory cells for each row. The memory includes a first memory cell selection circuit configured to perform write operations and a second memory cell selection circuit, different from the first circuit, configured to perform read operations. The first circuit is capable of selecting, for each row, memory cells from one of the group of memory cells for a write operation. The second circuit is capable of selecting, for each row, memory cells from one of the groups of memory cells for a read operation. | 08-08-2013 |
20130201766 | Volatile Memory with a Decreased Consumption and an Improved Storage Capacity - A volatile memory includes volatile memory cells in which data write and read operations are performed. The memory cells are arranged in rows and in columns and are distributed in first separate groups of memory cells for each column. The memory includes, for each column, a write bit line dedicated to write operations and connected to all the memory cells of the column and read bit lines dedicated to read operations. Each read bit line is connected to all the memory cells of one of the first groups of memory cells. Each memory cell in the column is connected to a single one of the read bit lines. | 08-08-2013 |
20130200440 | HIGH-K HETEROSTRUCTURE - A method for preparing a multilayer substrate includes the step of deposing an epitaxial γ-Al | 08-08-2013 |
20130196500 | METHOD FOR FORMING A VIA CONTACTING SEVERAL LEVELS OF SEMICONDUCTOR LAYERS - A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material. | 08-01-2013 |
20130193550 | 3D INTEGRATED CIRCUIT - A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer. | 08-01-2013 |
20130183774 | Integrated Circuit Testing Method - A method for testing an integrated circuit includes determining performance data of the integrated circuit, wherein at least first and second derivatives of S parameters of the integrated circuit are taken into account when determining the expected performance data. The performance data can be determined by measuring S parameters of the integrated circuit. An equivalent non-linear model of the integrated circuit can be determined from the provided S parameters and first and second derivatives of the provided S parameters. The non-linear behavior of the integrated circuit can be quantified from the equivalent non-linear model. | 07-18-2013 |
20130182523 | ROBUST SRAM MEMORY CELL CAPACITOR PLATE VOLTAGE GENERATOR - An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies. | 07-18-2013 |
20130181785 | DEVICE OF VARIABLE CAPACITANCE - A variable capacitance device including: first and second transistors coupled in series by their main current nodes between first and second nodes of the device, a control node of the first transistor being adapted to receive a first control signal, and a control node of the second transistor being adapted to receive a second control signal; and control circuitry adapted to generate the first and second control signals from a selection signal. | 07-18-2013 |
20130181784 | VARIABLE CAPACITANCE DEVICE - A variable capacitance device including: first and second transistors coupled in parallel between first and second nodes of the capacitive device, a control node of the first transistor being adapted to receive a control signal, and a control node of the second transistor being adapted to receive the inverse of the control signal, wherein the first and second transistors are formed in a same semiconductor well. | 07-18-2013 |
20130157587 | INTEGRATED CIRCUIT COMPRISING AN INTEGRATED TRANSFORMER OF THE "BALUN" TYPE WITH SEVERAL INPUT AND OUTPUT CHANNELS - An integrated circuit includes an integrated transformer of the balanced-to-unbalanced type with N channels, wherein N is greater than 2. The integrated transformer includes, on a substrate, N inductive circuits that are mutually inductively coupled, and respectively associated with N channels. | 06-20-2013 |
20130157562 | WIRELESS DEVICE PAIRING - A wireless unit includes a first motion sensitive device; communications circuitry for wirelessly communicating with a further wireless unit; and a processing device configured to compare at least one first motion vector received from the first motion sensitive device with at least one second motion vector received from a second motion sensitive device of the further wireless unit. | 06-20-2013 |
20130155558 | COMPACT ELECTRONIC DEVICE FOR PROTECTING FROM ELECTROSTATIC DISCHARGE - A device for protecting a set of N nodes from electrostatic discharges, wherein N is greater than or equal to three, includes a set of N units respectively possessing N first terminals respectively connected to the N nodes and N second terminals connected together to form a common terminal. Each unit includes at least one MOS transistor including a parasitic transistor connected between a pair of the N nodes and configured, in the presence of a current pulse between the pair of nodes, to operate, at least temporarily, in a hybrid mode including MOS-type operation in a sub-threshold mode and operation of the bipolar transistor. | 06-20-2013 |
20130155303 | METHOD OF CAPTURING AN IMAGE WITH AN IMAGE SENSOR - A method may include a cycle of reading a current pixel including connecting the capacitive node of the pixel to a capacitive node of a previous pixel already read, connecting the capacitive node of the current pixel and the capacitive node of a previous pixel to an output line, reading a first voltage of the capacitive node of the pixel through the output line, transferring charges from the accumulation node to the capacitive node of the pixel, reading a second voltage of the capacitive node of the pixel through the output line, and disconnecting the capacitive node from the capacitive node of a previous pixel, and a cycle of reading a next pixel. This cycle may include accumulating charges in the accumulation node of the next pixel while the capacitive node of the current pixel is connected to a capacitive node of a previous pixel. | 06-20-2013 |
20130155283 | HARDENED PHOTODIODE IMAGE SENSOR - An image sensor including a pixel array, each pixel including, in a substrate of a doped semiconductor material of a first conductivity type, a first doped region of a second conductivity type at the surface of the substrate; an insulating trench surrounding the first region; a second doped region of the first conductivity type, more heavily doped than the substrate, at the surface of the substrate and surrounding the trench; a third doped region of the second conductivity type, forming with the substrate a photodiode junction, extending in depth into the substrate under the first and second regions and being connected to the first region; and a fourth region, more lightly doped than the second and third regions, interposed between the second and third regions and in contact with the first region and/or with the third region. | 06-20-2013 |
20130142227 | COMMUNICATIONS ARRANGEMENT FOR A SYSTEM IN PACKAGE - A circuit includes a first n-bit communications block and a second m-bit communications block. A controller is configured to control mode of operation for the first and second communications blocks. In a first mode, the first and second communications blocks function as a single communications block for n+m bit communications. In a second mode, the first and second communications blocks operate as substantially independent communications block for n bit communications and m bit communications. | 06-06-2013 |
20130142003 | DUAL CLOCK EDGE TRIGGERED MEMORY - A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock. | 06-06-2013 |
20130141824 | Electronic Device, in Particular for Protection Against Electrostatic Discharges, and Method for Protecting a Component Against Electrostatic Discharges - The electronic device includes a first (BP) and a second (BN) terminal and electronic means coupled between said two terminals; the electronic means include at least one block (BLC) comprising an MOS transistor (TR) including a parasitic bipolar transistor, the MOS transistor having the drain (D) thereof coupled to the first terminal (BP), the source (S) thereof coupled to the second terminal (BN) and being additionally configured, in the event of a current pulse (IMP) between the two terminals, to operate in a hybrid mode including MOS operation in a subthreshold mode and operation of the parasitic bipolar transistor. The device can comprise two blocks (BLC | 06-06-2013 |
20130140693 | METHOD FOR FORMING AN INTEGRATED CIRCUIT - A method for forming an integrated circuit including the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 μm, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels on the front surface and leveling the surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling the surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material. | 06-06-2013 |
20130138975 | PROTECTION OF MEMORY AREAS - A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit. | 05-30-2013 |
20130120087 | COPLANAR WAVEGUIDE - An embodiment relates to a coplanar waveguide electronic device comprising a substrate whereon is mounted a signal ribbon and at least a ground plane. The signal ribbon comprises a plurality of signal lines of a same level of metallization electrically connected together, and the ground plane is made of an electrically conducting material and comprises a plurality of holes. | 05-16-2013 |
20130120049 | Power Switch - A power switch includes first and second MOS transistors in series between first and second nodes. Both the first and second transistors have a gate coupled to its substrate. First and second resistive elements are coupled between the gate of the first transistor and the first node, and between the gate of the second transistor and the second node, respectively. A triac is coupled between the first and second nodes. The gate of the triac is coupled to a third node common to the first and second transistors. A third MOS transistor has a first conduction electrode coupled to the gate of the first transistor and a second conduction electrode coupled to the gate of the second transistor. | 05-16-2013 |
20130113017 | ELECTRONIC DEVICE FOR PROTECTING FROM ELECTROSTATIC DISCHARGE - A protection device includes a triac and triggering units. Each triggering unit is formed by a MOS transistor configured to operate at least temporarily in a hybrid operating mode and a field-effect diode. The field-effect diode has a controlled gate that is connected to the gate of the MOS transistor. | 05-09-2013 |
20130105664 | IMAGE SENSOR WITH INDIVIDUALLY SELECTABLE IMAGING ELEMENTS | 05-02-2013 |
20130099797 | Variable Impedance Device - A variable impedance device includes a passive tuner that includes at least one variable component, which is controllable to apply a variable impedance value to an input signal of the passive tuner. A low noise amplifier is configured to supply the input signal to the passive tuner by amplifying an input RF (radio frequency) signal. | 04-25-2013 |
20130075870 | METHOD FOR PROTECTION OF A LAYER OF A VERTICAL STACK AND CORRESPONDING DEVICE - A device and corresponding fabrication method includes a vertical stack having an intermediate layer between a lower region and an upper region. The intermediate layer is extended by a protection layer. The vertical stack has a free lateral face on which the lower region, the upper region and the protection layer are exposed. | 03-28-2013 |
20130072032 | METHOD FOR DEPOSITING A SILICON OXIDE LAYER OF SAME THICKNESS ON SILICON AND ON SILICON-GERMANIUM - A method for depositing a silicon oxide layer on a substrate including a silicon region and a silicon-germanium region, including the steps of: forming a very thin silicon layer having a thickness ranging from 0.1 to 1 nm above silicon-germanium; and depositing a silicon oxide layer on the substrate. | 03-21-2013 |
20130057334 | METHOD FOR PROVIDING A SYSTEM ON CHIP WITH POWER AND BODY BIAS VOLTAGES - Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected. | 03-07-2013 |
20130049155 | PHOTOSITE WITH PINNED PHOTODIODE - A photosite is formed in a semiconductor substrate and includes a photodiode confined in a direction orthogonal to the surface of the substrate. The photodiode includes a semiconductor zone for storing charge that is formed in an upper semiconductor region having a first conductivity type and includes a main well of a second conductivity type opposite the first conductivity type and laterally pinned in a first direction parallel to the surface of the substrate. The photodiode further includes an additional semiconductor zone including an additional well having the second conductivity type that is buried under and makes contact with the main well. | 02-28-2013 |
20130027066 | TRANSISTOR TEST STRUCTURE - A test structure may characterize the properties of a transistor including a DC test structure for testing DC properties of the transistor, and an AC test structure for testing AC properties of the transistor. The DC and AC test structures may have common test pads. | 01-31-2013 |
20130026846 | TRANSFORMER OF THE BALANCED-UNBALANCED TYPE - A transformer of the balanced-unbalanced type includes a primary inductive circuit and a secondary inductive circuit housed inside an additional inductive winding connected in parallel to the terminals of the secondary circuit and inductively coupled with the primary circuit and the secondary circuit. | 01-31-2013 |
20130015910 | DEVICE FOR TRANSFERRING PHOTOGENERATED CHARGES AT HIGH FREQUENCY AND APPLICATIONSAANM Tubert; CedricAACI SassenageAACO FRAAGP Tubert; Cedric Sassenage FRAANM Roy; FrancoisAACI SeyssinsAACO FRAAGP Roy; Francois Seyssins FRAANM Mellot; PascalAACI Lans en VercorsAACO FRAAGP Mellot; Pascal Lans en Vercors FR - A device for transferring charges photogenerated in a portion of a semiconductor layer delimited by at least two parallel trenches, each trench including, lengthwise, at least a first and a second conductive regions insulated from each other and from the semiconductor layer, including the repeating of a first step of biasing of the first conductive regions to a first voltage to form a volume accumulation of holes in the area of this portion located between the first regions, while the second conductive regions are biased to a second voltage greater than the first voltage, and of a second step of biasing of the first regions to the second voltage and of the second regions to the first voltage. | 01-17-2013 |
20130009041 | PINNED PHOTODIODE CMOS IMAGE SENSOR WITH A LOW SUPPLY VOLTAGE - A device for controlling an image sensor including at least one photosensitive cell including a photodiode capable of discharging into a sense node via a first MOS transistor, the sense node being connected to the gate of a second MOS transistor having its source connected to a processing system. The device includes a bias circuit capable of increasing the voltage of the source during the discharge of the photodiode into the sense node. | 01-10-2013 |
20130003255 | INTEGRATED CAPACITIVE DEVICE AND INTEGRATED ANALOG DIGITAL CONVERTER COMPRISING SUCH A DEVICE - An integrated capacitive device includes an electrically conducting comb, at least some of whose teeth form first electrodes of capacitors, and electrically conducting fingers extending between the teeth of the comb so as to form second electrodes of the capacitors. The device includes a first finger-teeth set having a single reference finger forming a reference capacitor having a reference capacitive value, at least one second finger-teeth set including several fingers, the reference finger and the number of fingers of the second finger-teeth set or sets forming a geometric series with ratio two. At least one additional set includes a single additional finger forming, with at least one tooth of the comb, an additional capacitor having an additional capacitive value substantially equal to half the reference capacitive value. | 01-03-2013 |
20130002283 | Defect Detection by Thermal Frequency Imaging - A method can be used for detecting defects in an electronic integrated circuit that includes a power input and a data input. The electronic integrated circuit is powered with a periodic power signal having a frequency and an input signal is applied to the data input. A surface of the electronic integrated circuit is swept with a laser beam. A first image is generated using a laser beam reflected from the surface and a second image is generated using a selected part of the laser beam reflected from the surface. The selected part of the reflected laser beam has a frequency that corresponds to the frequency of the power signal. Defects in the integrated circuit can be detected by superposing the first image and the second image. | 01-03-2013 |
20120320550 | METHOD FOR ELECTRICAL CONNECTION BETWEEN ELEMENTS OF A THREE-DIMENSIONAL INTEGRATED STRUCTURE AND CORRESPONDING DEVICE - A link device for three-dimensional integrated structure may include a module having a first end face designed to be in front of a first element of the structure, and a second end face designed to be placed in front of a second element of the structure. The two end faces may be substantially parallel, and the module including a substrate having a face substantially perpendicular to the two end faces and carrying an electrically conducting pattern formed in a metallization level on top of the face and enclosed in an insulating region. The electrically conducting pattern may include a first end part emerging onto the first end face and a second end part emerging onto the second end face and connected to the first end part. | 12-20-2012 |
20120319204 | Triggerable Bidirectional Semiconductor Device - A triggerable bidirectional semiconductor device has two terminals and at least one gate. The device comprises, within a layer of silicon on insulator, a central semiconductor zone incorporating the at least one gate and comprising a central region having a first conductivity type, two intermediate regions having a second conductivity type respectively arranged on either side of and in contact with the central region, two semiconductor end zones respectively arranged on either side of the central zone, each end zone comprising two end regions having opposite types of conductivity, in contact with the adjacent intermediate region, the two end regions of each end zone being mutually connected electrically in order to form the two terminals of the device. | 12-20-2012 |
20120316813 | METHOD AND DEVICE FOR PROVIDING RELIABLE INFORMATION ABOUT THE LIFETIME OF A BATTERY - A battery powering a propulsion engine of a vehicle, is controlled by determining state data representative of the operation and wear of the battery, authenticating state data using an encryption method, and transmitting authenticated state data to an on-board computer of the vehicle for display. | 12-13-2012 |
20120315518 | METHOD AND DEVICE FOR EXTENDING THE LIFETIME OF A BATTERY IN PARTICULAR OF A VEHICLE - A method includes coupling two conducting rods between terminals of a battery cell of a battery having several branches coupled in parallel, each branch having several battery cells coupled in series. A force tending to squeeze the rods against each other is applied, with the rods being held apart from each other using an insulating block. At least one operating state signal of the cell is monitored, and the insulating block is removed based on the monitoring, allowing the rods to come into electrical contact and short-circuit the battery cell. | 12-13-2012 |
20120314813 | WIRELESS TRANSMISSION SYSTEM - A wireless data transmitter including: a data modulator adapted to modulate a data signal based on a frequency signal; and at least one antenna adapted to wirelessly transmit the modulated data signal and the frequency signal independently. | 12-13-2012 |
20120314736 | MULTI-STANDARD WIRELESS TRANSMITTER - The invention concerns a circuit for multi-standard wireless RF transmission comprising: input circuitry ( | 12-13-2012 |
20120313874 | METHOD OF MANUFACTURING A VIBRATORY ACTUATOR FOR A TOUCH PANEL WITH HAPTIC FEEDBACK - The disclosure relates to a method of manufacturing vibratory elements, comprising forming on a substrate a multilayer structure by an integrated circuit manufacturing method, the multilayer structure comprising an element susceptible of vibrating when it is subjected to an electrical signal, and electrodes for transmitting an electrical signal to the vibratory element, the vibratory element comprising a mechanical coupling face that is able to transmit to control element vibrations perceptible by a user. | 12-13-2012 |
20120313766 | METHOD OF CONTROLLING A HANDHELD OBJECT USING HAPTIC FEEDBACK - The disclosure relates to a method for controlling an object configured to be handheld and including vibratory actuators. The method including mechanically coupling a first group of at least one vibratory actuator to a first part of the object, mechanically coupling a second group of at least one vibratory actuator to a second part of the object, the first and the second parts being configured to be able to vibrate independently of each other, and to come into contact with different areas of the hand of the user holding the object, and transmitting to each group of actuators, an electrical signal having a frequency adapted to the resonance frequency of the part to which it is mechanically coupled. | 12-13-2012 |
20120308177 | PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING AT LEAST ONE COPLANAR WAVEGUIDE - An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via. | 12-06-2012 |
20120305750 | MATRIX IMAGING DEVICE COMPRISING AT LEAST ONE SET OF PHOTOSITES WITH MULTIPLE INTEGRATION TIMES - A method for controlling a pixel may include first and second photosites, each having a photodiode and a charge-transfer transistor, a read node, and an electronic read element, all of which are common to all the photosites. The method may include an accumulation of photogenerated charges in the photodiode of the first photosite during a first period, an accumulation of photogenerated charges in the photodiode of the second photosite during a second period shorter than the first period, a selection of the signal corresponding to the quantity of charges accumulated in the photodiode of a photosite having the highest unsaturated intensity or else a saturation signal, and a digitization of the selected signal. | 12-06-2012 |
20120294489 | METHOD FOR AUTOMATICALLY FOLLOWING HAND MOVEMENTS IN AN IMAGE SEQUENCE - A method for following hand movements in an image flow, includes receiving an image flow in real time, locating in each image in the received image flow a hand contour delimiting an image zone of the hand, extracting the postural characteristics from the image zone of the hand located in each image, and determining the hand movements in the image flow from the postural characteristics extracted from each image. The extraction of the postural characteristics of the hand in each image includes locating in the image zone of the hand the center of the palm of the hand by searching for a pixel of the image zone of the hand the furthest from the hand contour. | 11-22-2012 |
20120286832 | Data Synchronization Circuit - The invention concerns a circuit comprising: a first circuit block ( | 11-15-2012 |
20120286321 | High-Performance Device for Protection from Electrostatic Discharge - The semiconductor device for protection from electrostatic discharges comprises several modules (MDi) for protection from electrostatic discharges comprising triggerable elements (TRi) coupled with triggering means, the said modules being connected between two terminals by the intermediary of a resistive network (R). A common semiconductor layer contacts all of the modules, each triggerable element (TRi) having at least one gate (GHi), and the triggering means comprise a single triggering circuit (TC) common to all of the triggerable elements and whose output is connected to the gates of all of the triggerable elements. | 11-15-2012 |
20120275075 | Electrostatic Discharge Protection Device - Semiconducting device for protecting at least one node of an integrated circuit against electrostatic discharges, comprising a doublet of floating gate thyristors connected in parallel and head-to-foot, the two thyristors having respectively two distinct gates and a common gate formed by a common semiconducting layer, the anode of a first thyristor of the doublet and the cathode of the second thyristor of the doublet forming a first terminal of the doublet designed to be connected to a cold point and the cathode of the first thyristor of the doublet and the anode of the second thyristor of the doublet forming a second terminal of the doublet designed to be connected to the said node to be protected. | 11-01-2012 |
20120273952 | MICROELECTRONIC CHIP, COMPONENT CONTAINING SUCH A CHIP AND MANUFACTURING METHOD - Microelectronic chip including a semiconductor substrate; at least one area of its surface which is suitable to be electrically connected to a metal frame designed to accommodate the chip; at least one interconnect area formed by a copper-based conductive layer and comprising a connecting device, the interconnect area being connected to the area by a conductor, wherein the area is formed by a layer forming a copper diffusion barrier inserted between interconnect area and the substrate. | 11-01-2012 |
20120269206 | HIGH SPEED AND HIGH JITTER TOLERANCE DISPATCHER - A deserializer circuit includes demultiplexer circuitry configured to receive serial data from an input and output a plurality of divided data outputs, and multiplexer circuitry configured to receive a first logic level at a first input of said multiplexer circuitry, and receive a second logic level at a second input of said multiplexer circuitry and receive one of said divided data outputs at a control input of said multiplexer circuitry. The outputs of the multiplexer circuitry produce the received serial data in a parallel form. | 10-25-2012 |
20120268168 | CLOCK GATING CELL CIRCUIT - A clock gate includes a first Muller gate that receives at its inputs a clock signal and an enable signal. The output of the first Muller gate is applied, with a delayed version of the clock signal, to a second Muller gate. A logic circuit operates to logically combine the output of the second Muller gate with a delayed version of the clock signal. The output of the logic circuit provides a gated clock output. | 10-25-2012 |
20120262635 | ELEMENTARY IMAGE ACQUISITION OR DISPLAY DEVICE - An elementary image acquisition or display device, including a focusing structure with microlenses, each microlens being shaped to focus incident light beams towards a substrate while avoiding intermediate conductive tracks and vias. | 10-18-2012 |
20120261784 | METHOD FOR FORMING A BACK-SIDE ILLUMINATED IMAGE SENSOR - A method for forming a back-side illuminated image sensor from a semiconductor substrate, including the steps of: a) forming, from the front surface of the substrate, areas of same conductivity type as the substrate but of higher doping level, extending deep under the front surface, these areas being bordered with insulating regions orthogonal to the front surface; b) thinning the substrate from the rear surface to the vicinity of these areas and all the way to the insulating regions; c) partially hollowing out the insulating regions on the rear to surface side; and d) performing a laser surface anneal of the rear surface of the substrate. | 10-18-2012 |
20120261783 | BACK-SIDE ILLUMINATED IMAGE SENSOR PROVIDED WITH A TRANSPARENT ELECTRODE - A back-side illuminated image sensor formed from a thinned semiconductor substrate, wherein: a transparent conductive electrode, insulated from the substrate by an insulating layer, extends over the entire rear surface of the substrate; and conductive regions, insulated from the substrate by an insulating coating, extend perpendicularly from the front surface of the substrate to the electrode. | 10-18-2012 |
20120261732 | METHOD FOR FORMING A BACK-SIDE ILLUMINATED IMAGE SENSOR - A method for forming a back-side illuminated image sensor from a semiconductor substrate, including the steps of: a) thinning the substrate from its rear surface; b) depositing, on the rear surface of the thinned substrate, an amorphous silicon layer of same conductivity type as the substrate but of higher doping level; and c) annealing at a temperature enabling to recrystallized the amorphous silicon to stabilize it. | 10-18-2012 |
20120261670 | BACK-SIDE ILLUMINATED IMAGE SENSOR WITH A JUNCTION INSULATION - A method for forming a back-side illuminated image sensor, including the steps of: a) forming, from the front surface, doped polysilicon regions, of a conductivity type opposite to that of the substrate, extending in depth orthogonally to the front surface and emerging into the first layer; b) thinning the substrate from its rear surface to reach the polysilicon regions, while keeping a strip of the first layer; c) depositing, on the rear surface of the thinned substrate, a doped amorphous silicon layer, of a conductivity type opposite to that of the substrate; and d) annealing at a temperature capable of transforming the amorphous silicon layer into a crystallized layer. | 10-18-2012 |
20120256937 | DATA MANAGEMENT FOR IMAGE PROCESSING - A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. The coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed. | 10-11-2012 |
20120252174 | PROCESS FOR FORMING AN EPITAXIAL LAYER, IN PARTICULAR ON THE SOURCE AND DRAIN REGIONS OF FULLY-DEPLETED TRANSISTORS - A layer of a semiconductor material is epitaxially grown on a single-crystal semiconductor structure and on a polycrystalline semiconductor structure. The epitaxial layer is then etched in order to preserve a non-zero thickness of said material on the single-crystal structure and a zero thickness on the polycrystalline structure. The process of growth and etch is repeated, with the same material or with a different material in each repetition, until a stack of epitaxial layers on said single-crystal structure has reached a desired thickness. The single crystal structure is preferably a source/drain region of a transistor, and the polycrystalline structure is preferably a gate of that transistor. | 10-04-2012 |
20120248932 | METHOD OF ADJUSTING THE RESONANCE FREQUENCY OF A MICRO-MACHINED VIBRATING ELEMENT - The present disclosure relates to a method of adjusting the resonance frequency of a vibrating element, comprising measuring the resonance frequency of the vibrating element, determining, using abacuses and as a function of the resonance frequency measured, a dimension and a position of at least one area of modified thickness to be formed on the vibrating element so that the resonance frequency thereof corresponds to a setpoint frequency, and forming on the vibrating element, an area of modified thickness of the determined dimension and position. | 10-04-2012 |
20120248542 | TRANSISTOR WITH ADJUSTABLE SUPPLY AND/OR THRESHOLD VOLTAGE - The first electrode of the transistor may include a first electrically conductive region provided within the semiconductor substrate. The second electrode may include a second electrically conductive region provided within the semiconductor substrate. The first and second regions may be separated by the substrate region, and the control electrode may include a third electrically conductive region provided within the substrate. The third electrically conductive region may be both separated from the substrate region by an insulating region and electrically coupled to the substrate region by a junction diode intended to be reverse-biased. | 10-04-2012 |
20120225326 | MODULE ELEMENT, IN PARTICULAR FOR A BIOFUEL CELL, AND MANUFACTURING PROCESS - A module of a biofuel cell includes three module elements each having a porous membrane. At least two of the porous membranes are electrically conducting and form the cathode and the anode of the biofuel cell. The third membrane, which is preferably positioned between the two electrically conducting membranes need not be conducting, but defines two emergent cavities within the module. A porous through-channel extends through a silicon support of the module so as to connect one of the emergent cavities to at least one external wall of the silicon support. | 09-06-2012 |
20120217649 | DIGITAL INTEGRATED CIRCUIT - An array of functional cells includes a subset of cells powered by at least one supply rail. That supply rail is formed of first segments located on a first metallization level and second segments located on a second metallization level with at least one conductor element extending between the first and second segments to electrically connect successive segments of the supply rail. | 08-30-2012 |
20120211804 | CHARGE TRANSFER PHOTOSITE - A photosite may include, in a semi-conductor substrate, a photodiode pinched in the direction of the depth of the substrate including a charge storage zone, and a charge transfer transistor to transfer the stored charge. The charge storage zone may include a pinching in a first direction passing through the charge transfer transistor defining a constriction zone adjacent to the charge transfer transistor. | 08-23-2012 |
20120211646 | DEVICE AND METHOD FOR MEASURING LIGHT ENERGY RECEIVED BY AT LEAST ONE PHOTOSITE - A method is for measuring light energy received by a pixel including a transfer transistor, and a photodiode including a charge storage region. The method may include encapsulating the gate of the transfer transistor of the pixel in a semiconductor layer, at least one part of which includes a hydrogenated amorphous semiconductor. The method also may include grounding the charge storage region of the pixel, and determining the drift over time in the magnitude of the drain-source current of the transfer transistor. | 08-23-2012 |
20120204034 | DATA TRANSMISSION METHOD USING AN ACKNOWLEDGEMENT CODE COMPRISING HIDDEN AUTHENTICATION BITS - A method for transmitting data between a first and a second point comprises the steps of transmitting data, from the first to the second point, together with a signature comprising bits of a first authentication code, and transmitting an acknowledgement, from the second to the first point. The length of the first authentication code is greater than the length of the signature and the first authentication code comprises hidden authentication bits. The acknowledgement is produced by using hidden authentication bits of a second authentication code presumed to be identical to the first, produced at the second point. | 08-09-2012 |
20120190316 | Radio Frequency Splitter - A multichannel splitter formed from 1 to 2 splitters, wherein: an input terminal of a first 1 to 2 splitter defines an input of the multichannel splitter; the 1 to 2 splitters are electrically series-connected; and first respective outputs of the 1 to 2 splitters define output terminals of the multichannel splitter. | 07-26-2012 |
20120187519 | COOLING DEVICE FOR AN INTEGRATED CIRCUIT - A pump having: a cavity formed inside an insulating substrate, the upper part of the substrate being situated near the cavity having an edge; a conductive layer covering the inside of the cavity up to the edge and optionally covering the edge itself; a flexible membrane made of a conductive material placed above the cavity and resting against the edge; a dielectric layer covering the conductive layer or the membrane whereby insulating the portions of the conductive layer and of the membrane that are near one another; at least one aeration line formed in the insulating substrate that opens into the cavity via an opening in the conductive layer, and; terminals for applying a voltage between the conductive layer and the membrane. | 07-26-2012 |
20120182070 | OUTPUT STAGE FORMED INSIDE AND ON TOP OF AN SOI-TYPE SUBSTRATE - A method for controlling an output amplification stage comprising first and second complementary SOI-type power MOS transistors, in series between first and second power supply rails, the method including the steps of: connecting the bulk of the first transistor to the first rail when the first transistor is maintained in an off state; connecting the bulk of the second transistor to the second rail when the second transistor is maintained in an off state; and connecting the bulk of each of the transistors to the common node of said transistors, during periods when this transistor switches from an off state to an on state. | 07-19-2012 |
20120176173 | ADAPTIVE MULTI-STAGE SLACK BORROWING FOR HIGH PERFORMANCE ERROR RESILIENT COMPUTING - Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. We present a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput. | 07-12-2012 |
20120163425 | Phase-Shifting Device for Antenna Array - Device comprising processing means (MT), transmission channels (VE | 06-28-2012 |
20120161802 | DIGITAL CIRCUIT TESTABLE THROUGH TWO PINS - A method for scan-testing of an integrated circuit includes the following steps carried out by the circuit itself: upon powering on of the circuit, watching for bit sequences applied to a use pin configured for receiving serial data from the exterior at the rate of a clock signal applied to a clock pin; configuring the circuit in a test mode when a bit sequence is identified as a test initialization sequence; connecting latches of the circuit in a shift register configuration, and connecting the shift register for receiving a test vector in series from the use pin; switching the transfer direction of the use pin to the output mode for providing to the exterior serial data at the rate of the clock signal; and connecting the shift register for providing its content, as a test result set, in series on the use pin. | 06-28-2012 |
20120161269 | LOW-CROSSTALK FRONT-SIDE ILLUMINATED IMAGE SENSOR - A front-side illuminated image sensor, including photodetection regions, charge transfer elements, and an interconnection stack, all formed at the surface of a semiconductor substrate, microcavities being formed in the interconnection stack in front of the photodetection regions, microcavities being filled with materials forming color filters including metal pigments, regions of a material forming a barrier against ionic diffusion extending on the lateral walls of the microcavities. | 06-28-2012 |
20120157011 | ELECTRONIC SWITCH AND COMMUNICATION DEVICE INCLUDING SUCH A SWITCH - Switch including a terminal of a first type and at least two terminals of a second type, and a number of circuits capable of ensuring exclusive connection of one of the terminals of the second type to the terminal of the first type as a function of a set of control orders wherein the terminal of the first type is connected to a common point by a first circuit; each terminal of the second type is connected to the common point by a second circuit, with each second circuit including a portion that is magnetically coupled to the first circuit, a static switch mounted in parallel with the portion and capable of being controlled in the “off” state in order to connect the terminal of the first type to the terminal of the second type associated with the second circuit in question. | 06-21-2012 |
20120155573 | Phase Shifting Circuitry - Phase shifting circuitry is provided for phase shifting at least one of first and second quadrature components of a data signal. The circuitry includes a first phase shifter adapted to phase shift, by a first phase angle, the first quadrature component by adding together weighted versions of the first and second quadrature components. | 06-21-2012 |
20120154238 | INTEGRATED MILLIMETER WAVE TRANSCEIVER - A millimeter wave transceiver including a plate forming an interposer having its upper surface supporting an interconnection network and having its lower surface intended to be assembled on a printed circuit board by bumps; an integrated circuit chip assembled on the upper surface of the interposer; antennas made of tracks formed on the upper surface of the interposer; and reflectors on the upper surface of the printed circuit board in front of each of the antennas, the effective distance between each antenna and the reflector plate being on the order of one quarter of the wavelength, taking into account the dielectric constants of the interposed materials. | 06-21-2012 |
20120153997 | Circuit for Generating a Reference Voltage Under a Low Power Supply Voltage - A circuit for generating a reference voltage including: a first current source in series with a first bipolar transistor, between a first and a second terminal of application of a power supply voltage; a second current source in series with a second bipolar transistor and a first resistive element, between said first and second terminals, the junction point of the first resistive element and of the second bipolar transistor defining a third terminal for providing the reference voltage; a follower assembly having an input terminal connected between the first current source and the first bipolar transistor, and having an output terminal connected to a base of the second bipolar transistor; and a resistive dividing bridge between the output terminal of the follower assembly and said second terminal, the midpoint of this dividing bridge being connected to a base of the first bipolar transistor. | 06-21-2012 |
20120153422 | Imaging Device with Filtering of the Infrared Radiation - An imaging device includes at least one photosite formed in a semiconducting substrate and fitted with a filtering device for filtering at least one undesired radiation. The filtering device is buried in the semiconducting substrate at a depth depending on the wavelength of the undesired radiation. | 06-21-2012 |
20120153128 | IMAGE SENSOR WITH REDUCED OPTICAL CROSSTALK - A method of fabricating an image sensor includes the steps of: forming at least two photosites in a semiconductor substrate; forming a trench between the photosites; forming a thin liner on at least the sidewalls of the trench; depositing a conductive material having a first refractive index in the trench; and forming a region surrounded by the conductive material and having a second refractive index lower than the first index of refraction within the conductive material in the trench. | 06-21-2012 |
20120153127 | IMAGE SENSOR WITH REDUCED CROSSTALK - An image sensor having a semiconductor substrate, at least two photosites in the substrate and an isolation region between the photosites. The isolation region has a first trench covered by a thin electrically insulating liner and filled with an electrically conductive material, the conductive material has a second trench at least partially filled with an optically isolating material. | 06-21-2012 |
20120147230 | METHOD FOR CHARACTERIZING PIXELS OF AN IMAGE SENSOR - A method for characterizing image sensor pixels arranged in an array, including the steps of: (a) illuminating a first portion of the array formed of pixels associated with a color filter of a first color; (b) measuring the detection performed by a central pixel of the first portion; (c) illuminating a second portion of the array formed of a central pixel associated with a color filter of a second color and of peripheral pixels associated with a color filter of the first color; (d) measuring the detection performed by the central pixel and the peripheral pixels of the second portion; (e) comparing the measurements of steps (b) and (d). | 06-14-2012 |
20120139771 | DIFFERENTIAL SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER - A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase. | 06-07-2012 |
20120133021 | SEMICONDUCTOR DEVICE COMPRISING A CAPACITOR AND AN ELECTRICAL CONNECTION VIA, AND FABRICATION METHOD - A main blind hole is formed in a front face of a wafer having a rear face. A through capacitor is formed in the main blind hole including a conductive outer electrode, a dielectric intermediate layer, and a filling conductive material forming an inner electrode. Cylindrical portions of the outer electrode, the dielectric intermediate layer and the inner electrode have front ends situated in a plane of the front face of the wafer. A secondary rear hole is formed in the rear face of the wafer to reveal a bottom of the outer electrode. A rear electrical connection is made to contact the bottom of the outer electrode through the secondary rear hole. A through hole via filled with a conductive material is provided adjacent the through capacitor. An electrical connection is made on the rear face between the rear electrical connection and the through hole via. | 05-31-2012 |
20120133020 | SEMICONDUCTOR DEVICE COMPRISING A CAPACITOR AND AN ELECTRICAL CONNECTION VIA AND FABRICATION METHOD - A dielectric wafer has, on top of its front face, a front electrical connection including an electrical connection portion. A blind hole passes through from a rear face of the wafer to at least partially reveal a rear face of the electrical connection portion. A through capacitor is formed in the blind hole. The capacitor includes a first conductive layer covering the lateral wall and the electrical connection portion (forming an outer electrode), a dielectric intermediate layer covering the first conductive layer (forming a dielectric membrane), and a second conductive layer covering the dielectric intermediate layer (forming an inner electrode). A rear electrical connection is made to the inner electrode. | 05-31-2012 |
20120126230 | METHOD FOR MANUFACTURING A SEMICONDUCTOR CHIP STACK DEVICE - A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array. | 05-24-2012 |
20120126094 | ANALOG TO DIGITAL RAMP CONVERTER - A method of analog to digital voltage conversion including: generating a quadratic signal based on an analog time varying reference signal; generating a ramp signal based on the quadratic signal; and converting an analog input voltage to a digital output value based on a time duration determined by a comparison of the analog input voltage with the ramp signal. | 05-24-2012 |
20120120716 | SECURE NON-VOLATILE MEMORY - A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope. | 05-17-2012 |
20120119942 | RADAR WAVE TRANSMIT/RECEIVE DEVICE - Device for transmitting/receiving frequency modulated type radar waves that includes: a circuit for generating radar waves which includes a voltage-controlled oscillator coupled to a circulator which is itself connected to a transmit/receive antenna; a detection circuit including a first mixer which is fed by the circulator and the voltage-controlled oscillator, wherein voltage-controlled oscillator incluing an input for injecting a signal generated by an additional circuit, the additional circuit having its input fed by the output signal of voltage-controlled oscillator and including a second mixer which is fed by two signals generated on the basis of the output signal of voltage-controlled oscillator. | 05-17-2012 |
20120117391 | Method and System for Managing the Power Supply of a Component - A method and system for managing the power supply of a component and of a memory cooperating with the component are disclosed. The component and the memory are powered with a first variable power supply source having a first power supply voltage level greater than a minimum operating voltage of the memory. When a voltage level of the first power supply source drops and reaches a threshold that is greater than or equal to the minimum operating voltage of the memory, the power supply of the memory is toggled to a second power supply source having a second voltage level that is greater than or equal to the minimum operating voltage of the memory. | 05-10-2012 |
20120112948 | COMPACT SAR ADC - A method of successive approximation analog to digital conversion including: during a sample phase, coupling an input signal to a plurality of pairs of capacitors; and during a conversion phase, coupling a first capacitor of each pair to a first supply voltage, and a second capacitor of each pair to a second supply voltage. | 05-10-2012 |
20120106120 | TRANSMISSION LINE FOR ELECTRONIC CIRCUITS - A transmission line formed in a device including a stack of first and second chips having their front surfaces facing each other and wherein a layer of a filling material separates the front surface of the first chip from the front surface of the second chip, this line including: a conductive strip formed on the front surface side of the first chip in at least one metallization level of the first chip; and a ground plane made of a conductive material formed in at least one metallization level of the second chip. | 05-03-2012 |
20120098684 | Device and Method for Processing an Analogue Signal - Device for processing an analogue signal, comprising an analogue-digital converter with a pipelined architecture having an offset, and compensation means configured to compensate for the said offset, the said compensation means comprising digital correction means configured to correct the integer portion of the offset based on the digital signal delivered by the analogue-digital converter, and analogue correction means included in the last stage of the analogue-digital converter and configured to correct the decimal portion of the offset. | 04-26-2012 |
20120086608 | Antenna Array for Transmission/Reception Device for Signals with a Wavelength of the Microwave, Millimeter or Terahertz Type - Transmission/reception device for signals having a wavelength of the microwaves, millimeter or terahertz type, comprising an antenna array. The antenna array comprises a first group of first omni-directional antennas and a second group of second directional antennas disposed around the first group of antennas. | 04-12-2012 |
20120086091 | BACKSIDE IMAGE SENSOR - A backside image sensor including an assembly of pixels, each pixel including, in a vertical stack, a photosensitive area and a filtering element topping the photosensitive area on the back surface side, wherein at least two adjacent filtering elements of adjacent pixels are separated by a vertical metal wall extending over at least eighty percent of the height of the filtering elements or over a greater height. | 04-12-2012 |
20120081978 | READ BOOST CIRCUIT FOR MEMORY DEVICE - A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground. | 04-05-2012 |
20120074527 | INTEGRATED CIRCUIT COMPRISING A DEVICE WITH A VERTICAL MOBILE ELEMENT INTEGRATED IN A SUPPORT SUBSTRATE AND METHOD FOR PRODUCING THE DEVICE WITH A MOBILE ELEMENT - The integrated circuit comprises a support substrate having opposite first and second main surfaces. A cavity passes through the support substrate and connects the first and second main surfaces. The integrated circuit comprises a device with a mobile element, the mobile element and a pair of associated electrodes of which are included in a cavity. An anchoring node of the mobile element is located at the level of the first main surface. The integrated circuit comprises a first elementary chip arranged at the level of the first main surface and electrically connected to the device with a mobile element. | 03-29-2012 |
20120062313 | TRANSISTOR SUBSTRATE DYNAMIC BIASING CIRCUIT - A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage. | 03-15-2012 |
20120062288 | Device and Method for Generating a Signal of Parametrizable Frequency - Device for generating a signal of parametrizable frequency comprising a phase locked loop including a generator of a reference signal, a phase-frequency comparator comprising a first input for receiving the reference signal, an oscillator controlled on the basis of the result output by the phase-frequency comparator, a fractional divider coupled between an output of the oscillator and a second input of the phase-frequency comparator, and a selector selectively linking an input of the oscillator either with an input of the generator, or with the output of the oscillator as a function of the multiplication ratio of the fractional divider. | 03-15-2012 |
20120042292 | METHOD OF SYNTHESIS OF AN ELECTRONIC CIRCUIT - A method of synthesis of at least one logic device coupled between first and second supply voltages and having a plurality of inputs and an output, the logic device including a plurality of transistors having a standard gate length, the method including: identifying, in the at least one logic device, one or more transistors connected between the first or second supply voltage and the output node; and increasing the gate length of each of the identified one or more transistors. | 02-16-2012 |
20120032291 | Stand-Alone Device - A stand-alone device comprising a silicon wafer having its front surface including a first layer of a first conductivity type and a second layer of a second conductivity type forming a photovoltaic cell; first vias crossing the wafer from the rear surface of the first layer and second vias crossing the wafer from the rear surface of the second layer; metallization levels on the rear surface of the wafer, the external level of these metallization levels defining contact pads; an antenna formed in one of the metallization levels; and one or several chips assembled on said pads; the metallization levels being shaped to provide selected interconnects between the different elements of the device. | 02-09-2012 |
20120018619 | Method of Resetting a Photosite, and Corresponding Photosite - A method of resetting a photosite is disclosed. Photogenerated charges accumulated in the photosite are reset by recombining the photogenerated charges with charges of opposite polarity. | 01-26-2012 |
20120012891 | VOLTAGE-CONTROLLED BIDIRECTIONAL SWITCH - A voltage-controlled vertical bi-directional monolithic switch, referenced with respect to the rear surface of the switch, formed from a lightly-doped N-type semiconductor substrate, in which the control structure includes, on the front surface side, a first P-type well in which is formed an N-type region, and a second P-type well in which is formed a MOS transistor, the first P-type well and the gate of the MOS transistor being connected to a control terminal, said N-type region being connected to a main terminal of the MOS transistor, and the second main terminal of the MOS transistor being connected to the rear surface voltage of the switch. | 01-19-2012 |
20120007686 | MULTIBAND VOLTAGE CONTROLLED OSCILLATOR WITHOUT SWITCHED CAPACITOR - A controlled oscillator includes, connected in parallel, a capacitor configured to be tuneable based upon a first signal, an inductor, and an active impedance. The active impedance is formed by a pair of cross-coupled transistors connected so as to produce a negative resistive component at the terminals of the active impedance. Circuitry produces a degeneracy tuneable by a second signal in the cross-coupled pair, such that the cross-coupled pair produces a capacitive component tuneable based upon the second signal at the terminals of the active impedance. | 01-12-2012 |
20120007201 | MONOLITHIC PHOTODETECTOR - A photodetector including a photodiode formed in a semiconductor substrate and a waveguide element formed of a block of a high-index material extending above the photodiode in a thick layer of a dielectric superposed to the substrate, the thick layer being at least as a majority formed of silicon oxide and the block being formed of a polymer of the general formula R | 01-12-2012 |
20120006980 | PHOTOSENSITIVE INTEGRATED CIRCUIT EQUIPPED WITH A REFLECTIVE LAYER AND CORRESPONDING METHOD OF PRODUCTION - A method for producing a photosensitive integrated circuit including producing circuit control transistors, producing, above the control transistors, and between at least one upper electrode and at least one lower electrode, at least one photodiode, by amorphous silicon layers into which photons from incident electromagnetic radiation are absorbed, producing at least one passivation layer, between the lower electrode and the control transistors, and producing, between the control transistors and the external surface of the integrated circuit, a reflective layer capable of reflecting photons not absorbed by the amorphous silicon layers. | 01-12-2012 |
20120004016 | FILTERING CIRCUIT WITH COUPLED BAW RESONATORS AND HAVING IMPEDANCE MATCHING ADAPTATION - A filtering circuit includes a substrate; an acoustic mirror or a membrane destined to act as a mechanical support of acoustic resonators and to isolate these resonators from the substrate; a first section comprising an upper resonator and a lower resonator coupled to each other by at least one acoustic coupling layer; and a second section comprising an upper resonator and a lower resonator coupled to each other by at least one acoustic coupling layer. The filtering circuit also includes metallic vias implementing an inter stage connection between the lower resonator of a section and the upper resonator of the other section. Preferably, the upper resonators exhibit a piezoelectric layer having a thickness selected in order to achieve an optimal impedance matching between the said first and second sections. | 01-05-2012 |
20120001665 | FRACTIONAL FREQUENCY DIVIDER - A fractional frequency divider including a frequency division unit for generating a reduced frequency timing signal having j pulses for every k pulses of an original timing signal, wherein j and k are each integers; and phase correction circuitry adapted to selectively shift each jth pulse of the reduced frequency timing signal by a first fixed time period. | 01-05-2012 |
20110316587 | Bistable CML Circuit - A common-source circuit including two branches in parallel between a terminal of application of a voltage and a current source, each branch comprising: a series association of a resistor and a transistor, having their junction point defining an output terminal of the branch; a first switch connecting an input terminal of the branch to a control terminal of the transistor; and a controllable stage for amplifying data representing the level present on the output terminal of the opposite branch. | 12-29-2011 |
20110298554 | METHOD OF ADJUSTMENT DURING MANUFACTURE OF A CIRCUIT HAVING A CAPACITOR - A method of adjustment during manufacture of a capacitance of a capacitor supported by a substrate, the method including the steps of: a) forming a first electrode parallel to the surface of the substrate and covering it with a dielectric layer; b) forming, on a first portion of the dielectric layer, a second electrode; c) measuring the electrical signal between the first electrode and the second electrode, and deducing therefrom the capacitance to be added to obtain the desired capacitance; d) thinning down a second portion of the dielectric layer, which is not covered by the second electrode, so that the thickness of this second portion is adapted to the forming of the deduced capacitance; and e) forming a third electrode on the thinned-down portion and connecting it to the second electrode. | 12-08-2011 |
20110298491 | Dual-Edge Register and the Monitoring Thereof on the Basis of a Clock - Sequential electronic circuit ( | 12-08-2011 |
20110298010 | Cell Library, Integrated Circuit, and Methods of Making Same - A cell library intended to be used to form an integrated circuit, this library defining a first cell including a first MOS transistor of minimum dimensions, and a second cell including a second MOS transistor of lower leakage current, wherein the second cell takes up the same surface area as the first cell, and the second MOS transistor has a gate of same length as the gate of the first MOS transistor across at least a first width in its central portion, and of greater length across at least a second width on either side of the central portion. | 12-08-2011 |
20110293015 | METHOD AND DEVICE FOR IMAGE INTERPOLATION SYSTEMS BASED ON MOTION ESTIMATION AND COMPENSATION - A motion estimation method and device are provided for processing images to be inserted, between a preceding original image and a following original image, into a sequence of images. Each image is divided into pixel blocks associated with motion vectors. For a current block of an image being processed, motion vectors associated with blocks of the image being processed and/or associated with blocks of a processed image are selected. Candidate vectors are generated from selected motion vectors. An error is calculated for each candidate vector. A penalty is determined for a subset of candidate vectors on the basis of the values of the pixels of the pixel block in the preceding original image from which the candidate motion vector points to the current block and/or on the basis of the values of the pixels of the pixel block in the following original image to which the candidate motion vector points from the current block. | 12-01-2011 |