Texas Instruments Deutschland GmbH Patent applications |
Patent application number | Title | Published |
20160048396 | CENTRAL PROCESSOR-COPROCESSOR SYNCHRONIZATION - An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register. | 02-18-2016 |
20150381137 | ADAPTIVE SYSTEM CONTROLLED POWER SUPPLY TRANSIENT FILTER - An electronic device that includes a power on reset, a variable power supply filter coupled to the power on reset, and control logic coupled to the power on reset and the variable power supply filter. The control logic is configured to activate the variable power supply filter based on a core domain of the electronic device being active. | 12-31-2015 |
20150378374 | PROGRAMMABLE SUPPLY DOMAIN PULLDOWN - A power gated electronic device that includes a power supply domain coupled to a power gate switch, a comparator, and control logic. The power supply domain is configured to receive voltage from a power supply. The comparator is configured to receive voltage from the power supply domain and compare the voltage from the power supply domain with a threshold level. The control logic is configured to receive the output of the comparator and, based on the comparison between the voltage from the power supply domain and the threshold level, cause the power supply domain to pulldown. | 12-31-2015 |
20150333502 | SHORT-CIRCUIT PROTECTION SYSTEM FOR POWER CONVERTERS - One example includes a power converter system. The system includes a switching circuit configured to activate at least one power supply switch in response to a driver signal to provide an output voltage at an output based on an input voltage at an input and based on an inductor current associated with an inductor. The at least one power supply switch includes a parasitic diode that interconnects the inductor and the output. The system also includes a short-circuit protection system configured to detect a short-circuit condition and to deactivate the at least one power supply switch in response to the detection of the short-circuit condition to provide the inductor current from the inductor to the output through the parasitic diode in response to the deactivation of the at least one power supply switch. | 11-19-2015 |
20150309088 | VERIFICATION OF BANDGAP REFERENCE STARTUP - A bandgap reference (BGR) startup verification circuit includes a current minor for receiving an output current from a bandgap reference (BGR) circuit and generating output currents therefrom. A first verification sub-circuit is coupled to receive a first output current to generate a detection voltage (Vdet) and includes a voltage comparator receiving Vdet and a voltage output of the BGR circuit (VBG) to provide a first verification output. A second verification sub-circuit including a voltage comparator is coupled to receive a second output current and a second reference current and provide a second verification output. A third verification sub-circuit includes a current comparator coupled to receive a third output current and a third reference current and provide a third verification output. A digital state machine has inputs receiving the first, second and third verification output, and circuitry for processing these outputs to determine whether the BGR circuit has properly started. | 10-29-2015 |
20150301915 | PROCESSOR WITH DEBUG PIPELINE - A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline. | 10-22-2015 |
20150301830 | PROCESSOR WITH VARIABLE PRE-FETCH THRESHOLD - A method and apparatus for controlling pre-fetching in a processor. A processor includes an execution pipeline and an instruction pre-fetch unit. The execution pipeline is configured to execute instructions. The instruction pre-fetch unit is coupled to the execution pipeline. The instruction pre-fetch unit includes instruction storage to store pre-fetched instructions, and pre-fetch control logic. The pre-fetch control logic is configured to fetch instructions from memory and store the fetched instructions in the instruction storage. The pre-fetch control logic is also configured to provide instructions stored in the instruction storage to the execution pipeline for execution. The pre-fetch control logic is further configured set a maximum number of instruction words to be pre-fetched for execution subsequent to execution of an instruction currently being executed in the instruction pipeline. The maximum number is based on a value contained in a pre-fetch threshold field of an instruction executed in the execution pipeline. | 10-22-2015 |
20150286236 | Bandgap Reference Voltage Failure Detection - An integrated circuit is provided with a bandgap voltage reference circuit having a bandgap reference voltage output. A bandgap failure detection circuit is coupled to the bandgap reference voltage output. The bandgap failure detection forms a model value of the reference voltage from a first time, compares a present value of the reference voltage at a second time to the model value; and asserts a bandgap fail signal to indicate when the present value is less than the model value by a threshold value. The integrated circuit is reset by the bandgap fail signal. The detection circuit may be operated from a failsafe voltage domain that also allows a critical circuit to complete a pending operation during a reset. | 10-08-2015 |
20150286231 | Control for Voltage Regulators - A mixed signal approach is applied to detect an output voltage condition as applied to a load. A current mode monitoring approach can be adopted and applied in discrete time using a mixed analog and digital approach. For application to various low drop-out voltage regulator situations, a sensing transistor can be connected in parallel with a feedback loop transistor of the low drop-out voltage regulator circuit to create a sensing current that is proportional to the current passing through the feedback loop transistor and thus the output current provided to the load. This sensing approach can be adapted to sense both overload and light load conditions to allow dynamic power control of the device. | 10-08-2015 |
20150271913 | ELECTRONIC DEVICE PACKAGE WITH VERTICALLY INTEGRATED CAPACITORS - A system-in-a-package (SIP) has a semiconductor chip embedded in a dielectric substrate. An inductor is on a top surface of a substrate and is connected to the semiconductor chip. A thin film capacitor may be placed between the inductor and the dielectric substrate. A second thin film capacitor may be placed on the top surface of the semiconductor chip, or be embedded in the dielectric substrate with a thermal pad on a bottom surface of the substrate which is connected to the second thin film capacitor to facilitate heat dissipation. | 09-24-2015 |
20150222268 | CONFIGURABLE ANALOG FRONT ENDS FOR CIRCUITS WITH SUBSTANTIALLY GATE ENCLOSED INNER ELECTRODE MOSFET SWITCH - A configurable integrated circuit (IC) includes a substrate having a semiconductor surface that the IC is formed within and thereon. The IC includes a configurable Analog Front End (cAFE) including at least one circuit module or input/output (IO), an analog switch having at least a first substantially gate enclosed Metal Oxide Semiconductor Field Effect Transistor (SGEFET) having a gate stack including a gate on a gate dielectric, a source, and a drain. The drain or source is a substantially gate enclosed (SGE) inner electrode relative to the gate, and the other of the source and the drain is outside the gate. The inner electrode of the first SGEFET is directly coupled to an analog bus. A switch control provides control signals to at least the gate of the first SGEFET for controlling a connectivity between the circuit module and/or the IO and the analog bus. | 08-06-2015 |
20150212820 | PROCESSOR LOOP BUFFER - A method and apparatus for executing program loops. A processor, includes an execution unit and an instruction fetch buffer. The execution unit is configured to execute instructions. The instruction fetch buffer is configured to store instructions for execution by the execution unit. The instruction fetch buffer includes a loop buffer configured to store instructions of an instruction loop for repeated execution by the execution unit. The loop buffer includes buffer control logic. The buffer control logic includes pointers, and is configured to predecode a loop jump instruction, identify loop start and loop end instructions using the predecoded loop jump instruction and pointers; and to control non-sequential instruction execution of the instruction loop. The width of the pointers is determined by loop buffer length and is less than a width of an address bus for fetching the instructions stored in the loop buffer from an instruction memory. | 07-30-2015 |
20150205613 | EFFICIENT CENTRAL PROCESSING UNIT (CPU) RETURN ADDRESS AND INSTRUCTION CACHE - A processor includes an instruction fetch unit and an instruction decode unit. The instruction fetch unit includes an instruction pre-fetch buffer and is configured to fetch instructions from memory into the instruction pre-fetch buffer. The instruction decode unit is coupled to the instruction pre-fetch buffer and upon decoding a call instruction from the instruction pre-fetch buffer, causes next N instruction words of the instruction pre-fetch buffer to be preserved for execution after completing execution of a software module indicated by the call instruction, and causes the instruction fetch unit to begin fetching instructions of the software module from the memory at an address indicated by the call instruction. Upon completion of execution of the software module, the instruction decode unit begins to decode the preserved N instruction words while the instruction fetch unit concurrently fetches instruction words from beginning at an address after the N instruction words. | 07-23-2015 |
20150177326 | Waveform Calibration Using Built In Self Test Mechanism - A system on a chip (SoC) includes a transceiver comprising a transmitter having a power amplifier and a receiver having a signal buffer. At least one of the transmitter and receiver has a configurable portion that can be configured to produce a range of waveforms (both in waveshape as well as duty cycle). A low cost built in self test (BIST) logic is coupled to the transceiver. The BIST logic is operable to calibrate the configurable portion of the transceiver to produce a waveform that has a selected harmonic component that has an amplitude that is less than a threshold value. Current consumed by the transceiver may be dynamically reduced by selecting an optimized waveform that has low harmonic components. | 06-25-2015 |
20150123638 | STARTUP CLAMP CIRCUIT FOR NON-COMPLIMENTARY DIFFERENTIAL PAIR IN DCDC CONVERTER SYSTEM - A DCDC converter includes a transconductance amplifier, a comparator, a current driving component, an output impedance, a switch, a clamp resistor and a p-channel FET. The transconductance amplifier outputs a transconductance current and a switch control signal. The comparator has a two n-channel FET inputs forming a differential pair and outputs a compared signal. The current driving component generates an output current based on the compared signal. The output impedance component generates an output DC voltage based on the output current. The switch is between the two n-channel FETs and can open and close based on the switch control signal. The clamp resistor is arranged in series with the switch. The p-channel FET is in series with the clamp resistor and is controlled by the output DC voltage. | 05-07-2015 |
20150100759 | PIPELINED FINITE STATE MACHINE - A system and method for controlling operation of a pipeline. In one embodiment, a pipelined datapath includes a plurality of processing stages and a pipeline controller. Each of the processing stages is configured to further processing provided by a previous one of the processing stages. The pipeline controller is configured to control operation of the processing stages. The pipeline controller includes a pipelined finite state machine. The pipelined finite state machine includes a plurality of control stages. Each of the control stages is configured to control operation of a single one of the processing stages, and to receive a state value that defines a state of the control stage for controlling the single one of the processing stages from a previous control stage. | 04-09-2015 |
20150070081 | SYSTEM AND METHOD FOR REDUCTION OF BOTTOM PLATE PARASITIC CAPACITANCE IN CHARGE PUMPS - A system for providing a load current at a specific output voltage to a circuit block of an integrated circuit (IC) includes a supply node at a supply voltage, a charge pump, and a cross-coupling circuit. The charge pump includes a first a first capacitor to charge while a first clock signal is high and a second capacitor to charge while a second clock signal is high. Each of the capacitors has a top plate node, a bottom plate node, a ground node, and an intermediate node between the bottom plate node and the ground node. The cross-coupling circuit couples the intermediate node of the first capacitor to the supply node while the second clock signal is high and couples the intermediate node of the second capacitor to the supply node while the first clock signal is high. | 03-12-2015 |
20150070080 | SYSTEM AND METHOD FOR DISTRIBUTED REGULATION OF CHARGE PUMPS - A system for providing a load current at a specific voltage to a circuit block of an integrated circuit (IC) includes a plurality of charge pumps and a control circuit to generate a control signal for each of the charge pumps. The control signal causes each of the charge pumps to be enabled, partially enabled, or disabled, and controls at least one of the charge pumps independently of the other charge pumps. | 03-12-2015 |
20150061103 | EMBEDDED DIE PACKAGE - A method of making an electrical assembly includes making a laminate substrate, embedding a plurality of integrated circuit dies in the laminate substrate, forming a plurality of through-holes in the laminate substrate and adding conductive material to the through-holes, and making at least one saw cut extending through the laminate substrate and through the plurality of through-holes and the conductive material therein to form at least one laminate block with a cut face and a plurality of sectioned through-holes. | 03-05-2015 |
20150058602 | PROCESSOR WITH ADAPTIVE PIPELINE LENGTH - A system and method for reducing pipeline latency. In one embodiment, a processing system includes a processing pipeline. The processing pipeline includes a plurality of processing stages. Each stage is configured to further processing provided by a previous stage. A first of the stages is configured to perform a first function in a pipeline cycle. A second of the stages is disposed downstream of the first of the stages, and is configured to perform, in a pipeline cycle, a second function that is different from the first function. The first of the stages is further configured to selectably perform the first function and the second function in a pipeline cycle, and bypass the second of the stages. | 02-26-2015 |
20150058391 | PROCESSOR WITH EFFICIENT ARITHMETIC UNITS - A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier. | 02-26-2015 |
20150053770 | RFID TAG WITH INTEGRATED ANTENNA - A radio frequency identification (RFID) tag. In one embodiment, an RFID tag includes an integrated circuit die. The integrated circuit die includes circuitry configured to store information and transmit the stored information responsive to reception of a radio frequency (RF) signal. The integrated circuit die also includes an antenna coupled to the circuitry. The antenna is configured to transmit and receive RFID signals. Further, the antenna and the interconnects of the circuitry are formed of a same metal, and fabricated using a same semiconductor process. | 02-26-2015 |
20150048820 | FLUXGATE MAGNETIC SENSOR READOUT APPARATUS - Compact, low power fluxgate magnetic sensor readout circuits and apparatus are presented in which demodulator or rectifier circuit to modulates a sense signal from the fluxgate sense coil, and the demodulated signal is provided to an amplifier circuit with a transconductance or other amplifier and one or more feedback capacitors connected between the amplifier input and amplifier output to integrate the amplifier output current and provide a voltage output signal indicating the magnetic field sensed by the fluxgate sensor. | 02-19-2015 |
20150048818 | INTEGRATED FLUXGATE MAGNETIC SENSOR AND EXCITATION CIRCUITRY - Improved magnetic sensor excitation circuitry is presented for providing a periodic bidirectional excitation waveform to a fluxgate magnetic sensor excitation coil using a bridge circuit connected to the excitation coil and having lower transistors for switched selective connection to a current mirror input transistor to mirror a current provided by pulsed current source, and with integrated filtering to control pulse rise times and slew rate. | 02-19-2015 |
20150042325 | HYBRID CLOSED-LOOP/OPEN-LOOP MAGNETIC CURRENT SENSOR - Hybrid magnetic current sensors and sensing apparatus are presented with closed-loop and open-loop circuitry employs first and second integrated magnetic sensors to sense a magnetic field in a magnetic core structure gap to provide high accuracy current measurement via a closed-loop magnetic circuit with the first sensor in a nominal current range as well as open-loop current measurement using the second sensor in an extended second range to accommodate over-current conditions in a host system as well as to provide redundant current sensing functionality. | 02-12-2015 |
20150016006 | METHOD AND APPARATUS FOR DEMAGNETIZING TRANSFORMER CORES IN CLOSED LOOP MAGNETIC CURRENT SENSORS - Automated degaussing methods and apparatus are presented for degaussing a magnetic core in close loop fashion, in which a plurality of pulses are applied to a compensation coil magnetically coupled with the core with duration or energy being decreased in succeeding pulse cycles according to a discrete feedback algorithm, and with individual pulse polarities being set according to core magnetization polarity measured subsequent to an immediately preceding pulse. | 01-15-2015 |
20140372729 | PROCESSOR WITH EXECUTION UNIT WAIT CONTROL - A processor includes a processor core. The processor core includes a first execution unit and a second execution unit. The first execution unit is configured to 1) execute a complex instruction that requires multiple instruction cycles to execute; 2) generate a wait signal that when asserted suspends execution of instructions by the second execution unit for at least a portion of the execution of the complex instruction; and 3) maintain information defining parameters of the wait signal generation across interruption of the complex instruction by execution of a different instruction in the first execution unit. | 12-18-2014 |
20140306760 | APPARATUS AND METHOD FOR TRANSIMPEDANCE AMPLIFIERS WITH WIDE INPUT CURRENT RANGES - Improved preamplifier circuits for converting single-ended input current signals to differential output voltage signals, including first and second transimpedance amplifiers with input transistors operating according to bias currents from a biasing circuit, output transistors and adjustable feedback impedances modified using an automatic gain control circuit, as well as a reference circuit controlling the bias currents according to an on-board reference current and the single-ended input or the differential output voltage signals from the transimpedance amplifiers. | 10-16-2014 |
20140292356 | METHOD AND SYSTEM FOR DETERMINING PROXIMITY OF AN OBJECT - A first sensor detects whether an object is within a first region that surrounds the first sensor. A second sensor detects whether the object is within a second region that surrounds the second sensor. The first and second sensors are omnidirectional capacitive electrodes. In response to the first sensor detecting that the object is not within the first region, a device determines that the object is not proximate to a particular side of the first and second sensors. In response to the first sensor detecting that the object is within the first region, and the second sensor detecting that the object is within the second region, the device determines that the object is not proximate to the particular side. In response to the first sensor detecting that the object is within the first region, yet the second sensor detecting that the object is not within the second region, the device determines that the object is proximate to the particular side. | 10-02-2014 |
20140292293 | VOLTAGE REGULATOR - A voltage regulator for providing power to a system includes feedforward circuitry receiving a signal from the system indicating the current needed by the system, and the feedforward circuitry causes the voltage regulator to change the voltage regulator output current in response to the signal from the system. | 10-02-2014 |
20140266319 | CAPACITIVE HIGH PASS PRE-EMPHASIS CIRCUIT - Some aspects of the disclosure are directed to a transmission circuit that includes a main driver. The transmission circuit also includes a plurality of capacitive modules connected in parallel to the main driver. A controller also is included that is coupled to the plurality of capacitive modules. The controller selectively enables and disables each capacitive module to implement a target amount of pre-emphasis. | 09-18-2014 |
20140239449 | THREE PRECISION RESISTORS OF DIFFERENT SHEET RESISTANCE AT SAME LEVEL - An integrated circuit contains three thin film resistors over a dielectric layer. The first resistor body includes only a bottom thin film layer and the first resistor heads include the bottom thin film layer, a middle thin film layer and a top thin film layer. The second resistor body and heads include all three thin film layers. The third resistor body does not include the middle thin film layer. The three resistors are formed using two etch masks. | 08-28-2014 |
20140218018 | APPARATUS AND METHOD FOR IN SITU CURRENT MEASUREMENT IN A CONDUCTOR - Improved current sensing methods and apparatus and conductor apparatus are presented for sensing current in a bus bar or other conductor using one or more circular magnetic sensors or multiple magnetic sensors disposed on a substrate in a pattern surrounding a longitudinal path within the outer periphery of the conductor to avoid or mitigate sensed magnetic field crosstalk and to facilitate use of high sensitivity magnetic sensors at locations inside the conductor periphery in which the magnetic field is relatively small. | 08-07-2014 |
20140210529 | Phase Locked Loop and Method for Operating the Same - The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response. | 07-31-2014 |
20140189367 | DIGITAL-ENCRYPTION HARDWARE ACCELERATOR - An electronic device for encrypting and decrypting data blocks of a message having n data blocks in accordance with the data encryption standard (DES) has a first data processing channel having a first processing stage for performing encryption and decryption of data blocks of a predefined length, and a second data processing channel having a second processing stage for performing encryption and decryption of data blocks. The electronic device also has a control stage (FSM) for controlling the first processing stage and the second processing stage, so as to perform an encryption or decryption step with the second processing stage on an encrypted/decrypted data block output from the first processing stage, and to control the second processing stage to compute a message authentication code over the encrypted or decrypted message received from the first processing stage block-by-block. | 07-03-2014 |
20140111280 | ELECTRONIC DEVICE, FIBER-OPTIC COMMUNICATION SYSTEM COMPRISING THE ELECTRONIC DEVICE AND METHOD OF OPERATING THE ELECTRONIC DEVICE - An electronic device, a fiber-optic communication system comprising the electronic device and a method of operating the electronic device are provided. The electronic device comprises a transimpedance-type amplifier having a transimpedance stage comprising an amplifier which is coupled in series with an input node. A feedback resistor is coupled in series between an output node of the amplifier and an inverting input node of the amplifier to provide a virtual ground node which is coupled to the input node, the inverting input node of the amplifier and to the feedback resistor. A current source is coupled to the virtual ground node so as to compensate for an offset current in an input signal which is coupled to the input node of the electronic device. Further, the electronic device comprises a control stage which is configured to control the current source as a function of a current through the feedback transistor. | 04-24-2014 |
20140103489 | Electronic Device Comprising a Semiconductor Structure Having an Integrated Circuit Back End Capacitor and Thin Film Resistor and Method of Manufacturing the Same - An electronic device comprising a semiconductor structure having an integrated circuit back end capacitor and an integrated circuit back end thin film resistor and a method of manufacturing the same is provided. The semiconductor structure comprises a first dielectric layer, a bottom plate of the capacitor and a thin film resistor body. Furthermore, there is a second dielectric layer which is disposed on the bottom plate of the capacitor and on top of the thin film resistor body. A top plate of the capacitor is disposed on the second dielectric layer in a region of the second dielectric layer which is defined by the lateral dimensions of the bottom plate of the capacitor. The bottom plate and the resistor body are laterally spaced apart layers which are both disposed on the first dielectric layer and which are composed of a same thin film material. | 04-17-2014 |
20140084912 | HALL SENSOR EXCITATION SYSTEM - A Hall plate excitation system provides reduced offset and temperature dependence. The Hall plate excitation system includes a current source, a switching network, and a controller. The current source is configured to provide an excitation current to a Hall plate. The switching network is configured to switchably connect the current source to each of a plurality of terminals of the Hall plate. The controller is configured to adjust the excitation current no more than once during each spinning cycle; and to sequentially switch the excitation current to each of the plurality of terminals of the Hall plate during each spinning cycle. | 03-27-2014 |
20130335156 | OSCILLATOR COMPRISING AN RC-CIRCUIT AND A PUSH-PULL STAGE AND ELECTRONIC DEVICE COMPRISING THE OSCILLATOR - Oscillator and electronic device comprising an oscillator, wherein the oscillator has an RC-circuit and a push-pull stage. A tapping point of the RC-circuit is coupled to an input of the push-pull stage and an output of the push-pull stage is fed back to a switching transistor which is coupled to the tapping point of the RC-circuit. | 12-19-2013 |
20130320949 | ELECTRONIC DEVICE FOR AVERAGE CURRENT MODE DC-DC CONVERSION - An average current mode buck-boost DC to DC converter has a buck stage coupled between an input voltage source terminal and an output terminal. A boost stage is coupled between the input voltage source terminal and the output terminal. A current ramp control circuit generates a ramp signal for driving the buck and boost stages, the ramp signals being coupled to the buck and boost stages. A constant voltage related to the desired output voltage by a constant is applied directly to both a voltage control feedback loop for adjusting the output voltage and directly to an input to the current ramp control circuit, whereby the output voltage can be shifted from one voltage to another by feedforward control. | 12-05-2013 |
20130314067 | LOW POWER DC-DC CONVERTER AND METHOD OF OPERATING THE SAME - A low power DC-DC converter includes a converter stage coupled to an input node, and having a low side switch and a rectifier switch. A peak current detector senses a current at the low side switch and a zero current detector senses a current at the rectifier switch. It is configured to set the low side switch to a non-conductive state and the rectifier switch to a conductive state if the peak current detector detects a predetermined peak current. It is configured to set the rectifier switch to a non-conductive state if the zero current detector detects zero current at the rectifier switch. A time interval between subsequent current peaks is triggered by a charge comparator receiving an average current fed to the low side and rectifier switches from the input node and a reference current coupled to the charge comparator by a reference current source. | 11-28-2013 |
20130271185 | ELECTRONIC DEVICE AND METHOD FOR LOW LEAKAGE SWITCHING - The invention relates to a low leakage switch having an input node for receiving an input voltage and an output node for providing an output voltage. The low leakage switch comprises a main sampling transistor the backgate voltage of which is biased through other transistors, and wherein the control gate of the main sampling transistor is controlled through a second control signal and the control gates of the other transistors are controlled through a first control signal, wherein the electronic device is further configured to activate the other transistor for adjusting the backgate voltage of the main sampling transistor through the first control signal before activating the main sampling transistor for sampling the input voltage on a main sampling capacitor through the second control signal. | 10-17-2013 |
20130249056 | METHOD AND ELECTRONIC DEVICE FOR A SIMPLIFIED INTEGRATION OF HIGH PRECISION THINFILM RESISTORS - The invention relates to a method of manufacturing an integrated circuit. An electrically resistive layer of a material for serving as a thin film resistor (TFR) is deposited. A first electrically insulating layer is deposited on the electrically resistive layer of the TFR. An electrically conductive layer of an electrically conductive material is deposited. An area is left without the conductive layer and the area overlaps the electrically resistive layer of the TFR. A second electrically insulating layer is deposited on top of the conductive layer. A first VIA opening is etched through the second insulating layer, the area without the conductive layer adjacent to the electrically conductive layer and through the first insulating layer down to the electrically resistive layer of the TFR. A conductive material is deposited in the first VIA opening so as to electrically connect the conductive layer and the electrically resistive layer of the TFR. | 09-26-2013 |
20130234513 | SINGLE INDUCTOR-MULTIPLE OUTPUT DC-DC CONVERTER, METHOD FOR OPERATING THE SAME AND ELECTRONIC DEVICE COMPRISING THE CONVERTER - Single inductor-multiple output (SIMO) DC-DC converter, having an output node which is coupled to one side of the single inductor to receive a load current. A plurality of output switches which are coupled to the output node for switching the load current from the output node to a plurality of output lines is provided. Each output line has a load capacitor. Further, each output line may comprise a charge pump which is coupled to the output switch and the load capacitor of the output line. | 09-12-2013 |
20130201583 | ELECTRONIC DEVICE AND METHOD FOR PROTECTING AGAINST DAMAGE BY ELECTROSTATIC DISCHARGE - An electronic device with a protective circuit against damage by electrostatic discharge includes a discharge current path connectable between an input to be protected and a ground pin. An enabling circuit outputs a control signal for connecting the discharge current path in the event of an electrostatic discharge. A deactivating circuit which deactivates the enabling circuit during operation of the electronic device is controlled by the inverted control signal. A method of protecting an electronic device against damage by electrostatic discharge includes providing a control signal for connecting a discharge current path between an input to be protected and a ground pin in the event of an electrostatic discharge. An inverted control signal is applied to the inverted control signal to a deactivating circuit. The inverted control signal prevents connection of the discharge current path between the input to be protected and ground during operation of the electronic device. | 08-08-2013 |
20130173868 | Generation of Activation List for Memory Translation and Memory Access Protection in Industrial Ethernet Standard - The invention relates to an EtherCAT fieldbus system, a master and a slave for the system and a method. The slave is configured to be coupled to the EtherCAT fieldbus. A first configurable memory of the slave stores a first activation list indicating for consecutive bytes of data of an EtherCAT datagram a corresponding fieldbus memory management information or synchronization management information. | 07-04-2013 |
20130113540 | ELECTRONIC DEVICE AND METHOD FOR PROVIDING A DIGITAL SIGNAL AT A LEVEL SHIFTER OUTPUT - An electronic device comprising a level shifter and a method. The level shifter includes an input adapted to receive an input signal switching between a low input voltage level and a high input voltage level and a first switch and a second switch coupled in series between a low output voltage supply and a high output voltage supply. An output is coupled to an interconnection node between the first and the second switch and is adapted to be coupled to a load. The first and second switches are controlled by the input signal. The level shifter further includes a third switch which is coupled between the interconnection node and an auxiliary voltage supply which has a voltage level between the low output voltage level and the high output voltage level. | 05-09-2013 |
20130063113 | LOAD CURRENT SENSING CIRCUIT AND METHOD - A load current sensing circuit for sensing a DC-DC converter load current in a DC-DC converter comprising a high-side power transistor and a low-side power transistor connected in series between supply terminals and having a converter switching node therebetween coupled to an inductor to which a load is to be coupled. A first averaging stage determines a DC voltage component of the PWM signal and a second averaging stage determines a DC component of the voltage signal at the converter switching node. A comparison stage determines a difference voltage between the first averaging stage and the second averaging stage. An impedance replica stage forms a resistance which is proportional to the resistance of the series-connected power transistors. A measuring stage measures a current flowing through the impedance replica stage with the determined difference voltage applied. | 03-14-2013 |
20130063104 | ELECTRONIC DEVICE AND METHOD FOR DC-DC CONVERSION WITH LOW POWER MODE - The invention relates to an electronic device and a method for DC-DC-conversion. The electronic device includes energizing switch and a commutating switch coupled at a switching node. The switching node is configured to be coupled to an inductor. The electronic device is configured to repeatedly suspend the regular synchronous switching of the commutating switch during a load detection period, to sense the voltage at the output node during the load detection period and to determine a high-load condition or a light-load condition of the DC-DC-conversion based on the sensed voltage at the output node. | 03-14-2013 |
20130044015 | ELECTRONIC DEVICE AND METHOD FOR MEASURING DNL OF AN SAR ADC - The device comprises a successive approximation register, a capacitive digital-to-analog converter comprising a plurality of capacitors, the plurality of capacitors being coupled with a first side to a common node; a comparator coupled to the common node and being adapted to make bit decisions by comparing a voltage at the common node with another voltage level, and a SAR control stage for providing a digital code representing a conversion result. The device is configured to operate in a calibration mode, where the device is configured to sample a reference voltage on a first capacitor of the plurality of capacitors by coupling one side of the first capacitor to the reference voltage, to perform a regular conversion cycle with at least those capacitors of the plurality of capacitors having lower significance than the first capacitor and to provide the conversion result of the regular conversion cycle for calibrating the first capacitor. | 02-21-2013 |
20130031154 | SELF-TIMED MULTIPLIER - A self-timed multiplier unit includes a multiplier and a clock generator. The multiplier has a first set of semiconductor circuits in a critical path. The clock generator has a second set of semiconductor circuits configured to control a clock period of said clock generator selected to set a clock period longer than the propagation delay through the critical path of the multiplier. The clock generator may include a delay circuit having a delay to set the clock period longer than the propagation delay through the critical path of said multiplier. The clock generator uses circuit with identical logical design including the same standard cells, the same logic design or the same floor plan. Close matching of these circuit causes the multiplier and the clock generator to experience the same PVT speed variations. | 01-31-2013 |
20130009706 | ELECTRONIC DEVICE AND METHOD FOR AN AMPLIFIER WITH RESISTIVE FEEDBACK - An electronic device comprising an amplifier having at least a first input transistor of a first doping type. A first transistor is coupled with a channel as a feedback path between an output of the amplifier and a control gate of the first input transistor forming an input of the amplifier. A diode-coupled second transistor is coupled with a channel between a first current source and the output of the amplifier wherein a control gate of the first transistor is coupled between the first current source and the diode-coupled second transistor and the first transistor is of a second doping type which is opposite to the first doping type of the first input transistor of the amplifier. | 01-10-2013 |
20120262437 | POWER SUPPLY UNIT AND A METHOD FOR OPERATING THE SAME - A power supply unit includes a boost converter having an input node and output node. The output node is coupled to a high-side of an H-bridge that is for supplying power to a capacitive load that is coupled to a first node and to a second node of the H-bridge. A first diode is coupled in forward direction between the first node of the H-bridge and the input node of the boost converter. A second diode is coupled in forward direction between the second node of the H-bridge and the input node of the boost converter. | 10-18-2012 |
20120223695 | ELECTRONIC DEVICE AND METHOD FOR A LIMITER IN AN AC APPLICATION - An electronic device, including a first limiter including a first transistor configured to be coupled with a first side of a channel to a first output node of a non-ideal voltage source having an inner impedance greater zero in order to limit the voltage at the first output node by drawing a current from the first output node. The second side of the channel of the first transistor is coupled to a capacitor so as to supply a current from the first output node to the capacitor, if the voltage level at the output node reaches or exceeds an upper limit. | 09-06-2012 |
20120212206 | ELECTRONIC DEVICE FOR OPTIMIZING THE OUTPUT POWER OF A SOLAR CELL AND METHOD FOR OPERATING THE ELECTRONIC DEVICE - An electronic device for optimizing the output power of a solar cell, the electronic device having: a variable resistor coupled in series between the solar cell and a load, a control unit that is configured to control the variable resistor, a sensor for measuring an output voltage and a sensor for measuring the output current of the solar cell, wherein the control unit is configured to vary the resistance of the series resistor over time such that the first order derivative of the output voltage over time has a constant value, to monitor the second order derivative of the output current over time simultaneously, to detect whether the second order derivative of the output current over time exceeds a predetermined threshold value and to identify the corresponding values of the output voltage and current as a maximum power point (MPP) of the solar cell. | 08-23-2012 |
20120211895 | CHIP MODULE AND METHOD FOR PROVIDING A CHIP MODULE - A semiconductor device comprising a semiconductor die that is embedded in a package, wherein the die has a front side comprising a plurality of pads to be bonded to terminals of the package, and wherein a backside of the die is coupled to a backside surface of the package by a thermal bridge. | 08-23-2012 |
20120193801 | RFID TRANSPONDER AND METHOD FOR CONNECTING A SEMICONDUCTOR DIE TO AN ANTENNA - An RFID transponder having a semiconductor die with a solderable contact area and an antenna made from a winding wire, wherein the winding wire is soldered to the contact area, and the solderable contact area is made from a nickel based alloy. | 08-02-2012 |
20120187857 | LIGHTING SYSTEM, ELECTRONIC DEVICE FOR A LIGHTING SYSTEM AND METHOD FOR OPERATING THE ELECTRONIC DEVICE - An electronic device for a lighting system, comprising a TRIAC dimmer configured to receive a mains supply voltage and provide a phase cut voltage to the electronic device and having a control loop configured to control a duty cycle of a switched voltage converter that receives the rectified input voltage and provides drive current to a light emitting semiconductor device. The control loop has an error amplifier that is coupled to receive a sense voltage that is indicative of a current through the light emitting semiconductor device, the error amplifier is configured to provide a feedback signal to a pulse width modulation logic configured to control the duty cycle of the switched voltage converter to provide a constant drive current to the light emitting semiconductor device in response to the sense voltage, the error amplifier being coupled to receive a reference voltage that is a function of the input voltage. | 07-26-2012 |
20120181996 | MULTI CHIP MODULE, METHOD FOR OPERATING THE SAME AND DC/DC CONVERTER - A multi chip module having a current sensing circuit and a semiconductor half bridge configuration having two vertically stacked field effect transistor dies that are connected by horizontally extending tap clips at respective opposite sides of their channels, wherein the current sensing circuit is coupled to two checkpoints, at least one being located on one of the tap clips so as to measure a voltage drop over a predetermined portion of the tap clip acting as a shunt resistor for sensing a current that is provided to a switching node of the half bridge configuration. | 07-19-2012 |
20120119884 | ELECTRONIC DEVICE AND METHOD FOR RFID - An electronic device comprising a first node to be coupled to a first antenna, a second node coupled to a second antenna, a third node to be coupled to a third antenna, a first comparator coupled with a first input to the first node and with a second input to a second node, a second comparator coupled with a first input to the first node and with a second input to the third node, a third comparator coupled with a first input to the second node and with a second input to the third node. Each of the first, the second and the third comparators are configured to compare a first current and a second current at the first input and the second input. | 05-17-2012 |
20120112761 | AUTOMATIC TEST EQUIPMENT FOR TESTING AN OSCILLATING CRYSTAL AND METHOD FOR OPERATING THE SAME - Embodiments of the invention relate to automatic test equipment for testing a circuit having an oscillating crystal and to a method for operating such automatic test equipment. A generator generates a first signal comprising an oscillating part having at least one predetermined frequency. A first terminal couples the first signal to the oscillating crystal. At least one predetermined frequency is located inside a predetermined window around one of the resonance frequencies of the oscillating crystal. An analyzer has a second terminal coupled to the oscillating crystal for detecting a second signal and a rectifier connected in series with a low-pass filter for rectifying and filtering the second signal. A detector for detects a DC-signal at the output of the low-pass filter and for signals a valid test result for the oscillating crystal if the DC-signal exceeds a certain threshold value. | 05-10-2012 |
20120106256 | ELECTRONIC CIRCUIT WITH A FLOATING GATE TRANSISTOR AND A METHOD FOR DEACTIVATING A FLOATING GATE TRANSISTOR TEMPORARILY - An electronic circuit includes a floating gate transistor with a floating gate capacitor. The floating gate transistor can be programmed to be in an ON or an OFF state by charging the floating gate capacitor. The circuit further includes a deactivation capacitor adapted to store a charge sufficient for deactivating the floating gate transistor temporarily. The deactivation capacitor is connectable in series to the floating gate capacitor. A method for deactivating a floating gate transistor temporarily is provided, wherein the floating gate transistor includes a floating gate capacitor. A deactivation capacitor is charged with a charge sufficient for changing the state of the floating gate transistor temporarily. The deactivation capacitor is connected in series to the floating gate capacitor for deactivating the floating gate transistor. | 05-03-2012 |
20120092055 | ELECTRONIC DEVICE AND METHOD FOR KICKBACK NOISE REDUCTION OF SWITCHED CAPACITIVE LOADS AND METHOD OF OPERATING THE ELECTRONIC DEVICE - An electronic device which includes a first stage having an input capacitance, a switch, a buffer and a second stage having an input sensitive to charge injection and/or voltage glitches. An input of the buffer and the input of the second stage are coupled together at a first node which is configured to be coupled to a voltage source for supplying a reference voltage to the input of the first stage having the input capacitance. In a first configuration of the switch, the switch is arranged to either connect the input of the first stage to the first node and to disconnect the input of the first stage from an output of the buffer. In a second configuration of the switch, to connect the input of the first stage to the output of the buffer and to disconnect the input of the first stage from the first node. | 04-19-2012 |
20120086509 | Amplifier Input Stage and Slew Boost Circuit - Various apparatuses, methods and systems for boosting an amplifier slew rate are disclosed herein. For example, some embodiments of the present invention provide an apparatus including a pair of inputs connected to a pair of differential input devices in an amplifier, a current source, a first current path connected to the current source, a second current path connected to the current source and to the pair of differential input devices, a switch in the first current path, and a voltage difference signal connected between the pair of inputs and the switch. The voltage difference signal represents the voltage difference between the pair of inputs. The conductance of the switch is inversely proportional to the voltage difference signal. | 04-12-2012 |
20120076176 | ELECTRONIC DEVICE AND METHOD FOR SPREAD SPECTRUM CLOCK (SSC) MODULATION - The invention relates to an electronic device that includes a plurality of buffers and a phase locked loop. For each buffer a fractional divider is provided which is coupled to receive the output from the phase locked loop and configured to feed a divided output signal to a respective buffer. A spread spectrum clock control logic stage in the spread spectrum clock (SSC) is provided which is configured to individually adjust a value of the division of each fractional divider in order to individually and independently modulate the output signal of each fractional divider according to a spread spectrum modulation scheme. | 03-29-2012 |
20120074987 | ELECTRONIC DEVICE AND METHOD FOR BUFFERING - A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode. | 03-29-2012 |
20120068302 | ELECTRONIC DEVICE AND METHOD FOR DIRECT MOUNTING OF PASSIVE COMPONENTS - An electronic device including a semiconductor die, which has a top surface that is configured to operate as a printed circuit board so as to provide connections for at least one passive component, in particular a passive surface mounted device (SMD). | 03-22-2012 |
20120062279 | Adaptively Biased Comparator - The invention relates to an electronic device which comprises a comparator coupled to monitor a first supply voltage level at a first supply voltage node. The comparator comprises a differential input transistor stage having one input coupled to the first supply voltage node and the other input coupled to receive a reference voltage level, a first current source configured to supply a current of a first magnitude, a second current source configured to supply a current of a second magnitude, and a capacitor. The first magnitude is greater than the second magnitude and the first current source is coupled with one side to the differential input stage for supplying the differential input stage and with the other side to a first node. The second current source is coupled with one side to the first node and with the other side to a second supply voltage node having a second supply voltage level and the capacitor is coupled with one side to the first node and with the other side to the first supply voltage node. | 03-15-2012 |
20110309807 | ELECTRONIC DEVICE FOR SWITCHED DC-DC CONVERSIONAND METHOD FOR OPERATING THE SAME - An electronic device for switched DC-DC conversion of an input voltage level into an output voltage level, comprising a first power switch and a second power switch, being connected in parallel and having a different gate width, and a driving stage that is configured to selectively drive the first power switch and/or second power switch depending on a load current output. | 12-22-2011 |
20110285449 | APPARATUS AND METHOD FOR EFFICIENT LEVEL SHIFT - An apparatus is provided that uses a first level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain. The first level shifter comprises a storing element in the second voltage domain, an input stage coupled to the storing element for providing a signal state to be stored in the storing element and a feedback loop from an output of the storing element to the input stage for controlling the input stage in response to a transition of a high level output signal of the storing element. | 11-24-2011 |
20110241633 | SWITCHING CONVERTER CONTROL CIRCUIT - A DC-DC converter has a control circuit for controlling a high-side power transistor and a low-side power transistor connected in series between supply terminals to which an input supply voltage is applied. The converter has a switching node at the interconnection of the power transistors for connection of an inductor to which a load is connected. The control circuit has a feedback loop that provides a pulse width modulated control signal, logic circuitry to which the pulse width modulated control signal is applied and gate drivers with inputs connected to outputs of the logic circuitry and outputs applying gate drive signals to the gates of the power transistors. A digital signal is obtained which is indicative of whether the converter switching node is at a potential above or below a zero reference at the time of the turn-off edge of the low-side gate drive signal. The turn-off edge of the low-side gate drive signal is advanced or delayed by a predetermined amount in response to the value of the digital signal. | 10-06-2011 |
20110227555 | BUFFER FOR TEMPERATURE COMPENSATED CRYSTAL OSCILLATOR SIGNALS - A buffer is provided. The buffer includes a buffering stage that receives an enable signal and an input signal and that provides an output signal and a bandgap stage that is coupled to the buffering stage and that is activated and deactivated by the enable signal. In particular, the buffering stage includes a buffering substage that includes a buffering transistor that is coupled to the input stage, wherein the buffering transistor is formed on a substrate, and wherein the buffering transistor has a channel with a doping concentration that is approximately the same as the substrate. | 09-22-2011 |
20110216468 | ELECTRONIC DEVICE FOR CONTROLLING A CURRENT - An electronic device is provided for controlling a current. The electronic device includes a first MOS transistor coupled with a gate to a common gate node, with a source to ground and with a drain to a pin so as to receive from the pin a current to be controlled. There is a second MOS transistor coupled with a gate to the common gate node, with a source to ground and with a drain so as to receive a reference current controlled by a control loop. There is a first resistor coupled between the common gate node and ground. | 09-08-2011 |
20110204860 | DC-DC CONVERTER WITH AUTOMATIC INDUCTOR DETECTION FOR EFFICIENCY OPTIMIZATION - A DC-DC converter has high-side power and low-side power transistors connected in series between supply terminals, an inductor connected between the power transistors and an output terminal. A comparator compares the output voltage with a reference voltage. A detector detects when inductor current approaches zero. A timer is configured to determine a minimum ON time of the high-side power transistor optimized for a particular value inductor. A current detector detects current flow in the back-gate diode of the low-side power transistor. timer is configured to determine an overriding ON time in response to the back-gate current detector. Logic provides control signals to gate power transistors in response to the comparator and the longer one of the minimum ON time and the overriding ON time. The minimum ON time for the high-side power transistor is adjusted in response to the actual inductance of the inductor. | 08-25-2011 |
20110202698 | APPARATUS AND METHOD FOR INCREASED ADDRESS RANGE OF AN I2C OR I2C COMPATIBLE BUS - An integrated circuit (IC) configured to operate as a slave on an inter-integrated circuit (I | 08-18-2011 |
20110193839 | LEVEL SHIFTER FOR USE IN LCD DISPLAY APPLICATIONS - A level shifter for use in LCD display applications is provided which includes a group of separate channels each with a signal input and a signal output and with channel control circuitry supporting gate voltage shaping for improving image quality. The level shifter further has a number of flicker clock inputs. The channel control circuitry of each particular channel in the group comprises logic circuitry combining all of said flicker clock inputs with the signal input of the particular channel and signal inputs form other channels into a gate voltage shaping enable signal for the control circuitry of the particular channel. With this configuration it is possible to use the same level shifter IC with only one flicker clock signal for all phases, regardless of how many, without the need for an additional synchronization signal, or multiple flicker clock signals as is conventional. The level shifter automatically determines which input signal needs to be modified for the gate voltage shaping when the active portion of the flicker clock signal is detected. | 08-11-2011 |
20110189383 | Device and Method for Inert Gas Cure for Leadframe or Substrate Strips - A cover for use in a cure oven, wherein the cover is configured to enclose an inner volume of a storage cassette air-tightly. The storage cassette is of the kind to store a plurality of leadframe or substrate strips having a die overcoat to be cured. The cover comprises a first opening for supplying an inert gas to the storage cassette and a second opening for letting the inert gas off. A box for use in a cure oven, the box including a storage cassette configured to store a plurality of leadframe or substrate strips having a die overcoat to be cured and a cover to enclose the plurality of leadframe or substrate strips in the storage cassette air-tightly. A first opening is provided for supplying an inert gas to the storage cassette and a second opening is provided for letting the inert gas off. A method of curing a die over coat on a leadframe or substrate, including arranging a plurality of leadframe or substrate strips having a die overcoat to be cured in a storage cassette and enclosing the leadframe or substrate strips in the storage cassette air-tightly in a box which has a first and a second opening. The box is placed in a cure oven and by the first opening an inert gas is supplied into the box for preventing oxidation of the leadframe or substrate strips. The cure oven is heated to cure the die overcoat. | 08-04-2011 |
20110175683 | ELECTRONIC DEVICE FOR CONTROLLING A FREQUENCY MODULATION INDEX AND A METHOD OF FREQUENCY-MODULATING - An electronic device controlling a frequency modulation index has a frequency modulation index control loop having an input adapted to be connected to a frequency output of a frequency controllable oscillator. The oscillator has a center frequency F | 07-21-2011 |
20110165760 | METHOD OF PRODUCING BIPOLAR TRANSISTOR STRUCTURES IN A SEMICONDUCTOR PROCESS - In the method of producing bipolar transistor structures in a semiconductor process, an advanced epitaxial trisilane process can be used without the risk of poly stringers being formed. A base window is structured in a polycrystalline silicon layer covered with an oxide layer, and a further step is epitaxial growing of a silicon layer in the base window from trisilane. The window structuring is performed in a sequence of anisotropic etch and isotropic ash steps, thereby creating stepped and inwardly sloping window edges. Due to the inwardly sloping side walls of the window, the epitaxially grown silicon layer is formed without inwardly overhanging structures, and the cause of poly stringers forming is thus eliminated. | 07-07-2011 |
20110125435 | Apparatus and method for impedance measurement - A system is provided which comprises a signal generator for generating a periodic excitation signal and an analog to digital converter, wherein the system is configured to apply the periodic excitation signal to a network comprising a known first impedance and a second impedance and to take a first set of M digital samples of a first signal relating to the first impedance and a second set of M digital samples of a second signal relating to the second impedance with a sampling frequency that is an integer multiple of the frequency of the periodic signal. The system is further configured to determine the impedance value of the second impedance by calculating a relative phase difference between the first signal and the second signal using the first set of digital samples and the second set of digital samples. | 05-26-2011 |
20110089993 | ELECTRONIC DEVICE AND METHOD FOR DC-DC CONVERSION - An electronic device for driving a power switch coupled to receive a first supply voltage level at one side of its channel is provided. The electronic device includes a control switch coupled with a first side of a channel to receive a varying control voltage having a maximum level that is greater than a maximum voltage level of the first voltage supply and with another side of the channel to a control gate of the power switch for selectively applying the control voltage to the control gate of the power switch. The first side of the channel is coupled with the control gate of the control switch and a capacitor is provided and coupled with a first side to the control gate of the control switch and with a second side to a constant voltage supply. | 04-21-2011 |
20110068838 | ELECTRONIC DEVICE FOR POWER-ON-RESET - An electronic device is provided that includes a power-on-reset (POR) circuit. The POR circuit includes a trigger stage configured to change an output if a first power supply voltage level exceeds a threshold voltage level and a first inverter and a second inverter being cross-coupled. An output of the second inverter is the POR output of the power-up reset circuit. The output is coupled to the trigger stage for switching the trigger stage off in response to a change of a signal at the output of the second inverter. The first inverter is dimensioned to follow with a voltage level at an output an initially rising slope of the first power supply voltage level and the second inverter is dimensioned to keep a voltage level at an output at a second power supply voltage level during the initially rising slope of the first power supply voltage level. | 03-24-2011 |
20110068754 | ELECTRONIC DEVICE AND METHOD FOR DC-DC CONVERSION - An electronic device for DC-DC conversion of an input voltage into an output voltage is provided. The electronic device includes a current mode control loop for controlling a sensed current of the DC-DC conversion by comparing a voltage level indicating a magnitude of the sensed current with a reference voltage level indicating the maximum admissible magnitude of the sensed current. The reference voltage level is dynamically adjusted in response to a change of an input voltage level. | 03-24-2011 |
20110057718 | APPARATUS AND METHOD FOR OFFSET DRIFT TRIMMING - An apparatus is provided that includes a drift trimming stage that includes a first current source providing a current with a first temperature dependency and a second current source providing a current with a second temperature dependency. The first and the second current source are coupled at a first node and configured to have equal currents at a first temperature. There is further a third current source providing a current with a third temperature dependency and a fourth current source providing a current with a fourth temperature dependency. The third current source and the fourth current source are coupled at a second node and configured to have equal currents at the first temperature. There is a first resistor coupled between the first node and a third node, a second resistor coupled between the second node and the third node. The first node and the second node are coupled to provide a combined voltage drop across the first resistor and the second resistor for reducing the offset drift. | 03-10-2011 |
20110050250 | ELECTRONIC DEVICE AND METHOD FOR INDUCTOR CURRENT MEASUREMENT - An electronic device includes a circuit for measuring a current in an inductor, wherein the current in the inductor is controlled by alternately switching a first power transistor and a second power transistor each having a first electrode, a second electrode and a control gate. The measuring circuit includes a first sense transistor having a first electrode, a second electrode and a control gate, the first sense transistor having the control gate coupled to the control gate of the first power transistor. A second electrode is coupled to the second electrode of the first power transistor. A second sense transistor has a first electrode, a second electrode and a control gate, the second sense transistor having the control gate coupled to the control gate of the second power transistor and having the second electrode coupled to the second electrode of the second power transistor. An amplifier is operable in a first configuration for providing an output current that is a function of a first current though the first sense transistor during a first period of time or in a second configuration for providing the output current as a function of a second current through the second sense transistor during a second period of time, so as to alternately sense a current through the first power transistor with the first sense transistor and through the second power transistor with the second sense transistor. | 03-03-2011 |
20110041013 | ELECTRONIC DEVICE AND METHOD FOR VERIFYING CORRECT PROGRAM EXECUTION - An electronic device is provided which comprises a microprocessor for executing a program code and a first hardware code path verifying (CPV) stage coupled to the microprocessor. The hardware CPV stage comprises a first error detection code (EDC) generator configured to continuously determine an error detection code on a continuous sequence of code relating to an actually executed portion of the program code and to compare the actual error detection code with a predetermined error code so as to verify correct execution of the program code and to indicate an error. | 02-17-2011 |
20110037509 | APPARATUS AND METHOD FOR EFFICIENT LEVEL SHIFT - An apparatus is provided that uses a first level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain. The first level shifter comprises a storing element in the second voltage domain, an input stage coupled to the storing element for providing a signal state to be stored in the storing element and a feedback loop from an output of the storing element to the input stage for controlling the input stage in response to a transition of a high level output signal of the storing element. | 02-17-2011 |
20100295617 | APPARATUS AND METHOD FOR DRIVING AN LED - Here, a driver for an light emitting diode (LED) is provided. Within this driver, several differential pairs of bipolar transistors are employed in an input stage and output stage along with a control loop. Collectively, these components operate together to drive the LED with a low headroom voltage while still achieving high driver performance in terms of edge speed and jitter. | 11-25-2010 |
20100295615 | CML OUTPUT DRIVER - An integrated circuit (IC) for driving a light emitting semiconductor device is provided. The IC includes an input stage configured to receive a first input signal with a first differential pair of bipolar transistors and a second input signal with a second differential pair of bipolar transistors and to provide a pre-driver output signal being a superposition of the first input signal and the second input signal and an output stage including a third differential pair of bipolar transistors for receiving the pre-driver output signal of the input stage and for driving the light emitting semiconductor device in response to the pre-driver output signal, wherein the IC is configured to pre-distort the pre-driver output signal of the input stage so as to compensate a signal distortion of the output stage. | 11-25-2010 |
20100290368 | HALF-DUPLEX RFID TRANSPONDER AND A METHOD OF OPERATING A HALF-DUPLEX RFID TRANSPONDER - A half-duplex RFID transponder with an integrated three-dimensional front-end circuit which includes three LC resonant circuits arranged in a three-dimensional configuration. Each LC resonant circuit is coupled to a different one of three storage capacitors which are charged during a capacitor charging phase by energy in an RF signal received by the associated LC resonant circuit. The front-end circuit includes three receiver channels and each receiver channel is associated to a different one of the three LC resonant circuits. A channel selector is adapted to detect, which one of the three storage capacitors is first charged to a threshold voltage, to select the receiver channel associated to the LC resonant circuit which is coupled to the storage capacitor which is first charged and to deactivate the two other receiver channels. A method of operating a half-duplex RFID transponder with three LC resonant circuits arranged in a three-dimensional configuration with each LC resonant circuit coupled to a different storage capacitor which is charged during a capacitor charging phase by energy in an RF signal received by the associated LC resonant circuit. Three receiver channels are associated to the three LC resonant circuits. The method includes monitoring the charge level of each of the three storage capacitors, detecting which storage capacitor is first charged to a threshold voltage, selecting the receiver channel associated to the first charged storage capacitor and deactivating the two other receiver channels. | 11-18-2010 |
20100277220 | SELF BIASED GATE CONTROLLED SWITCH - Conventional current sharing circuits, which can be used in drivers for liquid crystal displays (LCDs), for example, often use bipolar transistors. However, bipolar transistors are not available in many CMOS processes. Thus, a current sharing circuit is provided here that employs CMOS transistors. In particular, the circuit provided here uses a current mirror and pass circuit to assist in providing this current sharing function. | 11-04-2010 |
20100264981 | CHARGE PUMP WITH SELF-TIMING AND METHOD - With conventional charge pumps, significant noise is present due at least in part to large changes in the supply current. To combat this problem, a charge pump is provided that includes a number of stages. These stages are coupled to receive periodic alternating voltages having a phase shift with respect to each other so that the changes in the supply current are reduced, which reduces noise. | 10-21-2010 |
20100253315 | POWER LEVEL INDICATOR - An electronic device is provided that is adapted to generate a supply voltage at an input node from a radio frequency (RF) signal. The electronic device includes a limiter coupled to the input node for limiting a supply voltage level at the input node that is generated by the received RF signal. The limiter is configured to draw a limiter current from the input node so as to limit the supply voltage level to a maximum and a magnitude of the limiter current is used for controlling a power consumption of the electronic device. | 10-07-2010 |
20100253313 | ELECTRONIC DEVICE AND METHOD FOR DC-DC CONVERSION WITH SLOPE COMPENSATION - An electronic device is provided which comprises circuitry for DC-DC conversion configured to switch an inductor current through an inductor using slope compensation, wherein the circuitry comprises a slope compensation stage configured to generate a slope compensation signal as a function of an switching frequency of the DC-DC conversion and an input voltage of the DC-DC converter. | 10-07-2010 |
20100235698 | JTAG Mailbox - An electronic device comprises a processing stage, a JTAG port including a test data input pin (TDI), a test data output pin (TDO), a test mode select pin (TMS), a test clock pin (TCK), and a test access port (TAP) controller having a data register (DR) shift state and an instruction register shift (IR) state. The electronic device operates in a scan event mode automatically mapped an incoming event to the TDO pin. | 09-16-2010 |
20100231187 | SWITCHED MODE POWER SUPPLY WITH CURRENT SENSING - An electronic device for switched mode DC-DC conversion is provided that includes a stage for sensing an output current causing a voltage difference between a first and a second node. The current sensing stage includes a comparator being capacitively coupled with a first input to the first node and with a second input to the second node for determining a magnitude of the output current. | 09-16-2010 |
20100220087 | APPARATUS AND METHOD FOR DRIVING DISPLAYS - Generally, displays, like liquid crystal displays (LCDs), use a DC-free addressing voltage in order to prevent decomposition of the display. Here, an integrated circuit (IC) is provided that compensates for temperature dependencies. This IC typically uses a thermistor or temperature varying element to measure the temperature of the display and adjusts the common reference voltage in response to the measured temperature. | 09-02-2010 |
20100214140 | DIGITAL TRIMMING OF SAR ADCS - Successive approximation register (SAR) analog-to-digital converters (ADCs) generally employ capacitive digital-to-analog converters (CDACs) to perform data conversions. In these CDACs, matching of capacitive values is important, and for conventional high resolution SAR ADCs, complex trimming or calibration procedures can be too costly. Here, however, a SAR ADC is provided that performs error correction so as to reduce the overall cost compared to conventional SAR ADCs. | 08-26-2010 |
20100211728 | APPARATUS AND METHOD FOR BUFFERING DATA BETWEEN MEMORY CONTROLLER AND DRAM - A apparatus is provided for buffering data between a memory controller and a DRAM. The apparatus includes a phase locked loop (PLL), a phase interpolator for aligning a phase of an output clock signal in response to a phase aligning control word, and a non-volatile storage location permanently storing the phase aligning control word. The phase aligning control word is determined through an initial training procedure of the device under predetermined training conditions of at least a supply voltage level and a temperature, and the predetermined training conditions are set so as to optimize the phase alignment of an edge of the output clock signal with respect to the buffered data signal. | 08-19-2010 |
20100208980 | APPARATUS AND METHOD FOR DETECTING DEFECTS IN WAFER MANUFACTURING - Apparatus for inspecting a semiconductor wafer ( | 08-19-2010 |
20100176859 | Self-Protecting Core System - The present invention is applicable to an electronic device including a master, a slave, a bus coupling the master and the slave and a clock generator for providing a system clock to the master and slave. The clock generator determines whether the received data is correct on a cycle-by-cycle basis. The clock generator suppresses an edge of a next clock cycle of the system clock signal if the data is not to be correct. The clock generator allows the edge of a next clock cycle of the system clock signal if the data is correct. | 07-15-2010 |
20100165686 | RECTIFIER CIRCUIT - A rectifier circuit for use in an energy harvesting application in which mechanical energy is converted into electrical energy by using an AC generator using an active rectifier bridge with a pair of input terminals adapted to be connected to an output of the AC generator and a pair of output terminals, an inductor connected across the output terminals of the active rectifier bridge and a storage capacitor. A pair of output switches selectively connects the storage capacitor across the inductor. A controller controls the active rectifier bridge and the pair of output switches such that in successive switching cycles within any half wave of AC input voltage from the output of the AC generator the inductor is first loaded by current from the output of the AC generator and then discharged into the storage capacitor. An energy harvesting system which uses an AC generator for generating electrical energy out of mechanical energy, a rectifier circuit which is connected with the input to the output of the AC generator and a low power wireless system as application unit. A method of rectifying an AC output voltage of an AC generator for use in an energy harvesting application. | 07-01-2010 |
20100164725 | TRANSPONDER DEMODULATOR FOR A LOW ANTENNA LIMITER THRESHOLD - An RFID transponder having an antenna for receiving an RF signal including an amplitude modulated downlink data signal, and a demodulating stage coupled to the antenna for receiving a derived RF signal which is derived from the received RF signal. The demodulating stage has a first filter for extracting a field strength signal component from the derived RF signal and a second filter for extracting the modulated downlink data signal component from the derived RF signal. Further, a demodulator is coupled to the second filter to receive the modulated downlink signal for demodulating the modulated downlink data signal component and coupled to the first filter to receive the field strength signal such that the demodulator is adapted to vary a demodulation sensitivity parameter in response to the field strength signal. | 07-01-2010 |
20100164570 | DEVICE AND METHOD FOR GENERATING CLOCK SIGNALS FOR DC-DC CONVERTERS - An electronic device includes a DC-DC converter for voltage conversion in a slave mode an in a master mode and including a phase locked loop. The phase locked loop comprises a controlled oscillator, a filter having an integration capacitor coupled to a control input of the controlled oscillator, a charge pump, and a phase frequency detector. In the slave mode, the controlled oscillator, the filter, the charge pump and the phase frequency detector are coupled to operate as the phase locked loop. There is a comparator coupled with an input to a control input of the controlled oscillator and with an output to the charge pump. In the master mode, the comparator is configured to control the charge pump in response to a control signal at the control input of the controlled oscillator when the phase frequency detector is switched off so as to perform a modulation of the control signal at the control input of the controlled oscillator by charging and discharging the integration capacitor. | 07-01-2010 |
20100161874 | MULTIPLE SLOT MEMORY SYSTEM - A memory system having a memory controller plus one or more registered memory modules, each registered memory module having a bank of memory chips and an associated register. A pre-register address/command bus connects the memory controller with the associated register. Each registered memory module has a post-register command/address bus that connects the memory chips in parallel with the associated register. The post-register command/address bus terminates with termination resistors that are connected to a voltage level that is approximately half of the supply voltage level. The memory controller provides chip select signals to the associated register of the registered memory modules. The associated registers, however, switch command/address signals to the memory chips independent of the chip select signals. | 06-24-2010 |
20100148875 | CIRCUIT FOR COMPENSATION OF LEAKAGE CURRENT-INDUCED OFFSET IN A SINGLE-ENDED OP-AMP - An electronic device includes an operational amplifier, with the operational amplifier having an amplifier input stage coupled with a first output node to an amplifier output stage. A compensation capacitance is connected between an output node of the amplifier output stage and the first output node of the amplifier input stage, thereby operating as a compensator for stabilizing the operational amplifier. The compensation capacitance provides a parasitic diode drawing a first leakage current from the first output node of the amplifier input stage, a leakage current compensation circuit being coupled to the first output node of the amplifier input stage and coupled to a second output node of the amplifier input stage for drawing a first current from the first output node and a second current from the second output node. The leakage current compensation circuit is adapted such that the second current is greater than the first current by an amount corresponding to the first leakage current. | 06-17-2010 |
20100141389 | RFID TRANSPONDER WITH IMPROVED WAKE PATTERN DETECTION AND METHOD - An RFID transponder is provided which includes an automatic gain control (AGC) stage for amplifying a radio frequency (RF) signal and for providing an amplified RF signal. The AGC stage has a control signal indicating an increase of the amplitude of the RF signal. A demodulator is coupled to receive the amplified RF signal for demodulating the amplified RF signal. The demodulator provides a data signal. A burst detector is coupled to receive the control signal of the AGC stage and adapted to provide a start signal in response to a change of the control signal. A wake pattern detector is coupled to receive the data signal and the start signal. The wake pattern detector is adapted to detect a predefined wake pattern in the data signal after having received the start signal and to issue a wake signal if the predefined wake pattern is detected for switching the RFID transponder from a first operating mode into a second operating mode having higher power consumption than the first operating mode. | 06-10-2010 |
20100136764 | METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - A method of manufacturing an integrated circuit comprises depositing a electrically resistive layer of a material for serving as a thin film resistor (TFR), depositing an electrically insulating layer on the resistor layer, removing the electrically insulating layer from outside an electrically active area of the resistor layer corresponding to a target TFR area, and depositing an electrically conductive layer of an electrically conductive material such that the conductive layer overlaps the target TFR area and the conductive layer electrically contacts the resistor layer outside the target TFR area. | 06-03-2010 |
20100052962 | POLYPHASE ELECTRIC ENERGY METER - A polyphase electric energy meter comprises a microcontroller with a front end that converts analog current input signals and analog voltage input signals to digital current and voltage samples for processing by the microcontroller. The front end includes separate input channels, each for one of the current input signals with a sigma-delta modulator followed by a decimation filter. The front end further includes a common input channel for all voltage input signals with a multiplexer, an analog-to-digital converter and a de-multiplexer. The separate input channels and the common input channel provide the digital current and voltage samples for processing by the microcontroller. | 03-04-2010 |
20100039144 | CURRENT DRIVER CIRCUIT - An integrated regulated current drive circuit for driving a squib of an inflatable airbag has a current sense resistor connected in series with a load, and a reference resistor connected in series with a reference current source. Both resistors are matched to define a precise ratio of resistance values which determines the amount of current fed to the squib. Both resistors are implemented by combining a number of identical on-chip resistor elements. | 02-18-2010 |
20100026546 | SAR ADC - An electronic device is provided for analog to digital conversion using successive approximation. The device comprises a first ADC stage. The first ADC stage includes a first plurality of capacitors adapted to sample an input voltage, and adapted to be coupled to either a first reference signal level or a second reference signal level. At least one capacitor of the first plurality of capacitors is adapted to be left floating. A control stage is adapted to switch the at least one floating capacitor to the first reference signal level or the second reference signal level in response to an analog to digital conversion decision made by a second ADC stage. | 02-04-2010 |
20090323238 | Electronic device including a protection circuit for a light-emitting device - An electronic device including a protection circuit for a light-emitting device An electronic device is provided that includes a protection circuit for a light-emitting device. The protection circuit comprises a first node adapted to be coupled to an anode of the light-emitting device and a second node adapted to be coupled to a cathode of the light-emitting device. A voltage detection stage is coupled between the first and second nodes. The voltage detection stage is adapted to detect an overvoltage condition between the first and second nodes. Furthermore, the protection circuit comprises a thyristor coupled with its anode to the first node, its cathode to the second node to the voltage detection stage. When the overvoltage condition is detected in normal operation the thyristor is controlled to open so that the current can flow through the thyristor. | 12-31-2009 |
20090322372 | AUTOMATIC TEST EQUIPMENT - A coupling line is provided for coupling a signal generator to a device under test and includes a first Zener diode and a second Zener diode. The first Zener diode and the second Zener diode are coupled in an antiserial manner. They are adapted to couple the signal generator to the device under test when the signal generator is active and decouple the signal generator from the device under test when the signal generator is inactive. | 12-31-2009 |
20090322295 | TECHNIQUE TO IMPROVE DROPOUT IN LOW-DROPOUT REGULATORS BY DRIVE ADJUSTMENT - An electronic device includes a low drop-out regulator for providing a regulated output voltage. The low drop-out regulator generally comprises a power MOSFET transistor having a gate coupled to a driver. The driver has a first path including an NMOS transistor and being coupled to the gate of the power MOSFET, a second path having a PMOS transistor and being coupled to the gate of the power MOSFET, and a switch for alternately switching between the first and second paths so as to provide a voltage to the gate of the power MOSFET ranging from ground to a power supply level. | 12-31-2009 |
20090322292 | LINEAR VOLTAGE REGULATOR WITH ACCURATE OPEN LOAD DETECTION - A linear voltage regulator is provided which has a pair of complementary power transistors connected “back to back” in series between a voltage input and a voltage output. A current sense circuit is connected in parallel across one of the power transistors, such as the one connected to the voltage input. The current sense circuit includes a current sense resistor. A reference current path has a reference resistor connected in series with a current sink between the voltage input and a reference terminal, usually ground. A comparator has a first input connected to a terminal of the current sense resistor and a second input connected to a node between the reference resistor and the current sink. The comparator compares the voltage drop across the current sense resistor with the constant voltage drop across the reference resistor and provides an output signal indicative of an open load condition when the voltage drop across the current sensor falls below that of across the reference resistor. As long as the voltage drop in the current sense circuit remains small, i.e. less than app. 0.7V, the current flowing through the bulk diode of the power transistor remains negligible and the entire output current flows through the current sense circuit. For higher output currents the voltage drop across the current sense circuit is limited by the parallel bulk diode of the power transistor. With this approach, the current sense resistor can be dimensioned to generate a relatively high voltage drop of e.g. 100 mV, and a high accuracy of open load detection is achieved without the requirement for a high precision comparator. | 12-31-2009 |
20090303649 | ENHANCED CHARGER OVER VOLTAGE PROTECTION FET - An integrated battery charger protection circuit incorporates a charge control power FET for series connection in the battery load current path from a DC supply input terminal to a controlled DC output terminal. The circuit has a gate drive input terminal connected to the gate of the charge control power FET and further includes protective circuitry adapted to disable the DC output terminal in a fault condition detected within the integrated circuit. The controlled DC output terminal and the gate drive input terminal are connectable to the external charge control host circuit the same way as corresponding terminals of a discrete power FET, in particular of p-channel type. | 12-10-2009 |
20090295460 | ELECTRONIC DEVICE AND METHOD FOR EVALUATING A VARIABLE CAPACITANCE - An apparatus is provided. The apparatus comprises a digital signal generator, an analog filter, an amplitude modulator, and an analog-to-digital converter (ADC). The digital signal generator has a demodulator and provides a digital excitation signal. The analog filter is coupled to the digital signal generator. The amplitude modulator has a variable capacitor and is coupled to the analog filter. The amplitude modulator also generates an amplitude modulated signal with an amplitude that is a function of the capacitance of the variable capacitor. The ADC is coupled to the amplitude modulator and the demodulator, and the digital signal generator and the demodulator operate synchronously. | 12-03-2009 |
20090289665 | Comparator - An electronic device compares a first voltage with a selected first reference voltage or second reference voltage. The electronic device includes a comparator having a first input receiving the first voltage, a second input receiving the selected reference voltage and an output providing an output signal based on a comparison. A control stage connected to the output of the comparator generates a control signal based on the output of the comparator. The electronic device selects either the first reference voltage or the second reference voltage in response to the control signal thus comparing the first voltage with the selected reference voltage. | 11-26-2009 |
20090284295 | Timer for Low-Power and High-Resolution - The present invention is an electronic device comprising a counter driven by an input clock signal for counting clock cycles and providing a count. A clock signal generating stage provides a first set of phase shifted clock signals having m different phases. The electronic device determines n least significant bits of the count of the counter from the logic states of the first set of m phase shifted clock signals. | 11-19-2009 |
20090267682 | HIGH PRECISION POWER-ON-RESET CIRCUIT WITH AN ADJUSTABLE TRIGGER LEVEL - An electronic device comprising circuitry for providing a Power-on-Reset (POR) signal as a function of a supply voltage level of the circuitry. The circuitry comprises a Vbe-cell or a Vgs-cell comprising a first current path including a first transistor and a second current path including a second transistor. Each transistor has a control terminal for controlling a first current in the first current path and a second current in the second current path, wherein a control voltage level is commonly applied to the control terminals of the first and the second transistor. The control voltage level is derived from the current supply voltage level of the circuitry, and the circuitry further comprises a POR output node for providing a POR output signal, which changes from a first state to a second state in response to the ratio of the magnitudes of the first current and the second current. | 10-29-2009 |
20090267651 | SWITCH STATE DETECTOR AND ENCODER - A switch state detector for use in a system wherein a plurality of n switches (S | 10-29-2009 |
20090247054 | METHOD TO PREVENT SLURRY CAKING ON CMP CONDITIONER - A method of planarizing a semiconductor structure comprises moving a conditioning element on a surface of a polishing member, rotating the semiconductor structure relative to the polishing member against the surface of the polishing member, and rinsing the surface of the polishing member and the semiconductor structure. While the conditioning element is moved over the surface of the polishing member and the semiconductor structure is rotated against the surface of the polishing member, slurry is directed onto the polishing member. The step of rinsing comprises contacting the conditioning element to the surface of the polishing member. | 10-01-2009 |
20090212916 | TRANSPONDER BACK SCATTER MODULATOR WITH REGULATED MODULATION DEPTH - An RFID transponder includes an antenna and modulation circuitry for back scatter modulation at an local voltage rail connected to the antenna such that a voltage of the antenna is maintained within a predetermined range. The modulation circuitry includes a voltage regulation loop including a rectifier connected between the antenna and the local voltage rail (Vlocal) for rectifying a voltage from the antenna so as to load the local voltage rail (Vlocal) with the rectified voltage from the antenna, an error amplifier (A | 08-27-2009 |
20090212393 | METHOD OF MANUFACTURING AN ELECTRONIC DEVICE INCLUDING A PNP BIPOLAR TRANSISTOR - A method of manufacturing an electronic device including a PNP bipolar transistor comprises forming a collector in a substrate, depositing a base layer and an emitter layer on the substrate, and growing a nitride interface layer on the base layer as a base current modulation means, such that the nitride interface layer is arranged between the base layer and the emitter layer. | 08-27-2009 |
20090207864 | CIRCUITRY AND METHOD FOR DETECTION OF NETWORK NODE AGING IN COMMUNICATION NETWORKS - The network node includes a local crystal oscillator for providing a time reference derived from the clock signal produced by the local crystal oscillator, a reset stage for resetting the network node in response to a bus reset pulse received through the network and a control means for issuing a bus reset pulse of a predetermined length substantially greater than a clock period of the clock signal of the local crystal oscillator. Further the network node includes a bus reset detector for determining a length of the received bus reset pulse based on the local time reference. The bus reset detector in the network node is also adapted to adjust the local time reference based on the determined length of the received bus reset pulse. | 08-20-2009 |
20090206991 | INCREMENTING COUNTER WITH EXTENDED WRITE ENDURANCE - A method and device for writing a binary count of a length n to a memory having a limited number of write cycles, a physical storage location of bits (R-bits) of the count in the memory are periodically changed, fixed bits of the count are stored at fixed physical storage locations, and a bit value pattern of the fixed bits is used as an indicator for the physical storage locations of the changing bits (R-bits). | 08-20-2009 |
20090206811 | CURRENT LIMITED VOLTAGE SOURCE WITH WIDE INPUT CURRENT RANGE - An integrated electronic device includes circuitry for providing a regulated output supply voltage level at an output node from an adjustable current. The circuitry includes an adjustable current source for providing the adjustable current and for adjusting the adjustable current to a magnitude of a target value in response to a configuration signal, an auxiliary adjustable current source providing an auxiliary adjustable current having a magnitude corresponding to the target value, and an output supply voltage level regulating loop coupled to the output node and adapted to keep the output supply voltage level at a preset value. A current selecting stage is adapted to receive the adjustable current and the auxiliary current. The current selecting stage is further adapted to supply a selected current corresponding to a lesser value of the adjustable current and the auxiliary adjustable current. Further, a current limiting stage is coupled to the output node for limiting the selected current to a predefined magnitude. | 08-20-2009 |
20090206772 | DC-DC CONVERTER AND METHOD FOR MINIMIZING BATTERY PEAK PULSE LOADING - The invention relates to an electronic device, comprising a DC-DC converter for converting a primary supply voltage into an output voltage at an output node to be coupled to a super capacitor and a control stage for operating the regulated DC-DC converter in a forward direction in a boost mode providing a boost voltage level at the output node and for operating the regulated DC-DC converter in a reverse direction in a buck mode providing a buck voltage level at an auxiliary node arranged between a primary voltage supply providing the primary supply voltage and the output node, wherein the control stage is adapted to control the DC-DC converter when operating in reverse direction to provide a current to the auxiliary node using the super capacitor as a power source. | 08-20-2009 |
20090195366 | HIGH PERFORMANCE RFID TRANSPONDER WITH FAST DOWNLINK - A RFID transponder having a high quality factor antenna (LR), and a resonance capacitor (CR) coupled to the high quality factor antenna (LR) for providing a resonant circuit (LR, CR), wherein the RFID transponder is adapted to vary the quality factor of the resonant circuit (LR, CR) such that the quality factor is low during downlink data transmission when the RFID transponder receives data through the antenna (LR), and the quality factor is high during uplink data transmission, when the RFID transponder transmits data. | 08-06-2009 |
20090195234 | ON-CHIP VOLTAGE SUPPLY SCHEME WITH AUTOMATIC TRANSITION INTO LOW-POWER MODE OF MSP430 - An integrated electronic device includes circuitry for providing a system supply voltage from a primary power supply. The circuitry has a high power (HP) stage coupled to the primary power supply and having an output node coupled to a supply system node for providing a HP system supply voltage level and a HP output current such that the HP stage is configured to be active in a full power mode, and a low power (LP) stage coupled to the primary power supply and to the supply system node through a voltage follower for providing a LP supply voltage level and an LP output current such that the LP stage is configured to be active in a low power mode. The HP system supply voltage level is greater than the LP system supply voltage level and the voltage follower of the LP stage is adapted to switch off in response to a voltage level at the supply system node becoming greater than the HP system supply voltage level and to switch on in response to the voltage level at the supply system node becoming lower than the HP system supply voltage level. | 08-06-2009 |
20090195214 | CHARGING SYSTEM - A mobile electronic device includes circuitry for contactless charging. The circuitry comprises an inductor for contactlessly receiving power and supplying the power to the mobile electronic device. A control stage coupled to the inductor and is adapted to control a supply of power received by the inductor to the load to regulate a load current such that a supply voltage is maintained above a predetermined level. | 08-06-2009 |
20090189688 | HIGH DYNAMIC RANGE ASK DEMODULATOR FOR USE IN AN RFID TRANSPONDER - An ASK demodulator for use in an RFID transponder having a limiter circuit associated with the antenna circuit and converting the ASK antenna fieldstrength modulation into an ASK limiter current modulation by limiting the antenna voltage to a fixed value and thereby causing the limiter current to be substantially proportional to the ASK antenna field strength, and a current discriminator circuit that discriminates the ASK limiter current modulation. By converting the fieldstrength modulation into a proportional limiter current and discriminating that limiter current, a linear relationship and a stable demodulator sensitivity are achieved. The current discrimination can be made accurately under low-voltage conditions. | 07-30-2009 |
20090189647 | BIAS CURRENT GENERATOR FOR MULTIPLIE SUPPLY VOLTAGE CIRCUIT - An electronic device supplied by multiple supply voltages includes a bias current generating stage and maximum current selection stage. The bias current generating stage comprises a crude bias current generator for generating an crude bias current during a power up phase in which at least one of the multiple supply voltages has not yet reached its target supply voltage level, a reference current stage for providing a reference current having a target current value greater than the target value of the crude bias current when the multiple supply voltages have reached their target supply voltage levels. The maximum current selection stage is adapted to continuously output a bias current which is the maximum current of the crude bias current and the reference current. | 07-30-2009 |
20090184762 | OPTIMIZED RESISTOR NETWORK FOR PROGRAMMABLE TRANSCONDUCTANCE STAGE - A voltage-to-current converter is provided. The voltage-to-current converter comprises an amplifier, a resistor network, an R-2R network, and switches. The amplifier has a first input node (which is an input signal), a second input node, and an output node. The resistor network is coupled to the output node of the amplifier, includes a plurality of resistors coupled in series with on another, and includes a plurality of first tap nodes. The R-2R network is coupled to the resistor network and includes a plurality of second tap nodes. Additionally, at least one switch is coupled between the second input node of the amplifier and each first tap node, and at least one switch is coupled between the second input node of the amplifier and each of the second tap nodes. | 07-23-2009 |
20090174592 | RFID TRANSPONDER WITH PLL - An RFID transponder comprises an antenna for receiving data in a downlink mode and transmitting data in an uplink mode, with a modulation stage for modulating uplink data and a demodulation stage for demodulating downlink data. A class C amplifier is provided, which has a resonant circuit, a plucking device coupled to the resonant circuit, and a controllable pulse width generator coupled to the plucking device. The controllable pulse width generator is adapted to periodically switch the plucking device on and off so as to maintain an oscillation of the resonant circuit. The transponder further comprises a phase locked loop configured to be locked to an oscillating signal received through the antenna and to be switched into a free running mode without being locked to the oscillating signal received through the antenna, thereby being adapted to output an independent internal clock signal for the RFID transponder. | 07-09-2009 |
20090174529 | SELF-CALBRATING RFID TRANSPONDER - A RFID transponder includes a resonant circuit for providing a clock signal at a predetermined clock frequency, a self-calibration stage for calibrating the resonant circuit's current clock frequency towards the predetermined clock frequency. The self-calibration stage is adapted to compare a first clock frequency of the resonant circuit determined during an interrogation period, during which the resonant circuit is excited by an external RF signal, with a second clock frequency determined during a frequency maintenance period, during which the resonant circuit is excited internally through an oscillation maintenance circuit of the RFID transponder and to calibrate the resonant circuit towards the predetermined clock frequency based on the comparison result. | 07-09-2009 |
20090174417 | SWITCHED CAPACITOR MEASUREMENT CIRCUIT FOR MEASURING THE CAPACITANCE OF AN INPUT CAPACITOR - A switched capacitor measurement circuit is provided for measuring the capacitance of an input capacitor with a parallel parasitic resistor. The circuit comprises a switching arrangement, a reference capacitor, a steered current sink and an operational amplifier with an output, a non-inverting input connected to a reference voltage source and an inverting input connected to a first terminal of the input capacitor. The current sink is steered to compensate for a charge current due to the parasitic resistor. Still further, the circuit comprises a digital adder and an analog-to-digital converter with an analog input connected to the output of the operational amplifier and a digital output connected to a first input of the digital adder. A second input of the digital adder receives a negative digital error signal and the output of the digital adder provides a digital capacitance measurement signal corrected for an error current which is integrated across the reference capacitor in the gain mode due to the slewing of the operational amplifier. | 07-09-2009 |
20090174345 | POWER SUPPLY CIRCUIT - A power supply circuit is proposed for supplying current to a pair of white LEDs connected in series. The circuit comprises a DC-DC power converter, with a charge pump coupled to the output of the DC-DC power converter. A super capacitor is coupled to the charge pump to be charged to a voltage on top of the converter output in a first mode of operation. The super capacitor is discharged through the pair of LEDs during a second mode of operation. A control stage is provided for switching between the first mode of operation and the second mode of operation. | 07-09-2009 |
20090167264 | DC-DC CONVERTER USABLE FOR DUAL VOLTAGE SUPPLY - A converter has a single inductor with a first terminal connectable to a first terminal of the supply input through a first power transistor and a second terminal connectable to a second terminal of the supply input through a second power transistor. A first rectifier element connects the first terminal of the inductor with a first output terminal, and a second rectifier element connects the second terminal of the inductor with a second output terminal. A resistive voltage divider is connected between the first and second output terminals. A control circuit uses an input from the voltage divider as a reference input voltage and provides an output current to the second terminal of the supply input in response to any voltage difference between the reference input voltage and the second terminal of the supply input. This provides a virtual common reference potential at the second terminal of the supply input, which is thus a common ground (GND) terminal. In the ON phase of both power transistors, the inductor is charged with current from the supply input. In the OFF phase (both power transistors are OFF), the energy stored in the inductor is supplied to both of the positive and the negative supply output through the rectifier elements, the output current in fact flowing almost exclusively between the positive and negative supply outputs. Thus, in the OFF phase, the inductor is entirely isolated from the supply input and the supply outputs are in no way affected by any transients or fluctuations in the supply input voltage. | 07-02-2009 |
20090153300 | RFID TRANSPONDER WITH HIGH DOWNLINK DATA RATE - A RFID transponder includes a high quality factor antenna, and a resonance capacitor coupled to the high quality factor antenna for providing a resonant circuit. The RFID transponder has a symmetrical RF input stage and is adapted to vary the quality factor of the resonant circuit such that the quality factor is low during downlink data transmission when the RFID transponder receives data through the antenna, and the quality factor is high during uplink data transmission, when the RFID transponder transmits data. | 06-18-2009 |
20090153240 | COMPARATOR WITH SENSITIVITY CONTROL - A comparator has a differential input stage, a current source coupled to the differential input stage for providing a tail current to one side of the differential input stage, and a differential load coupled to the differential pair and having at least one diode coupled load transistor per differential side. A load current through either one of the at least one diode coupled load transistor on either differential side is mirrored with a current mirror configuration to provide a current be fed to a respective node, each node being coupled to a respective variable biasing current source and a respective other side of the differential input stage, so as to provide a variable positive feedback to the differential input stage. | 06-18-2009 |
20090153226 | HIGH-SIDE DRIVER FOR PROVIDING AN OFF-STATE IN CASE OF GROUND LOSS - An electronic device has circuitry for driving a high side switch. The circuitry has a high side driver including a first switch and a second switch being coupled to each other by a driver output node. The driver output node is adapted to be coupled to a control input of the high side switch. The first switch is coupled to a driver high voltage level and the second switch is coupled to ground for alternately pulling the driver output node to either the driver high voltage level or to ground so as to turn the high side switch on and off. A diode element is coupled between the driver output node and the second switch in a forward direction from the driver output node to the switch. | 06-18-2009 |
20090153198 | LOW-LEAKAGE SWITCH FOR SAMPLE AND HOLD - An integrated electronic device includes a sample and hold stage. The sample and hold stage has a sampling capacitor (C) for an input voltage at an input node (Vin), a first switch (S | 06-18-2009 |
20090147947 | DIGITAL-ENCRYPTION HARDWARE ACCELERATOR - An electronic device for encrypting and decrypting data blocks of a message having n data blocks in accordance with the data encryption standard (DES) is provided. The electronic device has a first data processing channel having a first processing stage for performing encryption and decryption of data blocks of a predefined length, and a first input data buffer coupled to a data input and to the first processing stage, and a second data processing channel having a second processing stage for performing encryption and decryption of data blocks, a second data input buffer coupled to an output of the first processing stage and to the second processing stage. The electronic device also has a control stage (FSM) for controlling the first processing stage and the second processing stage, so as to perform an encryption or decryption step with the second processing stage on an encrypted/decrypted data block output from the first processing stage. The control stage is adapted to control the first processing stage to perform data encryption or decryption according to the data encryption standard on each block and to control the second processing stage to compute a message authentication code over the encrypted or decrypted message received from the first processing stage block-by-block. | 06-11-2009 |
20090121644 | ADAPTIVE ALGORITHM FOR CAMERA FLASH LED POWER CONTROL VS. BATTERY IMPEDANCE, STATE OF DISCHARGE (SOD), AGING, TEMPERATURE EFFECTS - A method for driving a light-emitting semiconductor is provided. A supply voltage is converted into a secondary output voltage for supplying the light-emitting semiconductor with an output voltage. A level for the supply voltage at the beginning of a high current phase of the light-emitting semiconductor is sensed. A threshold voltage level for the supply voltage level is determined based on the sensed level. The high current phase with the light-emitting semiconductor is stated. The sensed level is continuously compared with the threshold voltage level, and an output current through the light-emitting semiconductor is controlled such that the sensed level does not drop below the threshold voltage level. | 05-14-2009 |
20090108775 | LED DRIVER WITH ADAPTIVE ALGORITHM FOR STORAGE CAPACITOR PRE-CHARGE - A method is provided for driving a plurality of light emitters in a plurality of output paths with each output path including at least one light emitter. The method includes the steps of applying a supply voltage level to a plurality of output paths; generating a current for each path during a period of a predetermined length for the output path; sensing a current level for each output path during the period; comparing each sensed current level with a reference level; increasing the supply voltage level if the sensed current level is lower than the reference level; determining a lowest supply voltage level for the worst case output path; and using the lower supply voltage level as a common supply voltage level for all output paths. | 04-30-2009 |
20090096388 | DRIVER FOR LIGHT EMITTING SEMICONDUCTOR DEVICE - An electronic device is provided comprising a driver for light emitting semiconductor devices. The driver includes a first MOS transistor (MN | 04-16-2009 |
20090091331 | CIRCUIT BOARD AND METHOD FOR AUTOMATIC TESTING - A circuit board (CB) and method for automatic testing of an electronic device under test (DUT). The circuit board (CB) has a first terminal (T | 04-09-2009 |
20090072755 | LIGHT-EMITTING SEMICONDUCTOR DEVICE DRIVER AND METHOD - An electronic device includes circuitry for driving a light-emitting diode (LED) or other light-emitting semiconductor device. The circuitry includes a first switch (NM | 03-19-2009 |
20090067487 | INCREASING PWM RESOLUTION BY MODULATION - A method for generating a pulse width modulated (PWM) signal includes determining a PWM period and/or a pulse width of the pulse width modulated signal by counting the number of clock cycles of a reference clock signal and by switching the pulse width modulated signal when a predetermined number of clock cycles is reached. The reference clock signal comprises clock cycles of at least a first clock period and a second clock period. The first clock period and the second clock period differ by an amount of time, which is substantially smaller than both half of the first clock period and half of the second clock period. | 03-12-2009 |
20090066423 | SPREAD SPECTRUM CLOCKING IN FRACTIONAL-N PLL - A combined spread spectrum and fractional-N phase locked loop circuit comprises a chain of a reference clock divider, a phase-frequency detector, a charge pump with loop filter, a voltage controlled oscillator that provides multiple phase outputs, and a feedback loop from the multiple phase outputs of the voltage controlled oscillator to a feedback input of the phase-frequency detector. The feedback loop includes a phase selector, a feedback divider and a control block with an output controlling said phase selector to select a particular phase as an input to the feedback divider. The control block includes spread spectrum logic circuitry receiving an input from the output of the phase selector and providing a directional control output signal and a phase step control signal. The control block further includes fractional logic circuitry receiving an input from the output of the phase selector and providing a phase step control signal. A logic interface circuit combines the directional control output signal from the spread spectrum logic circuitry, the phase step control signal from the spread spectrum logic circuitry, and the phase step control signal from the fractional logic circuitry. This means that when both of the spread spectrum logic circuitry and the fractional logic circuitry request a phase step in the same feedback clock period in the same direction, a single phase step control signal is passed to the phase selector and a further phase step control signal is passed to the phase selector in a subsequent clock period. Further, when the spread spectrum logic circuitry and the fractional logic circuitry request a phase step in the same feedback clock period in opposite directions, no phase step control signal is passed to the phase selector. | 03-12-2009 |
20090058375 | SELF-OSCILLATING CONVERTER - A converter has a main feedback path and two auxiliary feedback paths from an output node to an auxiliary differential input pair of a comparator. The auxiliary feedback paths have different RC time constants so that a differential ramp signal is effectively applied to the auxiliary differential inputs of the comparator. The circuit design compensates for a negligibly small equivalent series resistor of an output capacitor so that modern capacitors may be used without compromising the stable oscillation of the converter. | 03-05-2009 |
20090044050 | WATCHDOG MECHANISM WITH FAULT RECOVERY - A method for handling watchdog events of an electronic device includes detecting a watchdog fault in a normal mode, which is a watchdog event in which a watchdog trigger is not correctly serviced; entering from the normal mode into a first escalation level of nx escalation levels upon detection of the watchdog fault, wherein nx is an integer equal to or greater than 1; detecting correct watchdog events, which are watchdog events in which a watchdog trigger is correctly serviced; and concurrently detecting watchdog faults, leaving the first escalation level if a first escalation condition is met, and recovering in a recovering step back from any of the nx escalation levels to a previous level or mode, if a de-escalation condition is met. An electronic device embodiment includes a CPU and program instructions for carrying out the method. | 02-12-2009 |
20090039845 | METHOD AND APPARATUS FOR POWER MANAGEMENT OF A LOW DROPOUT REGULATOR - A method of switching a low dropout regulator includes determining an actual active time of a power request from an electronic device; enabling the low dropout regulator in response to said power request at a time corresponding to a start of the actual active time of the power request for an active enabled time having a duration at least the same as the actual active time and long enough to sufficiently settle the output voltage of the low dropout regulator; and disabling the low dropout regulator. In embodiments, the active enabled time is prolonged beyond the actual active time of the power request for all or at least some power requests. An electronic device includes circuits for controlling the switching of a low dropout in the described manner. | 02-12-2009 |
20090037770 | WATCHDOG MECHANISM WITH FAULT ESCALATION - A method for handling watchdog events of an electronic device includes detecting a watchdog fault in a normal mode, which is a watchdog event in which a watchdog trigger is not correctly serviced; entering from the normal mode into a first escalation level of nx escalation levels upon detection of the watchdog fault, wherein nx is an integer equal to or greater than 1; detecting correct watchdog events, which are watchdog events in which a watchdog trigger is correctly serviced; and concurrently detecting watchdog faults, leaving the first escalation level if a first escalation condition is met. An electronic device embodiment includes a CPU and program instructions for carrying out the method. | 02-05-2009 |
20090033411 | Oscillation Maintentance Circuit For Half Duplex Transponder - An oscillation maintenance circuit for a half-duplex transponder that has an LC resonant circuit, a storage capacitor and a rectifier connected to charge the storage capacitor with a rectified oscillation signal, having an end-of-burst detector providing an end-of-burst signal when the amplitude of the oscillation signal has dropped below a predetermined threshold. A clock regenerator provides a clock signal derived from the oscillation signal. Switching means controlled by the clock signal in the presence of the end-of-burst signal connect the storage capacitor with LC resonant circuit through at least one current limiting resistor during part of the period of the clock signal, in such a manner that energy is fed into the LC resonant circuit. | 02-05-2009 |
20090027251 | SAR ANALOG-TO-DIGITAL CONVERTER WITH LARGE INPUT RANGE - A method for analog-to-digital conversion is provided using successive approximation and a plurality of capacitors comprising a first set of capacitors and a second set of capacitors, a first side of each of the plurality of capacitors being coupled to a common node. The method comprises sampling an input voltage on the first set of capacitors, after the step of sampling leaving a side of at least one capacitor of the first set of capacitors floating, coupling a capacitor of the first set of capacitors, which is not floating, with a capacitor of the second set of capacitors so as to redistribute the charge on the coupled capacitors, comparing the voltage on the common node with a comparator reference voltage level to receive a comparison result to be used for a bit decision, and switching the floating side of the floating capacitor of the first set of capacitors to either a first reference voltage or a second reference voltage in accordance with the bit decision. | 01-29-2009 |
20090009151 | REFERENCE VOLTAGE GENERATOR WITH BOOTSTRAPPING EFFECT - An integrated electronic device for generating a reference voltage. The circuitry has a bias current generator for generating a first bias current, a diode element coupled to the bias current generator and fed by a second bias current derived from the first bias current for converting the second bias current into a reference voltage across the diode element, a supply voltage pre-regulator stage for regulating the supply voltage used for the bias current generator, and an output buffer coupled to the reference voltage for providing a low impedance output, wherein the reference voltage is coupled to the supply pre-regulator stage for biasing the supply pre-regulator stage by the reference voltage. | 01-08-2009 |
20090009150 | REFERENCE VOLTAGE GENERATOR WITH BOOTSTRAPPING EFFECT - An integrated electronic device for generating a reference voltage. The circuitry has a bias current generator for generating a first bias current, a diode element coupled to the bias current generator and fed by a second bias current derived from the first bias current for converting the second bias current into a reference voltage across the diode element, a supply voltage pre-regulator stage for regulating the supply voltage used for the bias current generator, and an output buffer coupled to the reference voltage for providing a low impedance output, wherein the reference voltage is coupled to the supply pre-regulator stage for biasing the supply pre-regulator stage by the reference voltage. | 01-08-2009 |
20080313485 | DATA PIPELINE WITH LARGE TUNING RANGE OF CLOCK SIGNALS - The invention relates to a data pipeline comprising a first stage with a data input for receiving a digital data input signal, a clock input and a data output, and a first bi-stable element being adapted to be switched in response to an edge of a first clock signal, and a dynamic latch stage comprising an input transfer element, and a second bi-stable element coupled between the input transfer element and a dynamic latch data output, wherein the input transfer element is adapted to be switched by a second clock signal and a delayed second clock signal, which is delayed with respect to the second clock signal by a first period of time being shorter than half a period of the second clock signal, such that the input transfer element allows signal transfer only during the first period of time. | 12-18-2008 |
20080309421 | PHASE LOCKED LOOP WITH TWO-STEP CONTROL - A phase locked loop has a digitally controlled oscillator (DCO) for generating a DCO output signal (f | 12-18-2008 |
20080309385 | ELECTRONIC DEVICE AND METHOD FOR ON CHIP SKEW MEASUREMENT - The invention relates to an integrated electronic device for digital signal processing, which includes a phase locked loop for generating an output clock signal based on a reference clock input signal, multiple outputs for providing multiple representatives of the output clock signal, a stage for generating a phase shifted output clock signal having multiple phases spanning one clock period of the output clock signal, a register having multiple units each coupled by a data input to a representative of the output clock signal, and to the phase shifted output clock signal for storing single bit values in response to an edge of the shifted output clock signal, wherein the stage for generating the phase shifted output clock is controlled to selectively shift the phase of the output clock and circuitry for reading out the stored single bit values from the register is provided in order to determine the output skew of the output clock signals based on the read out single bit value. | 12-18-2008 |
20080309319 | Electronic Device and Method for on Chip Jitter Measurement - The present invention relates to an integrated electronic device for digital signal processing, which includes a reference clock input for receiving a reference clock, a phase locked loop (PLL), a phase interpolator (PI) coupled to the phase locked loop (PLL) for shifting a phase of an output clock signal of the PLL in a stepwise manner so as to generate a shifted output clock signal (PHI_out), a logic stage for determining the state of the reference clock signal (REF_CLK) multiple times during an edge of the shifted output clock for each phase shift, a storing means for storing information whether or not the determined state of the reference clock signal (REF_CLK) is stable for a phase of the shifted output clock signal (PHI_out), and an interface configured to read out the stored information for determining the jitter of the shifted output clock signal (PHI_OUT). | 12-18-2008 |
20080301485 | REGISTER WITH PROCESS, SUPPLY VOLTAGE AND TEMPERATURE VARIATION INDEPENDENT PROPAGATION DELAY PATH - The digital data register has a plurality of parallel matched data paths, each data path having a data input for receiving a digital data input signal (CA/CNTRL), an output driver with a data output providing a digital data output signal (Q_CA/CNTRL) for application to an associated memory module and a flip-flop (FF1) arranged between the data input and the data output. The data register further comprises a clock input for receiving a clock input signal (CLK), a clock output for providing an output clock signal (Q_CLKn, Q_NCLKn) to the memory modules, a phase locked loop (PLL) with a clock input (REF), a feedback input (FB), a feedback output providing a feedback output signal (Q_NFB) and a clock output providing a clock output signal (Q_CLK, QNCLK). In addition a flip-flop (FF1 DELAY) and output driver replica are matched with the flip-flop and output driver of the data paths. the flip-flops (FF1) of the data paths and the flip-flop (FF1 DELAY) of the replica are clocked by the feedback signal applied to the feedback input (FB) of the phase locked loop (PLL). The phase locked loop (PLL) includes a phase aligner with a phase interpolator. The phase interpolator has an output that provides the output clock signal (Q_CLKn, Q_NCLKn) to the memory modules through a flip-flop (FF1 DELAY) and output driver matched with the flip-flop and output driver of the data paths. A phase frequency detector (PFD) has a first input (REF) coupled to the output of the output driver replica and a second input (SYS) coupled to the clock output. The phase interpolator is controlled by the output of the phase frequency detector (PFD). The proposed data register satisfies the three requirements of: (i) setup and hold timing on the pre-register side, (ii) clock centering on the post-register side, and (iii) constant propagation delay time (tpd) over PVT variations from the clock input to the data output. | 12-04-2008 |
20080284529 | METHOD AND APPARATUS OF A RING OSCILLATOR FOR PHASE LOCKED LOOP (PLL) - The present invention relates to a ring oscillator including a delay stage, the delay stage includes a differential pair of input transistor, a variable resistive load coupled to the transistor, a differential output between the variable resistive load and the corresponding input transistor, a variable current source coupled to the differential pair of transistors for variably setting a bias current through the differential pair of transistors, and an input coupled to the variable resistive load and the variable current source for receiving an configuration signal, wherein the variable resistive load and the variable current source are changed in response to the configuration signal, wherein the bias current of the variable current source increases and the variable resistive load decreases, and vice versa. | 11-20-2008 |
20080265967 | INTEGRATED CIRCUIT FOR CLOCK GENERATION FOR MEMORY DEVICES - A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK | 10-30-2008 |
20080265963 | CASCADED PHASE SHIFTER - The invention relates to a phase shifter which has at least two cascaded delay stages ( | 10-30-2008 |
20080265952 | Gate Driver Circuit for Power Transistor - A circuit arrangement with a gate driver circuit for a power transistor is disclosed which is suitable for low voltage applications, permitting a rail-to-rail output without a loss in speed/bandwidth, which is very simple, low cost, low current and area efficient. The gate driver circuit comprises a drain follower with a MOS driver transistor having the gate connected to an interconnection node of a capacitive divider. A first capacitor of the capacitive divider is connected between the drain and the gate and a second capacitor is connected between the gate and an input of the gate driver circuit. The gate driver has the required low impedance for driving the gate of the power transistor. | 10-30-2008 |
20080258795 | LOW POWER OSCILLATOR - A CMOS low frequency oscillator circuit comprising an amplifier ( | 10-23-2008 |
20080258697 | DYNAMIC GATE DRIVE VOLTAGE ADJUSTMENT - A DC-DC buck converter comprises a high-side power FET having a current path connected in series between an input terminal and an inductor connected to an output terminal supplying an output current to a load. The converter further comprises a low-side power FET having a current path connected between a reference terminal and an interconnection node of the high-side power FET with the inductor. The converter has a pulse width modulation controller receiving a feedback signal from the output terminal and providing pulse width modulated signals, and a gate driver circuit that receives the pulse width modulated signals from the pulse width modulation controller and applies pulse width modulated drive signals to the gates of the power FETs. The gate driver circuit supplies the drive signals to the gates of the power FETs at a variable voltage level adjusted in response to at least the output current, minimizing the power dissipation of the gate driver circuit. | 10-23-2008 |
20080253414 | VCSEL DRIVER - The invention provides a driver for a semiconductor light emitting device, in particular a vertical cavity surface emitting laser (VCSEL) which includes a delay buffer for generating an output signal as a delayed version of an input signal; a pulse generation stage coupled in parallel with the delay buffer and adapted to produce selectively positive and negative output pulses starting concurrently with respective positive and negative edges of the output signal of the buffer; and a summer for summing the output signal and the pulses. | 10-16-2008 |
20080252390 | CRYSTAL OSCILLATOR CIRCUIT - A crystal oscillator circuit includes a capacitive load stage (C | 10-16-2008 |
20080251007 | METHOD OF CONTROLLING AN EPITAXIAL GROWTH PROCESS IN AN EPITAXIAL REACTOR - A method of controlling an epitaxial growth process in an epitaxial reactor and a system for controlling an epitaxial growth process in an epitaxial reactor. | 10-16-2008 |
20080243976 | MULTIPLY AND MULTIPLY AND ACCUMULATE UNIT - The present invention relates to a multiply apparatus and a method for multiplying a first operand consisting of na bits and a second operand consisting of nx bits. In one embodiment the multiply apparatus comprising a CSA (CSA) unit with nx rows each comprising na AND gates for calculating a single bit product of two single bit input values and adder cells for adding results of a preceding row to a following row and a last output row for outputting a carry vector and a sum vector, and logic circuitry for selectively inverting the single bit products at the most significant position of the nx−1 first rows and at the na−1 least significant positions of the output row in response to a first configuration signal before inputting the selectively inverted single bit products to respective adder cells for switching the CSA unit selectively between processing of signed two's complement operands and unsigned operands in response to the first configuration signal. In one embodiment the method comprising outputting a carry vector and a sum vector, and adding the carry vector and the sum vector provided by the output row of the CSA unit via a CPA unit consisting of a row of na full adder cells, wherein the carry input of the CPA unit is coupled to receive a first configuration signal to switch between processing of signed and unsigned two's complement operands. | 10-02-2008 |
20080238387 | DUAL MODE REGULATION LOOP FOR SWITCH MODE POWER CONVERTER - The invention relates to a DC-DC converter, which includes a power stage driven by a pulse width modulator, a first error amplifier with a first input coupled to a first reference voltage source and a second input coupled to a current sink through which a current is fed from an output of the power stage to receive a first feedback voltage (FB | 10-02-2008 |
20080215805 | DIGITAL DATA BUFFER - A data buffer with a mechanism to optimize the setup/hold timing at the second flip-flop (or data register) so as to reduce the propagation delay time. The data buffer has a data path with a data input for receiving a digital data input signal, a clock input for receiving a clock input signal and a data output providing a digital data output signal for application to a data destination device, e.g. a RAM module in a memory system. The data buffer further has a clock output for providing an output clock signal to the data destination device and a phase locked loop (PLL) with a phase aligner and a first and second data register with respective clock inputs. The data input of the first data register is selectively coupled to the data input of the buffer or to a reference data input through a multiplexer. A reference data path is provided in parallel with the data path including a third data register with a data input to which the reference data input is coupled and a reference data output. A second clock output of the phase locked loop provides a clock signal shifted in phase by the phase aligner with respect to a feedback clock signal for application to the clock input of the second data register and to the clock input of the third data register. The data output of the second data register and the reference data output of the third data register are applied to inputs of a logic circuit that has a control output. The phase aligner in the phase locked loop has associated control circuitry with a control input coupled to the control output of the logic circuit. A learn cycle control signal is applied in parallel to the multiplexer and to the control circuitry of the phase aligner causing the phase aligner in a learn cycle to adjust the phase of the clock signal at the second clock output of the phase locked loop so as to optimise the setup/hold timing at the data input of the second data register. | 09-04-2008 |
20080215262 | POLYPHASE ELECTRIC ENERGY METER - A polyphase electric energy meter comprises a microcontroller with a front end that converts analog current input signals and analog voltage input signals to digital current and voltage samples for processing by the microcontroller. The front end includes separate input channels, each for one of the current input signals with a sigma-delta modulator followed by a decimation filter. The front end further includes a common input channel for all voltage input signals with a multiplexer, an analog-to-digital converter and a de-multiplexer. The separate input channels and the common input channel provide the digital current and voltage samples for processing by the microcontroller. | 09-04-2008 |