ALPHA & OMEGA SEMICONDUCTOR, LTD Patent applications |
Patent application number | Title | Published |
20140239383 | WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE - Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste. | 08-28-2014 |
20120293144 | VOLTAGE/CURRENT CONTROL APPARATUS AND METHOD - A voltage/current control apparatus and method are disclosed. The apparatus includes a low-side field effect transistor (FET) having a source, a gate and a drain, a high-side field effect transistor (FET) having a source, a gate and a drain, a gate driver integrated circuit (IC), a sample and hold circuit, and a comparator configured to produce a trigger signal at the output when a sum of the first and second input signals is equal to a sum of the third and fourth input signals, wherein the trigger signal is configured to trigger a beginning of a new cycle by turning the gate of the high-side FET “on” and the gate of the low-side FET “off”. | 11-22-2012 |
20120001176 | ETCH DEPTH DETERMINATION STRUCTURE - A semiconductor device wafer includes a test structure. The test structure includes a layer of material having an angle-shaped test portion disposed on at least a portion of a surface of the semiconductor wafer. A ruler marking on the surface of the semiconductor wafer proximate the test portion is adapted to facilitate measurement of a change in length of the test portion. | 01-05-2012 |
20110316090 | BOOST CONVERTER WITH INTEGRATED HIGH POWER DISCRETE FET AND LOW VOLTAGE CONTROLLER - A boost converter for high power and high output voltage applications includes a low voltage controller integrated circuit and a high voltage, vertical, discrete field effect transistor, both of which are packed in a single package on separate electrically isolated die pads. | 12-29-2011 |
20110278665 | HIGH-MOBILITY TRENCH MOSFETS - High-mobility vertical trench DMOSFETs and methods for manufacturing are disclosed. A source region, a drain region or a channel region of a high-mobility vertical trench DMOSFET may comprise silicon germanium (SiGe) that increases the mobility of the charge carriers in the channel region. In some embodiments the channel region may be strained to increase channel charge carriers mobility. | 11-17-2011 |
20110227155 | INTEGRATION OF A SENSE FET INTO A DISCRETE POWER MOSFET - A main FET and one or more sense FETs are formed in a common substrate. The main FET and sense FET(s) include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and sense FET(s). An electrical isolation may be between the gate terminals of the main FET and the sense FET(s). A sense pad in electrical contact with the source of the one or more sense FETs does not overlap an area of the device containing the sense FET(s). It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 09-22-2011 |
20100163979 | TRUE CSP POWER MOSFET BASED ON BOTTOM-SOURCE LDMOS - A semiconductor package may comprise a semiconductor substrate, a MOSFET device having a plurality cells formed on the substrate, and a source region common to all cells disposed on a bottom of the substrate. Each cell comprises a drain region on a top of the semiconductor device, a gate to control a flow of electrical current between the source and drain regions, a source contact proximate the gate; and an electrical connection between the source contact and source region. At least one drain connection is electrically coupled to the drain region. Source, drain and gate pads are electrically connected to the source region, drain region and gates of the devices. The drain, source and gate pads are formed on one surface of the semiconductor package. The cells are distributed across the substrate, whereby the electrical connections between the source contact of each device and the source region are distributed across the substrate. | 07-01-2010 |
20090322461 | PLANAR GROOVED POWER INDUCTOR STRUCTURE AND METHOD - An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil. | 12-31-2009 |
20090294934 | CONDUCTIVE CLIP FOR SEMICONDUCTOR DEVICE PACKAGE - A clip for a semiconductor device package may include two or more separate electrically conductive fingers electrically connected to each other by one or more electrically conductive bridges. A first end of at least finger is adapted for electrical contact with a lead frame. The bridges are adapted to provide electrical connection to a top semiconductor region of a semiconductor device and may also to provide heat dissipation path when a top surface of the fingers is exposed. A semiconductor device package may include the clip along with a semiconductor device and a lead frame. The semiconductor device may have a first and semiconductor regions on top and bottom surfaces respectively. The clip may be electrically connected to the top semiconductor region at the bridges and electrically connected to the lead frame at a first end of at least one of the fingers. | 12-03-2009 |
20090273328 | VOLTAGE/CURRENT CONTROL APPARATUS AND METHOD - A voltage/current control apparatus and method are disclosed. The apparatus includes a low-side field effect transistor (FET) having a source, a gate and a drain, a high-side field effect transistor (FET) having a source, a gate and a drain, a gate driver integrated circuit (IC), a sample and hold circuit, and a comparator configured to produce a trigger signal at the output when a sum of the first and second input signals is equal to a sum of the third and fourth input signals, wherein the trigger signal is configured to trigger a beginning of a new cycle by turning the gate of the high-side FET “on” and the gate of the low-side FET “off”. | 11-05-2009 |
20090250770 | INTEGRATION OF A SENSE FET INTO A DISCRETE POWER MOSFET - A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and the one or more sense FETs. An electrical isolation is disposed between the gate terminals of the main FET and the one or more sense FETs. Embodiments of this invention may be applied to both N-channel and P-channel MOSFET devices. | 10-08-2009 |
20090242973 | SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON - A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. | 10-01-2009 |
20090194880 | WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE - Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste. | 08-06-2009 |
20090166621 | RESISTANCE-BASED ETCH DEPTH DETERMINATION FOR SGT TECHNOLOGY - A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut D | 07-02-2009 |
20090160045 | WAFER LEVEL CHIP SCALE PACKAGING - A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip. | 06-25-2009 |
20090128968 | STACKED-DIE PACKAGE FOR BATTERY POWER MANAGEMENT - A stacked-die package for battery protection is disclosed. The battery protection package includes a power control integrated circuit (IC) stacked on top of integrated dual common-drain metal oxide semiconductor field effect transistors (MOSFETs) or two discrete MOSFETs. The power control IC is either stacked on top of one MOSFET or on top of and overlapping both two MOSFETs. | 05-21-2009 |
20090114949 | HIGH-MOBILITY TRENCH MOSFETS - High-mobility vertical trench DMOSFETs and methods for manufacturing are disclosed. A source region, a drain region or a channel region of a high-mobility vertical trench DMOSFET may comprise silicon germanium (SiGe) that increases the mobility of the charge carriers in the channel region. In some embodiments the channel region may be strained to increase channel charge carriers mobility. | 05-07-2009 |
20090079409 | VOLTAGE/CURRENT CONTROL APPARATUS AND METHOD - A voltage/current control apparatus and method are disclosed. The apparatus includes a low-side field effect transistor (FET) having a source, a gate and a drain, a high-side field effect transistor (FET) having a source, a gate and a drain, a gate driver integrated circuit (IC), a sample and hold circuit, and a comparator configured to produce a trigger signal at the output when a sum of the first and second input signals is equal to a sum of the third and fourth input signals, wherein the trigger signal is configured to trigger a beginning of a new cycle by turning the gate of the high-side FET “on” and the gate of the low-side FET “off”. | 03-26-2009 |
20090057869 | CO-PACKAGED HIGH-SIDE AND LOW-SIDE NMOSFETS FOR EFFICIENT DC-DC POWER CONVERSION - A circuit package assembly is disclosed. The assembly includes a conductive substrate; a high-side n-channel metal oxide semiconductor field effect transistor (NMOSFET) having a source on a side facing a surface of the conductive substrate and in electrical contact therewith and a low-side standard n-channel metal oxide semiconductor field effect transistor (NMOSFET) having a drain on a side facing the conductive substrate and in electrical contact therewith. Co-packaging of high-side and low-side NMOSFETs in this manner may reduce package size and parasitic inductance and capacitance compared to conventional packaging. | 03-05-2009 |
20080304306 | HIGH VOLTAGE AND HIGH POWER BOOST CONVETER WITH CO-PACKAGED SCHOTTKY DIODE - A high voltage and high power boost converter is disclosed. The boost converter includes a boost converter IC and a discrete Schottky diode, both of which are co-packaged on a standard single common die pad. | 12-11-2008 |
20080304305 | BOOST CONVERTER WITH INTEGRATED HIGH POWER DISCRETE FET AND LOW VOLTAGE CONTROLLER - A boost converter for high power and high output voltage applications includes a low voltage controller integrated circuit and a high voltage, vertical, discrete field effect transistor, both of which are packed in a single package. | 12-11-2008 |
20080272371 | RESISTANCE-BASED ETCH DEPTH DETERMINATION FOR SGT TECHNOLOGY - A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut D | 11-06-2008 |
20080233748 | ETCH DEPTH DETERMINATION FOR SGT TECHNOLOGY - A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the layer of material. The resist mask does not cover the trench. The layer of material is isotropically etched. An etch depth may be determined from a characteristic of etching of the material underneath the mask. Such a method may be used for forming SGT structures. The wafer may comprise a layer of material disposed on at least a portion of a surface of semiconductor wafer; a resist mask comprising an angle-shaped test portion disposed over a portion of the layer of material; and a ruler marking on the surface of the substrate proximate the test portion. | 09-25-2008 |