Xilinx, Inc. Patent applications |
Patent application number | Title | Published |
20160134289 | POWER MANAGEMENT SYSTEM FOR INTEGRATED CIRCUITS - An apparatus includes a plurality of programmable hardware resources and an analog-to-digital converter (ADC) disposed on an IC die. The ADC is configured to quantize values of one or more analog parameters of the IC die. The apparatus also includes a configuration control circuit configured to program the programmable hardware resources in response to a set of configuration data. The programmable hardware resources are programmed to implement a set of circuits specified by the configuration data and to connect the ADC to respective nodes of the IC die for sampling the analog parameters. The apparatus also includes an interface circuit coupled to the ADC and configured to generate a control signal based on quantized values of the one or more analog parameters from the ADC. The interface circuit outputs the control signal to a power supply coupled to a power terminal of the IC die. | 05-12-2016 |
20160133305 | CALIBRATION IN A CONTROL DEVICE RECEIVING FROM A SOURCE SYNCHRONOUS INTERFACE - In an example, a control device includes a data path, a clock path, a multiplexing circuit, and a calibration unit. The data path comprises a data delay unit coupled to a data input of a sampling circuit. The clock path comprises a clock delay unit coupled to a clock input of the sampling circuit. The multiplexing circuit selectively couples a reference clock or a data bus to an input of the data delay unit, and selectively couples the reference clock or a source clock to an input of the clock delay unit. The calibration unit is coupled to a data output of the sampling circuit. The calibration unit is operable to adjust delay values of the data delay unit and the clock delay unit based on the data output of the sampling circuit to establish and maintain a relative delay between the data path and the clock path. | 05-12-2016 |
20160118988 | CIRCUITS FOR AND METHODS OF CONTROLLING POWER WITHIN AN INTEGRATED CIRCUIT - A circuit for controlling power within an integrated circuit comprises a plurality of circuit blocks; a global control signal routed within the integrated circuit; and a plurality of power control blocks. Each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a first input coupled to receive a reference voltage and a second input coupled to receive the global control signal. The global control signal enables, for each circuit block, the coupling of the reference voltage to the corresponding circuit block. A method of controlling power within an integrated circuit is also disclosed. | 04-28-2016 |
20160111139 | DYNAMIC SELECTION OF OUTPUT DELAY IN A MEMORY CONTROL DEVICE - In an example, a memory control device includes an output circuit, an output delay unit, and a write-levelization controller. The output circuit is coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic random access memory (SDRAM) system having a plurality of ranks. The output delay unit is coupled to apply an output delay to a bitstream to be transmitted to generate the output signal. The output delay includes an aggregate of a de-skew delay and a write-levelization delay. The write-levelization delay controller is coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks. The de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions. | 04-21-2016 |
20160098059 | CIRCUITS FOR AND METHODS OF PROCESSING DATA IN AN INTEGRATED CIRCUIT DEVICE - A circuit for processing data in an integrated circuit device comprises a selection circuit; a first register coupled to a first output of the selection circuit; a second register implemented as a latch and coupled to a second output of the selection circuit; and a signal line coupled between the output of the first register and an input of the selection circuit. The selection circuit enables the coupling of an output signal of the first register to an input of the second register. A method of processing data in an integrated circuit device is also disclosed. | 04-07-2016 |
20160097805 | IN-DIE TRANSISTOR CHARACTERIZATION IN AN IC - In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors. | 04-07-2016 |
20160085449 | MANAGING MEMORY IN A MULTIPROCESSOR SYSTEM - In an example, a circuit to manage memory between a first and second microprocessors each of which is coupled to a control circuit, includes: first and second memory circuits; and a switch circuit coupled to the first and second memory circuits, and memory interfaces of the first and second microprocessors, the switch circuit having a mode signal as input. The switch is configured to selectively operate in one of a first mode or a second mode based on the mode signal such that, in the first mode, the switch circuit couples the first memory circuit to the memory interface of the first microprocessor and the second memory circuit to the memory interface of the second microprocessor and, in the second mode, the switch circuit selectively couples the first or second memory circuits to the memory interface of either the first or second microprocessor. | 03-24-2016 |
20160080008 | LANE-TO-LANE DE-SKEW FOR TRANSMITTERS - In a method relating generally to starting a plurality of transmitters, a sequence is initiated for each of the plurality of transmitters having corresponding data buffers. Latency is set for each of the data buffers responsive to execution of the sequence. The sequence includes: obtaining a read address associated with a read clock signal; obtaining a write address associated with a write clock signal; determining a difference between the read address and the write address; asserting a flag signal associated with the difference; and adjusting the read clock signal to change the difference to locate a change of state location for the flag signal to set the latency for a data buffer of the data buffers. | 03-17-2016 |
20160064328 | MULTI-CHIP SILICON SUBSTRATE-LESS CHIP PACKAGING - Examples generally provide a stacked silicon interconnect product and method of manufacture. The stacked silicon interconnect product includes a silicon substrate-less interposer comprising a plurality of metallization layers, wherein at least one metallization layer includes a plurality of metal segments separated by dielectric material. The stacked silicon interconnect product also includes a first die coupled to a first side of the silicon substrate-less interposer via a first plurality of microbumps. The stacked silicon interconnect product further includes a second die coupled to a second side of the silicon substrate-less interposer via a second plurality of microbumps, the second die communicatively coupled to the first die through a metallization layer of the plurality of metallization layers. | 03-03-2016 |
20160050017 | ADAPTIVE OPTICAL CHANNEL COMPENSATION - In an adaptation module relating generally to adaptive optical channel compensation, an analysis module is coupled to receive a first data signal and a second data signal and coupled to provide first information and second information. A comparison module is coupled to compare the first information and the second information to provide third information. An adjustment module is coupled to receive the third information to provide fourth information to compensate for distortion in the second data signal with reference to the first data signal. The second data signal is associated with a conversion of the first data signal to an optical signal for communication via an optical channel. | 02-18-2016 |
20160049940 | INTERCONNECT CIRCUITS HAVING LOW THRESHOLD VOLTAGE P-CHANNEL TRANSISTORS FOR A PROGRAMMABLE INTEGRATED CIRCUIT - An exemplary interconnect circuit for a programmable integrated circuit (IC) includes an input terminal coupled to receive from a node in the programmable IC, an output terminal coupled to transmit towards another node in the programmable IC, first and second control terminals coupled to receive from a memory cell of the programmable IC, and a complementary metal oxide semiconductor (CMOS) pass-gate coupled between the input terminal and the output terminal and to the first and second control terminals. The CMOS pass-gate includes a P-channel transistor configured with a low threshold voltage for a CMOS process used to fabricate the programmable IC. | 02-18-2016 |
20160049393 | CAPACITOR STRUCTURE IN AN INTEGRATED CIRCUIT - In an example, a capacitor in an integrated circuit (IC), includes: a first finger capacitor formed in at least one layer of the IC having a first bus and a second bus; a second finger capacitor formed in the at least one layer of the IC having a first bus and a second bus, where a longitudinal edge of the second bus of the second finger capacitor is adjacent a longitudinal edge of the first bus of the first finger capacitor and separated by a dielectric gap; and a first metal segment formed on a first layer above the at least one layer, the first metal segment being electrically coupled to the first bus of the first finger capacitor and increasing a width and a height of the first bus of the first finger capacitor. | 02-18-2016 |
20160026742 | SYSTEM-ON-CHIP INTELLECTUAL PROPERTY BLOCK DISCOVERY - An integrated circuit (IC) includes a bridge circuit configured to receive a first request from an external system, a discover circuit coupled to the bridge circuit and configured to process the first request received from the bridge circuit, and a memory map coupled to the discover circuit. The memory map stores a record for each of a plurality of Intellectual Property (IP) blocks implemented within the IC. The discover circuit is configured to generate a list of the IP blocks implemented within the IC from the records of the memory map responsive to the first request. The bridge circuit is configured to send the list to the external system. | 01-28-2016 |
20150358085 | OPTICAL COMMUNICATION CIRCUITS - Various apparatuses, circuits, systems, and methods for optical communication are disclosed. In some implementations an optical transmitter includes an optical data port configured to engage an optical fiber. The optical transmitter also includes a plurality of lasers coupled to the optical data port and configured and arranged to transmit respective optical signals over the optical fiber via the optical data port when selected. A control circuit of the optical transmitter is configured to receive an input data signal and encode the input data signal for transmission over the optical fiber by selecting one or more of the plurality of lasers at a time. The control circuit is configured to select one or more of the plurality of lasers at a time according to one of a frequency modulation encoding algorithm or an amplitude modulation encoding algorithm. | 12-10-2015 |
20150358084 | OPTICAL COMMUNICATION CIRCUITS - Various apparatuses, circuits, systems, and methods for optical communication are disclosed. In some implementations, an apparatus includes a package substrate and f first interposer mounted on the package substrate. The apparatus also includes a logic circuit and an optical interface circuit connected to the logic circuit via the first interposer. One of the optical interface circuit or the logic circuit is mounted on the first interposer. The optical interface circuit includes a driver circuit configured to receive electronic data signals from the logic circuit. The optical interface circuit also includes an optical transmitter circuit coupled to the driver circuit and configured to output optical data signals encoding the electronic data signals. | 12-10-2015 |
20150356027 | CIRCUITS FOR AND METHODS OF ENABLING THE ACCESS TO DATA - A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed. | 12-10-2015 |
20150348915 | INTEGRATED CIRCUIT PACKAGE WITH THERMAL NEUTRON SHIELDING - A semiconductor package with thermal neutron shielding is disclosed. The semiconductor package includes a substrate and an integrated circuit die disposed on the substrate. The semiconductor package also has a thermal neutron shield including a shielding material. The shielding material includes boron-10 and is configured to inhibit a portion of thermal neutrons that encounter the thermal neutron shield from passing through the thermal neutron shield. | 12-03-2015 |
20150347654 | EXTRACTING SYSTEM ARCHITECTURE IN HIGH LEVEL SYNTHESIS - Extracting a system architecture in high level synthesis includes determining a first function of a high level programming language description and a second function contained within a control flow construct of the high level programming description. The second function is determined to be a data consuming function of the first function. Within a circuit design, a port including a local memory is automatically generated. The port couples a first circuit block implementation of the first function to a second circuit block implementation of the second function within the circuit design. | 12-03-2015 |
20150311899 | VIRTUALIZATION OF PROGRAMMABLE INTEGRATED CIRCUITS - A programmable IC includes a plurality of programmable resources, a plurality of shareable logic circuits coupled to the plurality of programmable resources, and a virtualization circuit. The plurality of programmable resources includes programmable logic circuits and programmable routing resources. The virtualization circuit is configured to manage sharing of the plurality of shareable logic circuits between a plurality of user designs implemented in the plurality of programmable resources. The user designs are communicatively isolated from one another on the programmable IC. | 10-29-2015 |
20150282299 | THIN PROFILE METAL TRACE TO SUPPRESS SKIN EFFECT AND EXTEND PACKAGE INTERCONNECT BANDWIDTH - Embodiments of the invention generally provide an electronic device comprising an electrical interconnect component that includes an electrical trace. The electrical trace has geometric characteristics that serve to suppress the skin effect over a large band of frequency components. More specifically, the electrical trace has a thickness that is less than a skin depth for a particular chosen frequency component. By making the electrical trace have a thickness that is less than the skin depth, the current flows through substantially the entire cross-sectional area of the electrical trace for all frequencies up to the chosen frequency component, which reduces the effects associated with the skin effect. | 10-01-2015 |
20150236856 | AUTHENTICATION USING PUBLIC KEYS AND SESSION KEYS - One approach for authenticating data includes storing a plurality of combinations of representations of public keys and session key IDs in a non-volatile memory. A payload and accompanying public key, session key ID, and signature of the payload are input. The signature is a function of the payload and a private key of a key pair that includes the accompanying public key and the private key. Authenticity of the payload is determined based on the accompanying public key and session key ID and the combinations stored in the non-volatile memory, and from the signature and the payload. In response to determining that the payload is authentic, the payload is processed, and in response to determining that the payload is not authentic, processing of the payload is disabled. | 08-20-2015 |
20150222033 | LOW INSERTION LOSS PACKAGE PIN STRUCTURE AND METHOD - An apparatus for placement between a package and an integrated circuit board includes: an insert having: a substrate having a top side and a bottom side; a first set of pads at the top side of the substrate; a second set of pads at the bottom side of the substrate; and a plurality of vias in the substrate, the vias connecting respective pads in the first set to respective pads in the second set; wherein the insert has a thickness that is less than a spacing between the package and the integrated circuit board. | 08-06-2015 |
20150187715 | SEMICONDUCTOR DEVICE HAVING BUCKET-SHAPED UNDER-BUMP METALLIZATON AND METHOD OF FORMING SAME - A semiconductor device includes a first under-bump metallization (UBM) layer disposed over a bond pad, a dielectric layer above an interconnect layer having a via exposing at least a portion of the first UBM layer. A second UBM layer is disposed above the first UBM layer and forms a UBM bucket over the via. The first UBM layer and UBM bucket are configured to support a solder ball and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated. | 07-02-2015 |
20150180642 | DATA RECEIVERS AND METHODS OF IMPLEMENTING DATA RECEIVERS IN AN INTEGRATED CIRCUIT - A data receiver implemented in an integrated circuit is described. The data receiver comprises an input receiving a data signal; a first equalization circuit coupled to receive the data signal, wherein the first equalization circuit is used to receive the data of the data signal; and a second equalization circuit coupled to receive the data signal, wherein the second equalization circuit is used to adjust a clock phase offset. | 06-25-2015 |
20150160862 | MEMORY ARRANGEMENT FOR IMPLEMENTATION OF HIGH-THROUGHPUT KEY-VALUE STORES - A circuit for processing data is described. The circuit comprises an input for receiving a request for implementing a key-value store data transaction; a plurality of memory interfaces associated with different memory types enabling access to a plurality of memory devices associated with a key-value store; and a memory management circuit controlling the routing of data by way of the plurality of memory interfaces based upon a data transfer criterion. | 06-11-2015 |
20150145615 | HIGH QUALITY FACTOR INDUCTIVE AND CAPACITIVE CIRCUIT STRUCTURE - A circuit includes a first finger capacitor having a first bus line coupled to a first plurality of finger elements and a second bus line coupled to a second plurality of finger elements. The first bus line is parallel to the second bus line. The circuit further includes an inductor having a first leg oriented perpendicular to the first bus line and the second bus line. The first leg of the inductor is coupled to a center of the first bus line. | 05-28-2015 |
20150127877 | SERDES RECEIVER OVERSAMPLING RATE - An apparatus relates generally to serializer-deserializers. In such an apparatus, a first serializer-deserializer has a first data path and a data eye path. The first data path is coupled to a first data out interface of the first serializer-deserializer. A second serializer-deserializer has a second data path. The second data path is coupled to a second data out interface of the second serializer-deserializer. The data eye path of the first serializer-deserializer is coupled to the second data path of the second serializer-deserializer. | 05-07-2015 |
20150123265 | SOLDER BUMP ARRANGEMENTS FOR LARGE AREA ANALOG CIRCUITRY - An integrated circuit (IC) can include an analog region of a die of the IC. The analog region includes analog circuitry. The IC further includes a plurality of solder bumps implemented on a surface of the die in an area in vertical alignment with the analog region of the die. | 05-07-2015 |
20150106609 | MULTI-THREADED LOW-LEVEL STARTUP FOR SYSTEM BOOT EFFICIENCY - Methods, computer-readable media and devices for executing a plurality of startup instructions are disclosed. For example, a method includes a first processor of a device accessing a plurality of startup instructions in response to a startup of the device. The first processor then executes a first startup instruction of the plurality of startup instructions to perform a first task and executes a second startup instruction of the plurality of startup instructions. The executing the second startup instruction causes the first processor to send a further instruction to a second processor of the device to perform a second task. At least a portion of the first task and at least a portion of the second task are performed at a same time. | 04-16-2015 |
20150069577 | REMOVAL OF ELECTROSTATIC CHARGES FROM INTERPOSER FOR DIE ATTACHMENT - A wafer includes a first interposer having a first patterned metal layer and a second interposer having a second patterned metal layer. The wafer includes a metal connection in a scribe region of the wafer that electrically couples the first patterned metal layer of the first interposer with the second patterned metal layer of the second interposer forming a global wafer network. The wafer further includes a probe pad located in the scribe region that is electrically coupled to the global wafer network. | 03-12-2015 |
20150061756 | INPUT/OUTPUT CIRCUITS AND METHODS OF IMPLEMENTING AN INPUT/OUTPUT CIRCUIT - An input/output circuit implemented in an integrated circuit is described. The input/output circuit comprises an input/output pad and a voltage control circuit coupled to the input/output pad. The voltage control circuit sets a voltage at the input/output pad at a first voltage when the input/output pad is implemented as an input pad and at a second voltage when the input/output pad is implemented as an output pad. Methods of implementing input/output circuits in an integrated circuit are also described. | 03-05-2015 |
20150054085 | METHOD AND APPARATUS FOR SUPPRESSING METAL-GATE CROSS-DIFFUSION IN SEMICONDUCTOR TECHNOLOGY - An inverter includes: a PMOS comprising: a p-type source region, a p-type drain region, a p-channel region between the p-type source region and the p-type drain region, and a PMOS metal gate region; a NMOS, comprising: an n-type source region, an n-type drain region, an n-channel region between the n-type source region and the n-type drain region, and a NMOS metal gate region; an insulating layer above the p-channel region and the n-channel region, wherein the PMOS metal gate region and the NMOS metal gate region are above the insulating layer; and a gate contact between the NMOS metal gate region and the PMOS metal gate region. | 02-26-2015 |
20140312483 | SEMICONDUCTOR PACKAGE HAVING IC DICE AND VOLTAGE TUNERS - A semiconductor package includes an interposer and a plurality of integrated circuit (IC) dice disposed on and intercoupled via the interposer. A first IC die has a clock speed rating that is greater than a clock speed rating of another of the IC dice. A plurality of programmable voltage tuners are coupled to the plurality of IC dice, respectively. A first voltage tuner is coupled to the first IC die, and the first voltage tuner is programmed to reduce a voltage level of voltage input to the first voltage tuner and output the reduced voltage to the first IC die. | 10-23-2014 |
20140281844 | MODULAR AND SCALABLE CYCLIC REDUNDANCY CHECK COMPUTATION CIRCUIT - Devices and methods for performing a cyclic redundancy check are disclosed. For example, a device has a splitter for splitting a data word into a plurality of paths. The device also has a plurality of cyclic redundancy check units. Each of the units is for processing a respective one of the paths. In addition, each of the units includes a first output port for outputting a cyclic redundancy check value for a packet ending within the unit and a second output port for outputting a cyclic redundancy check value for a packet starting or ongoing within the unit. | 09-18-2014 |
20140281716 | ANALOG BLOCK AND TEST BLOCKS FOR TESTING THEREOF - An apparatus relating generally to a system-on-chip is disclosed. In this apparatus, the system-on-chip has at least one analog block, an input/output interface, a data test block, and a processing unit. The processing unit is coupled to the input/output interface to control access to the at least one analog block. The data test block is coupled to the at least one analog block through the input/output interface. The processing unit is coupled to the data test block and configured to execute test code having at least one test pattern. The data test block under control of the test code executed by the processing unit is configured to test the at least one analog block with the test pattern. | 09-18-2014 |
20140281455 | MULTI-BOOT OR FALLBACK BOOT OF A SYSTEM-ON-CHIP USING A FILE-BASED BOOT DEVICE - A method includes initiating a boot of a system-on-chip coupled to a boot device. The boot is initiated from boot code stored in nonvolatile memory responsive to a power-on-reset. Under control of the boot code: a first register value is loaded into a register; a name string from the boot code is accessed; the first register value is obtained from the register; and the first register value and name string are converted to a first string value, which is provided as a first filename. The boot device is searched for a boot image file with the first filename. If the first filename is not found in the boot device, the first register value is incremented to provide a second register value. The obtaining, converting, and searching are repeated using a second filename generated using the second register value, and a valid filename for the boot image file is iteratively generated. | 09-18-2014 |
20140269769 | TIMESTAMP CORRECTION IN A MULTI-LANE COMMUNICATION LINK WITH SKEW - A method, non-transitory computer readable medium and apparatus for correcting a timestamp in a multi-lane communication link with a skew are disclosed. For example, the method receives a data packet, a time stamp for the data packet and a fill level for a lane of the multi-lane communication link carrying the data packet, calculates a corrected timestamp for the data packet and replaces the time stamp for the data packet with the corrected timestamp. | 09-18-2014 |
20140266824 | CALIBRATION OF A SWITCHING INSTANT OF A SWITCH - An apparatus for calibration of a signal converter is disclosed. This apparatus includes a first digital-to-analog converter (“DAC”) and a calibration system coupled to an output port of the first DAC. The calibration system includes a second DAC. The calibration system is configured to provide an adjustment signal responsive to a spurious spectral performance parameter in an output of the first DAC. The spurious spectral performance parameter is sensitive to a timing error associated with the first DAC. The calibration system is coupled to provide the adjustment signal to the first DAC to correct the timing error of the first DAC. | 09-18-2014 |
20140266434 | CIRCUITS FOR AND METHODS OF IMPLEMENTING A GAIN STAGE IN AN INTEGRATED CIRCUIT - A circuit for implementing a gain stage in an integrated circuit is described. The circuit comprises a first inductor formed in a first plurality of metal layers; a second inductor formed in a second plurality of metal layers, the second inductor coupled to a center tap of the first inductor; and wherein the second inductor has a diameter that is less than a diameter of the first inductor. A method of implementing a gain stage in an integrated circuit is also described. | 09-18-2014 |
20140262440 | MULTI-LAYER CORE ORGANIC PACKAGE SUBSTRATE - A multi-layer core organic package substrate includes: a multi-layer core comprising at least two organic core layers, wherein two of the at least two organic core layers are separated by a core metal layer; a first plurality of build-up layers formed on top of the multi-core layer; and a second plurality of build-up layers formed below the multi-core layer. | 09-18-2014 |
20140254232 | INTEGRATED CIRCUIT DEVICES HAVING MEMORY AND METHODS OF IMPLEMENTING MEMORY IN AN INTEGRATED CIRCUIT DEVICE - An integrated circuit device having memory is disclosed. The integrated circuit device comprises programmable resources; programmable interconnect elements coupled to the programmable resources, the programmable interconnect elements enabling a communication of signals with the programmable resources; a plurality of memory blocks; and dedicated interconnect elements coupled to the plurality of memory blocks, the dedicated interconnect elements enabling access to the plurality of memory blocks. A method of implementing memory in an integrated circuit device is also disclosed. | 09-11-2014 |
20140253171 | PACKAGE INTEGRITY MONITOR WITH SACRIFICIAL BUMPS - An apparatus with package integrity monitoring capability, includes: a package having a die connected to an interposer through a plurality of bumps, wherein at least some of the bumps comprise dummy bumps; a package integrity monitor having a transmitter to transmit a test signal and a receiver to receive the test signal; and a first scan chain comprising a plurality of alternating interconnects in the die and in the interposer connecting some of the dummy bumps in series, wherein the first scan chain has a first end coupled to the transmitter of the package integrity monitor and a second end coupled to the receiver of the package integrity monitor. | 09-11-2014 |
20140252599 | SUBSTRATE-LESS INTERPOSER TECHNOLOGY FOR A STACKED SILICON INTERCONNECT TECHNOLOGY (SSIT) PRODUCT - A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, includes: a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer; and a dielectric layer formed on the bottom surface of the bottom most layer, wherein the dielectric layer includes one or more openings for providing contact to the plurality of metal segments in the bottom most layer. | 09-11-2014 |
20140205934 | SINGLE RETICLE APPROACH FOR MULTIPLE PATTERNING TECHNOLOGY - A reticle for multiple patterning a layer of an integrated circuit die includes a first portion with a first layout pattern for multiple patterning the layer of the integrated circuit die, and a second portion with a second layout pattern for multiple patterning the layer of the integrated circuit die. The first layout pattern is different from the second layout pattern. | 07-24-2014 |
20140198416 | CIRCUIT FOR AND METHOD OF ENABLING THE DISCHARGE OF ELECTRIC CHARGE IN AN INTEGRATED CIRCUIT - A circuit for enabling the discharge of electric charge in an integrated circuit is described. The circuit comprises an input/output pad coupled to a first node; a first diode coupled between the first node and a ground node; a transistor coupled in parallel with the first diode between the first node and ground node; and a resistor coupled between a body portion of the transistor and the ground node. A method of enabling the discharge of electric charge is also described. | 07-17-2014 |
20140173350 | ON-THE-FLY TECHNICAL SUPPORT - A method performed by an information handling system for on-the-fly technical support is described. In an exemplary method, an error message is read to obtain an error code therefrom. A project directory is searched to obtain a report; where the report indicates a failed module of a plurality of executable modules, and where the report is associated with the error message. A source of an error is identified from the error message. A failed stage of the failed module is identified from the report. A case inquiry for the error message is prepared for searching a document for resolution of the error, where the case inquiry identifies the failed stage. A network is accessed, and the case inquiry is sent over the network. | 06-19-2014 |
20140172347 | GENERATION OF A RANDOM SUB-SPACE OF THE SPACE OF ASSIGNMENTS FOR A SET OF GENERATIVE ATTRIBUTES FOR VERIFICATION COVERAGE CLOSURE - System, method and computer readable medium are described. The method may include obtaining user defined distribution traits characterizing a random sub-space of a space of assignments for a set of generative variables. The method may further include applying the user defined distribution traits on the space of assignments for a set of generative variables to generate the random sub-space of the space of assignments for a set of generative variables. The method may also include testing a device under test using the generated random sub-space of the space of assignments for a set of generative variables. | 06-19-2014 |
20140145293 | INTEGRATED CIRCUIT HAVING IMPROVED RADIATION IMMUNITY - An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors. | 05-29-2014 |
20140133527 | DIGITAL PRE-DISTORTION IN A COMMUNICATION NETWORK - A method of performing digital pre-distortion in a communication network is described. The method comprises implementing a transceiver in the communication network, the transceiver enabling the transfer of communication signals in the communication network by way of a wireless communication channel; sampling signals, at the transceiver, associated with a transmit signal which are necessary to perform digital pre-distortion; providing the sampled signals to a remote computer; and generating, at the remote computer, parameters to be applied to a digital pre-distortion circuit of the transceiver. A communication network configured to enable digital pre-distortion is also described. | 05-15-2014 |
20140133246 | CONFIGURABLE EMBEDDED MEMORY SYSTEM - An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data. | 05-15-2014 |
20140132369 | SYSTEM AND METHOD FOR REDUCING EFFECTS OF SWITCHED CAPACITOR KICKBACK NOISE - A circuit includes a first input terminal, a first transmission line, a first sampling switch coupled to the first input terminal through the first transmission line, a first sampling capacitor coupled to the sampling switch, and a first open-circuit quarter wavelength stub coupled to the first transmission line, the first open-circuit quarter wavelength stub configured to reduce kickback noise on the first transmission line. A method for reducing kickback noise in a circuit includes determining a frequency associated with a kickback noise on a first transmission line of the circuit, the circuit having an input terminal coupled to the first transmission line, configuring a length of an open-circuit quarter wavelength stub to correspond to the determined frequency, and coupling the open-circuit quarter wavelength stub to the first transmission line to filter the frequency associated with the kickback noise. | 05-15-2014 |
20140132305 | CLOCK NETWORK ARCHITECTURE - An apparatus includes an integrated circuit with a clock network in an array of circuit blocks. The clock network includes routing tracks, distribution spines, and clock leaves. The routing tracks and the distribution spines are bidirectional. | 05-15-2014 |
20140117494 | INDUCTOR STRUCTURE WITH PRE-DEFINED CURRENT RETURN - An inductor structure implemented within a semiconductor integrated circuit includes a coil of conductive material including at least one turn and a current return encompassing the coil. The current return is formed of a plurality of interconnected metal layers of the semiconductor integrated circuit. | 05-01-2014 |
20140091843 | PLESIOCHRONOUS CLOCK GENERATION FOR PARALLEL WIRELINE TRANSCEIVERS - A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the at least one decoder, the at least one digital frequency mismatch number to obtain at least one digital frequency divider number that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number into at least one fractional-N phase lock loop; and utilizing, by the at least one fractional-N phase lock loop, the at least one digital frequency divider number and an analog reference signal produced by a reference oscillator to produce a resultant signal at the transmit frequency; wherein the at least one decoder and the at least one fractional-N phase lock loop are contained on a single integrated circuit. | 04-03-2014 |
20140091819 | METHOD OF TESTING A SEMICONDUCTOR STRUCTURE - An integrated circuit (IC) comprises routing circuitry including a plurality of signal line segments in routing layers of the IC, and a plurality of micro-bump contacts coupled to the routing circuitry. The IC includes a plurality of test circuits coupled to respective subsets of the plurality of signal line segments. Each test circuit is configured to connect micro-bump contacts in the respective subset to form first and second sets of daisy chains. Each test circuit is configured to test the first and second sets of daisy chains for open circuits and test for short circuits between the first and second sets of daisy chains. Each test circuit is configured to determine the locations of detected open circuits and determine the locations of detected short circuits. | 04-03-2014 |
20140089718 | CLOCK DOMAIN BOUNDARY CROSSING USING AN ASYNCHRONOUS BUFFER - An apparatus includes a plurality of channels, where each of the channels includes an asynchronous buffer, a latency determination block, a tap selection circuit, and a variable delay. A latency locator is configured to identify a longest latency from among the channels and is coupled to provide the longest latency to the tap selection circuit of each of the channels. For each of the channels: the latency determination block is coupled to the asynchronous buffer to determine a latency value for the asynchronous buffer; the tap selection circuit is coupled to receive the latency value and the longest latency; the tap selection circuit is coupled to the variable delay; and the tap selection circuit is configured to select a tap of taps of the variable delay responsive to the latency value and the longest latency. | 03-27-2014 |
20140085003 | REDUCING THE EFFECT OF PARASITIC MISMATCH AT AMPLIFIER INPUTS - A circuit includes an amplifier including a differential input stage including a first input terminal and a second input terminal. The circuit further includes a differential input line coupled to the first input terminal and the second input terminal, and shielding at least partially encompassing the differential input line. The shielding is connected to a node of the differential input stage of the amplifier. | 03-27-2014 |
20140084477 | NOISE ATTENUATION WALL - An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer has first vias. First interconnects and second interconnects respectively are coupled on opposite surfaces of the interposer. A first portion of the first interconnects and a second portion of the first interconnects are spaced apart from one another defining an isolation region between them. A substrate has second vias. Third interconnects and the second interconnects are respectively coupled on opposite surfaces of the package substrate. A first portion of the first vias and a first portion of the second vias are both in the isolation region and are coupled to one another with a first portion of the second interconnects. | 03-27-2014 |
20140050286 | RECURSION UNIT SCHEDULING - An embodiment of a decoder is disclosed. For this embodiment of the decoder, a first estimation unit and a second estimation unit are for iterative decoding. A scheduler is to receive a mode select signal to provide either an indication of first scheduling information or second scheduling information to the first estimation unit and the second estimation unit responsive to the mode select signal. | 02-20-2014 |
20140049932 | FLEXIBLE SIZED DIE FOR USE IN MULTI-DIE INTEGRATED CIRCUIT - An integrated circuit (IC) structure can include a first die and a second die. The second die can include a first base unit and a second base unit. Each of the first base unit and the second base unit is self-contained and no signals pass between the first base unit and the second base unit within the second die. The IC structure can include an interposer. The interposer includes a first plurality of inter-die wires coupling the first die to the first base unit, a second plurality of inter-die wires coupling the first die to the second base unit, and a third plurality of inter-die wires coupling the first base unit to the second base unit. | 02-20-2014 |
20140048887 | INTEGRATED CIRCUIT HAVING IMPROVED RADIATION IMMUNITY - An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; an n-well formed on the substrate; a p-well formed on the substrate; and a p-tap formed in the p-well adjacent to the n-well, wherein the p-tap extends between circuit elements formed in the n-well and circuit elements formed in the p-well, and is coupled to a ground potential. A method of forming an integrated circuit having improved radiation immunity is also described. | 02-20-2014 |
20140029143 | RECEIVER HAVING A WIDE COMMON MODE INPUT RANGE - In one embodiment, a differential amplifier is provided. Gates of a first differential pair of transistors, of a first conductivity type, and a second pair or transistors, of a second conductivity type are coupled to first and second input terminals of the differential amplifier. A first pair of adjustable current sources are configured to adjust respective tail currents of the first differential pair of transistors in response to a first bias current control signal. A second pair of adjustable current sources are configured to adjust respective tail currents of the second differential pair of transistors in response to the first bias current control signal. A third pair of adjustable current sources are configured to adjust respective currents through the second differential pair of transistors in response to a second bias current control signal. | 01-30-2014 |
20140017852 | METHODS FOR FLIP CHIP STACKING - A method for flip chip stacking includes forming a cavity wafer comprising a plurality of cavities and a pair of corner guides, placing a through-silicon-via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated between the pair of corner guides, placing an integrated circuit (IC) die on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit, removing the stacked interposer unit from the cavity wafer, and bonding the solder bumps of the stacked interposer unit to an organic substrate such that the stacked interposer unit and the organic substrate form a flip chip. | 01-16-2014 |
20130333921 | OVERSIZED INTERPOSER - An embodiment of an interposer is disclosed. For this embodiment of the interposer, a first circuit portion is created responsive to a first printing region. A second circuit portion is created responsive to a second printing region. The interposer has at least one of: (a) a length dimension greater than a maximum reticle length dimension, and (b) a width dimension greater than a maximum reticle width dimension. | 12-19-2013 |
20130321047 | DISTORTION TOLERANT CLOCK AND DATA RECOVERY - A system can include a phase detector configured to generate a phase error signal indicating a phase error of an input signal compared to an output signal and a first filter coupled to the phase detector and configured to generate a first control signal derived from the phase error signal. The system can include a pattern error detector configured to generate a pattern error signal specifying a pattern error of the input signal compared to the output signal and a second filter coupled to the pattern error detector and configured to generate a second control signal derived from the pattern error signal. The system further can include a controlled oscillator coupled to the first filter and the second filter, wherein the controlled oscillator is configured to generate the output signal responsive to the first control signal, the second control signal, and a center frequency signal. | 12-05-2013 |
20130277099 | CONDUCTOR STRUCTURE WITH INTEGRATED VIA ELEMENT - An electrical circuit structure can include a first trace formed using a first conductive layer and a second trace formed using a second conductive layer. The first trace can be vertically aligned with the second trace. The electrical circuit structure can include a via segment formed of conductive material in a third conductive layer between the first conductive layer and the second conductive layer. The via segment can contact the first trace and the second trace forming a first conductor structure configured to convey an electrical signal in a direction parallel to the first conductive layer. | 10-24-2013 |
20130254639 | PARALLEL ENCODING FOR NON-BINARY LINEAR BLOCK CODE - An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed. | 09-26-2013 |
20130215541 | HIGH VOLTAGE RC-CLAMP FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION - In accordance with some embodiments, an electrostatic discharge (ESD) protection circuit for high-voltage power rails includes an RC-triggered clamp having an RC-circuit having a resistor coupled between a first node and a second node, and a capacitor coupled between the second node and a third node. The RC-triggered clamp also has a transistor with a first source/drain, a gate, and a second source/drain, wherein the first source/drain is coupled to the first node, and the second source/drain is coupled to the third node. The RC-triggered clamp also has an inverter, wherein an input of the inverter is coupled to the second node, and an output of the inverter is coupled to the gate of the transistor. The ESD protection circuit also includes one or more forward-biased diodes coupled in series between a supply node and the first node. | 08-22-2013 |
20130214432 | STACKED DIE ASSEMBLY - Embodiments of stacked die assemblies for an IC are disclosed. One embodiment includes a first interposer; a second interposer; a first integrated circuit die, a second integrated circuit die, and a plurality of components. The first integrated circuit die is interconnected to the first interposer and the second interposer, and the second integrated circuit die is interconnected to the second interposer. The plurality of components interconnect the first integrated circuit die to the first interposer and the second interposer. The plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area of the first interposer and the second interposer, and signals are routed between the first interposer and the second interposer via the first integrated circuit die and the plurality of components, avoiding the interconnect restricted area of the first interposer and the second interposer. | 08-22-2013 |
20130200511 | REDUCING STRESS IN MULTI-DIE INTEGRATED CIRCUIT STRUCTURES - An integrated circuit structure can include a first interposer and a second interposer. The first interposer and the second interposer can be coplanar. The integrated circuit structure further can include at least a first die that is coupled to the first interposer and the second interposer. | 08-08-2013 |
20130181783 | RESONATOR CIRCUIT AND METHOD OF GENERATING A RESONATING OUTPUT SIGNAL - A resonator circuit enabling temperature compensation includes an inductor coupled between a first node and a second node of the resonator circuit; a capacitor circuit coupled between the first node and the second node; and a temperature compensation circuit coupled between the first node and the second node. The temperature compensation circuit comprises a varactor coupled to receive a temperature control signal that sets the capacitance of the varactor. A method of generating a resonating output is also disclosed. | 07-18-2013 |
20130181360 | INTEGRATED CIRCUIT CONNECTIVITY USING FLEXIBLE CIRCUITRY - An integrated circuit (IC) structure can include an internal element and a flexible circuitry directly coupled to the internal element. The flexible circuitry can be configured to exchange signals between the internal element and a node external to the IC structure. | 07-18-2013 |
20130176647 | DRIVER CIRCUIT AND METHOD OF GENERATING AN OUTPUT SIGNAL - A driver circuit of an integrated circuit is described. The driver circuit comprises a signal node coupled to receive an output signal of the integrated circuit; an inductor circuit having a resistor coupled in series with an inductor between a first terminal and a second terminal, wherein the first terminal is coupled to the signal node; an electro-static discharge protection circuit coupled to the second terminal of the inductor circuit; and an output node coupled to the second terminal of the inductor circuit. A method of generating an output signal is also disclosed. | 07-11-2013 |
20130175709 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF ASSEMBLING AN INTEGRATED CIRCUIT PACKAGE - A method of assembling an integrated circuit package is disclosed. The method comprises placing a die on a substrate of the integrated circuit package; coupling a plurality of wire bonds from a plurality of bond pads on the die to corresponding bond pads on the substrate; applying a non-conductive material to the plurality of wire bonds; and encapsulating the die and the plurality of wire bonds. An integrated circuit package is also disclosed. | 07-11-2013 |
20130156118 | SYSTEMS AND METHODS FOR CHANGING DECODING PARAMETERS IN A COMMUNICATION SYSTEM - A communication system includes an iterative multi-stage decoder that may be dynamically configured to achieve a particular bit-error-rate. In one embodiment, a circuit comprises a first decoder block and a second decoder block to decode data received over a communication channel. A control circuit may change a number of iterations performed by the decoder blocks to decode received data based on a specified bit error rate and a detected signal-to-noise ratio of said received data. The number of computational units used in the decoders may be changed dynamically to achieve desired system performance. In one embodiment, resources are allocated based on a system initiating the connection. Programmable circuits are used in some embodiments to reconfigure the multi-stage decoder. | 06-20-2013 |
20130151911 | REDUCTION IN DECODER LOOP ITERATIONS - An embodiment of a method for decoding is disclosed. For this embodiment of the method, a decoder is limited to a set number of iterations for a decoding sequence. The set number of iterations is selected to be less than an optimal number of iterations for an optimal bit error rate (“BER”) resulting in a BER penalty. Inner loop decoding operations are performed within the decoder for the set number of iterations. Reliability information is output from the decoder to a data slicer. A symbol stream is output from the data slicer responsive to the reliability information. | 06-13-2013 |
20130148450 | CONTENTION-FREE MEMORY ARRANGEMENT - A memory arrangement includes a plurality of memory blocks, a first group of access ports, and a second group of access ports. Routing circuitry couples each pair of the first and second groups of access ports to a respective one of the memory blocks. Each pair includes a first access port from the first group and a second access port from the second group. The first access port has write access to a first portion of the respective memory blocks but not to a second portion of the memory block, and has read access to the second portion but not to the first portion. The second access port has write access to the second portion but not to the first portion, and has read access to the first portion but not to the second portion. | 06-13-2013 |
20130144926 | MINIMUM MEAN SQUARE ERROR PROCESSING - A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication. | 06-06-2013 |
20130138879 | CIRCUIT FOR AND METHOD OF ENABLING THE TRANSFER OF DATA BY AN INTEGRATED CIRCUIT - A circuit for enabling the transfer of data by an integrated circuit device is described. The circuit comprises a non-volatile memory array coupled to receive a clock signal and having a plurality of memory elements storing data; and a control circuit coupled to the non-volatile memory array, the control circuit enabling uni-directional transfer of data on a plurality of signal lines between the non-volatile memory array and the control circuit in a first mode and bi-directional transfer of data in a second mode; wherein the control circuit controls the transfer of data on the plurality of signal lines between the non-volatile memory array and the control circuit in the first mode on both the rising and falling edges of the clock signal. A method of enabling the transfer of data by an integrated circuit device is also described. | 05-30-2013 |
20130138712 | MINIMUM MEAN SQUARE ERROR PROCESSING - A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication. | 05-30-2013 |
20130117504 | EMBEDDED MEMORY AND DEDICATED PROCESSOR STRUCTURE WITHIN AN INTEGRATED CIRCUIT - An integrated circuit can include a programmable circuitry operable according to a first clock frequency and a block random access memory. The block random access memory can include a random access memory (RAM) element having at least one data port and a memory processor coupled to the data port of the RAM element and to the programmable circuitry. The memory processor can be operable according to a second clock frequency that is higher than the first clock frequency. Further, the memory processor can be hardwired and dedicated to perform operations in the RAM element of the block random access memory. | 05-09-2013 |
20130101066 | SYSTEMS AND METHODS FOR DIGITAL PROCESSING BASED ON ACTIVE SIGNAL CHANNELS OF A COMMUNICATION SYSTEM - A communication system includes digital signals that carry data and correspond to channels of a composite signal to be transmitted across a communication channel. Active channels are detected and used to configure digital processing. In one embodiment, active channels are detected, where a particular active channel corresponds to the presence of a particular one of the digital signals. Active channel detection may be used to configure pre-distortion of a composite signal to be transmitted to compensate for distortion in a digital-to-analog converter. Likewise, active channel detection may be used to optimize the configuration of an up-converter. In one embodiment, a programmable device is configured based on detected active channels into a plurality of different configurations. | 04-25-2013 |
20130094507 | PARALLEL PROCESSING OF NETWORK PACKETS - A packet processing circuit includes a plurality of header extraction circuits, and a scheduling circuit coupled to the plurality of header extraction circuits. The scheduling circuit is configured to receive one or more requests to extract header data of a respective packet from a data bus having a plurality of data lanes. In response to each request, the scheduling circuit determines a first subset of the plurality of data lanes that contain the respective header specified by the request, and assigns a respective one of the plurality of header extraction circuits to extract respective header data from the first subset of the plurality of data lanes. | 04-18-2013 |
20130093074 | MULTI-DIE INTEGRATED CIRCUIT STRUCTURE WITH HEAT SINK - An integrated circuit structure can include a first die including a first surface and a second surface and a second die including a first surface and a second surface. The first surface of the first die can be coupled to the second surface of the second die. The integrated circuit structure also can include a heat sink coupled to the first surface of the first die and the first surface of the second die. | 04-18-2013 |
20130063861 | INTERDIGITATED CAPACITOR HAVING DIGITS OF VARYING WIDTH - An interdigitated capacitor having digits of varying width is disclosed. One embodiment of a capacitor includes a first plurality of conductive digits and a second plurality of conductive digits positioned in an interlocking manner with the first plurality of conductive digits, such that an interdigitated structure is formed. The first plurality of conductive digits and the second plurality of conductive digits collectively form a set of digits, where the width of a first digit in the set of digits is non-uniform with respect to a second digit in the set of digits. | 03-14-2013 |
20130027228 | DECODER CIRCUIT FOR DOWN-SAMPLING A DIFFERENTIAL MANCHESTER ENCODING - Decoder circuits and methods down-sample the samples that oversample an input signal having a differential Manchester encoding. A first input port receives first, second, and third samples. A second input port receives a state indicating whether a clock transition or a data transition precedes the first, second, and third samples. A third input port receives first, second, and third down-sampled bits. A detector circuit is configured to generate a detection signal indicating a presence of a short pulse within the samples when the state indicates the clock transition and the second and third down-sampled bits are equal and differ from the first down-sampled bit and the third sample. A generator circuit is configured to generate a fourth down-sampled bit that equals the third sample when the detection signal indicates the presence of the short pulse, and that equals the second sample when the detection signal does not indicate the presence. | 01-31-2013 |
20130022136 | INTEGRATED CIRCUIT ENABLING THE COMMUNICATION OF DATA AND A METHOD OF COMMUNICATING DATA IN AN INTEGRATED CIRCUIT - An integrated circuit enabling the communication of data is described. The integrated circuit comprises an input/output port; a plurality of data converter circuits; and programmable interconnect circuits coupled between the input/output port and the plurality of data converter circuits, the programmable interconnect circuits enabling a connection of the plurality of data converter circuits to the input/output port of the integrated circuit. A method of enabling the communication of data in an integrated circuit is also described. | 01-24-2013 |
20130020675 | INDUCTIVE STRUCTURE FORMED USING THROUGH SILICON VIAS - An inductor for an integrated circuit can include a first turn comprising a first through silicon via (TSV) coupled to a second TSV. The inductor can include a third TSV coupled to the second TSV. | 01-24-2013 |
20130009694 | METHOD AND APPARATUS FOR SELF-ANNEALING MULTI-DIE INTERCONNECT REDUNDANCY CONTROL - An apparatus for interconnecting a first die and a second die of a multi-die device includes a master circuit block that interfaces with the first die of the multi-die device, a slave circuit block that interfaces with the second die of the multi-die device, a first memory in the slave circuit block, a second memory in the master circuit block, and a plurality of μbumps between the first die and the second die, wherein the master circuit block and the slave circuit block are configured to identify one of the μbumps as a faulty μbump, and store a first value that corresponds with the identified faulty μbump in the first memory. | 01-10-2013 |
20130002410 | RECEIVER CIRCUIT - A receiver circuit includes an analog front-end circuit, a first adaptation circuit, and a second adaptation circuit. A method operates the receiver circuit. The analog front-end circuit is configured to resolve an output signal from an input signal as a function of adjustable parameters. The first adaptation circuit is coupled to the analog front-end circuit and is configured to determine values of the adjustable parameters responsive to the output signal. The second adaptation circuit is coupled to the analog front-end circuit and to the first adaptation circuit. The second adaptation circuit is configured to adjust the values of the adjustable parameters responsive to one or more operating conditions of the receiver circuit. These operating conditions include a temperature and/or a power supply voltage of the receiver circuit. | 01-03-2013 |
20120331435 | INTEGRATED CIRCUIT DESIGN USING THROUGH SILICON VIAS - A method of integrated circuit design using through silicon vias (TSVs) can include determining that a stress field to which a first active circuit element of a circuit block is exposed and a stress field to which a second active circuit element of the circuit block is exposed are mismatched. Mismatch between the stress field of the first active circuit element and the stress field of the second active circuit element can be reduced by modifying a layout of the die for a TSV. | 12-27-2012 |
20120319248 | STRESS-AWARE DESIGN FOR INTEGRATED CIRCUITS - A method of circuit design involving an integrated circuit (IC) having an interposer can include identifying an active resource implemented within the IC within a region of the interposer exposed to an amount of stress that exceeds a normalized amount of stress on the interposer and selectively assigning an element of the circuit design to be implemented within the IC to the active resource according to a stress-aware analysis of the circuit design as implemented within the IC. | 12-20-2012 |
20120248569 | INTERPOSER HAVING AN INDUCTOR - An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures. | 10-04-2012 |
20120242446 | INTEGRATED CIRCUIT INDUCTOR HAVING A PATTERNED GROUND SHIELD - An inductor structure can be implemented within a semiconductor integrated circuit (IC). The inductor structure can include a coil of conductive material having a first terminal and a second terminal each located at an opposing end of the coil. The inductor structure can include a patterned ground shield including a plurality of fingers implemented within an IC process layer located between the coil of conductive material and a substrate of the IC. The inductor structure also can include an isolation wall formed to encompass the coil and the patterned ground shield. The isolation wall can be coupled to one end of each finger. | 09-27-2012 |
20120241904 | SYMMETRICAL CENTER TAP INDUCTOR STRUCTURE - An inductor structure implemented within a semiconductor integrated circuit (IC) can include a coil of conductive material that includes a center terminal located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline bisecting the center terminal. The coil can include a first differential terminal and a second differential terminal each located at an end of the coil and opposite the center terminal. The inductor structure can include an isolation ring surrounding the coil. In some cases, the inductor structure can include a return line of conductive material positioned on the center line. | 09-27-2012 |
20120229203 | CALIBRATING DEVICE PERFORMANCE WITHIN AN INTEGRATED CIRCUIT - A multi-fingered device can be calibrated for performance. The multi-fingered device can include a first finger configured to remain active and a second finger that is initially deactivated concurrent with the first finger being active. A measure of degradation for the multi-fingered device within an IC can be determined. The measure of degradation can be compared with a degradation threshold. Responsive to determining that the measure of degradation meets the degradation threshold, a finger of the multi-fingered device can be activated. | 09-13-2012 |
20120221833 | INTEGRATED CIRCUIT WITH PROGRAMMABLE CIRCUITRY AND AN EMBEDDED PROCESSOR SYSTEM - An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein. | 08-30-2012 |
20120212315 | MULTIPLE-LOOP SYMMETRICAL INDUCTOR - A symmetrical inductor includes an integrated circuit having a plurality of conductive layers. A first loop is disposed in an upper layer of the conductive layers, and at least two strapped loops are disposed in at least two layers of the conductive layers, respectively. The strapped loops are coupled in series to the first loop, and the at least two layers are below the upper layer. A second loop is disposed in the upper layer and is coupled in series to the at least two strapped loops. A first terminal electrode is coupled to the first loop, and a second terminal electrode is coupled to the second loop. A center-tap electrode is coupled to the at least two strapped loops. | 08-23-2012 |
20120199959 | EXTENDED UNDER-BUMP METAL LAYER FOR BLOCKING ALPHA PARTICLES IN A SEMICONDUCTOR DEVICE - An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. A UBM layer is disposed between the solder bump and the semiconductor portion and includes the UBM pad and a UBM field. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion. The UBM field is separated from each UBM pad by a gap extending from the UBM pad to the UBM field so as to electrically isolate the UBM field from the UBM pad. | 08-09-2012 |
20120188671 | T-COIL NETWORK DESIGN FOR IMPROVED BANDWIDTH AND ELECTROSTATIC DISCHARGE IMMUNITY - An embodiment of a circuit is described that includes a first inductor comprising a first end and a second end, where the first end of the first inductor forms an input node of the circuit. The embodiment of the circuit further includes a second inductor comprising a first end and a second end, where the second end of the first inductor is coupled to the first end of the second inductor forming an output node of the circuit; a resistor coupled to the second end of the second inductor; and an electrostatic discharge structure coupled to the output node and configured to provide an amount of electrostatic discharge protection, where the amount of electrostatic discharge protection is based on a parasitic bridge capacitance and a load capacitance metric. | 07-26-2012 |
20120185719 | POWER MANAGEMENT WITHIN AN INTEGRATED CIRCUIT - An integrated circuit can include a processor system configured to execute program code, wherein the processor system is hard-wired. The IC also can include programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system and can be configured to implement a power off procedure under the control of the processor system. | 07-19-2012 |
20120185674 | EXTENDING A PROCESSOR SYSTEM WITHIN AN INTEGRATED CIRCUIT - A method of extending a processor system within an integrated circuit (IC) can include executing program code within the processor system implemented within the IC, wherein the IC includes a programmable fabric. The processor system further can be coupled to the programmable fabric. A process can be performed using a process-specific circuit implemented within the programmable fabric in lieu of using the processor system. A result of the process from the process-specific circuit can be made available to the processor system. | 07-19-2012 |
20120139103 | SEMICONDUCTOR DEVICE WITH STACKED POWER CONVERTER - A semiconductor device with a stacked power converter is described. In some examples, a semiconductor device includes: a first integrated circuit (IC) die having bond pads and solder bumps, the bond pads configured for wire-bonding; and a second IC die mounted on the first IC die, the second IC die having an active side and a backside opposite the active side, the second IC die including bond pads on the active side configured for wire-bonding, and solder bumps disposed on a backside opposite the active side; where the solder bumps of the first IC die are electrically and mechanically coupled to the solder bumps of the second IC die to form bump bonds. | 06-07-2012 |
20120139102 | DISPOSING UNDERFILL IN AN INTEGRATED CIRCUIT STRUCTURE - In one embodiment, a method of forming a multi-die semiconductor device is provided. A plurality of dice is mounted on a semiconductor substrate, and neighboring ones of the dice are separated by a distance at which a first one of the neighboring dice will contact a meniscus of a flange of the neighboring die during underfill to form a capillary bridge between the neighboring dice. Solder bumps are reflowed to electrically connect contact terminals of the plurality of dice to contact terminals on a top surface of the substrate. Underfill is deposited along one or more edges of one or more of the plurality of dice. As a result of the capillary bridge formed between neighboring dice, flow of underfill is induced between the bottom surfaces of the neighboring dice and the top surface of the substrate. The dispensed underfill is cured. | 06-07-2012 |
20120139083 | POWER DISTRIBUTION NETWORK - In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto. | 06-07-2012 |
20120131417 | CLASSIFYING A CRITICALITY OF A SOFT ERROR AND MITIGATING THE SOFT ERROR BASED ON THE CRITICALITY - Methods and systems mitigate a soft error in an integrated circuit. A map is stored in a memory, and the map specifies a criticality class for each storage bit in the integrated circuit. A mitigative technique is associated with each criticality class. The soft error is detected in a corrupted one of the storage bits. The mitigative technique is performed that is associated with the criticality class specified in the map for the corrupted storage bit. | 05-24-2012 |
20120124257 | MULTICHIP MODULE FOR COMMUNICATIONS - An embodiment of a multichip module is disclosed. For this embodiment of the multichip module, a transceiver die has transceivers. A crossbar switch die has at least one crossbar switch. A protocol logic blocks die has protocol logic blocks. The transceiver die, the crossbar switch die, and the protocol logic blocks die are all coupled to an interposer. The interposer interconnects the transceivers and the protocol logic blocks to one another and interconnects the protocol logic blocks and the at least one crossbar switch to one another. | 05-17-2012 |
20120119374 | THROUGH SILICON VIA WITH IMPROVED RELIABILITY - A semiconductor device includes a substrate having a top surface and a bottom surface, and a through-silicon via (TSV) extending from the top surface of the substrate to the bottom surface of the substrate, the TSV having a height and a side profile extending along a longitudinal axis, wherein the side profile has an upper segment forming a first angle relative to the longitudinal axis, and a lower segment forming a second angle relative to the longitudinal axis, the second angle being different from the first angle, and wherein the lower segment has a height that is less than 20% of the height of the TSV. | 05-17-2012 |
20120098130 | LEAD-FREE STRUCTURES IN A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor die and lead-free solder bumps disposed on a surface of the semiconductor die. A substrate includes metal layers and dielectric layers. One of the metal layers includes contact pads corresponding to lead-free solder bumps, and one of the dielectric layers is an exterior dielectric layer having respective openings for the contact pad. Respective copper posts are disposed on the contact pads. The respective copper post for each contact pad extends from the contact pad through the respective opening for the contact pad. The semiconductor die is mounted on the substrate with connections between the lead-free solder bumps and the copper posts. | 04-26-2012 |
20120092119 | MULTIPLE-LOOP SYMMETRICAL INDUCTOR - A symmetrical inductor includes pairs of half-loops, first and second terminal electrodes, and a center-tap electrode. The half-loop pairs are in respective conductive layers of an integrated circuit. Each half-loop pair includes a first and second half-loop in the respective conductive layer. The first and second terminal electrodes are in a first conductive layer, and the center-tap electrode is in a second conductive layer. The first terminal electrode and the center-tap electrode are coupled through a first series combination that includes the first half-loop of each half-loop pair. The second terminal electrode and the center-tap electrode are coupled through a second series combination that includes the second half-loop of each half-loop pair. | 04-19-2012 |
20120092081 | TUNABLE RESONANT CIRCUIT IN AN INTEGRATED CIRCUIT - A tunable resonant circuit includes first and second capacitors that provide a matched capacitance between first and second electrodes of the first and second capacitors. A deep-well arrangement includes a first well disposed within a second well in a substrate. The first and second capacitors are each disposed on the first well. Two channel electrodes of a first transistor are respectively coupled to the second electrode of the first capacitor and the second electrode of the second capacitor. Two channel electrodes of a second transistor are respectively coupled to the second electrode of the first capacitor and to ground. Two channel electrodes of the third transistor are respectively coupled to the second electrode of the second capacitor and to ground. The gate electrodes of the first, second, and third transistors are responsive to a tuning signal, and an inductor is coupled between the first electrodes of the first and second capacitors. | 04-19-2012 |
20120074589 | CORNER STRUCTURE FOR IC DIE - One or more integrated circuit chips are flip-chip bonded to a first surface of a substrate. A contact array is fabricated on a second surface of the substrate. Corner structures attached to the integrated circuit chip cover at least two corners of the IC chip. | 03-29-2012 |
20120060038 | PROTECTING AGAINST DIFFERENTIAL POWER ANALYSIS ATTACKS ON SENSITIVE DATA - An embodiment of a method is disclosed for protecting sensitive data from discovery during an operation performed on input data with the sensitive data. This embodiment of the method includes performing the operation on a first quantity of random data with the sensitive data using a circuit arrangement before performing the operation with the sensitive data on the input data using the circuit arrangement. After performing the operation with the sensitive data on the first quantity of the random data, the operation is performed with the sensitive data on the input data using the circuit arrangement. After performing the operation with the sensitive data on the input data, the operation is performed with the sensitive data on a second quantity of random data using the circuit arrangement. | 03-08-2012 |
20120060037 | PROTECTING AGAINST DIFFERENTIAL POWER ANALYSIS ATTACKS ON DECRYPTION KEYS - An embodiment of a method is disclosed for protecting a key from discovery during decryption of a data stream. This embodiment of the method includes decrypting the data stream with the key. Before completing decryption of the data stream, the method checks consistency between a decrypted portion of the data stream and expected data using a circuit arrangement. In response to an inconsistency between the decrypted portion and the expected data, a tampering signal is generated to indicate tampering is suspected. | 03-08-2012 |
20120032326 | AIR THROUGH-SILICON VIA STRUCTURE - A silicon substrate has a conductive via extending from a first surface of the silicon substrate through the silicon substrate to a second surface of the silicon substrate. A dielectric via extends from the second surface of the silicon substrate toward the first surface of the silicon substrate. | 02-09-2012 |
20120019292 | CONFIGURATION OF A MULTI-DIE INTEGRATED CIRCUIT - An embodiment of an integrated circuit (IC) is described. This embodiment of the IC includes an interposer; a first die on an interposer, where the first die generates a global signal propagated through the interposer; and a second die on the surface of the interposer and coupled to the global signal. The first die and the second die each is configured to implement a same operating state concurrently in response to the global signal. | 01-26-2012 |
20120007188 | INTEGRATED CIRCUIT DEVICE WITH STRESS REDUCTION LAYER - An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a reduced-stress dual stress liner NMOS device having a stress reduction layer that extends between the tensile stress layer and the NMOS gate film stack, and a reduced-stress dual stress liner PMOS device having a stress reduction layer that extends between the compressive stress layer and the PMOS gate film stack. In embodiments of the invention additional reduced-stress dual stress liner NMOS devices and reduced-stress PMOS devices are formed by altering the thickness and/or the material properties of the stress reduction layer. | 01-12-2012 |
20120002392 | ELECTRO-STATIC DISCHARGE PROTECTION FOR DIE OF A MULTI-CHIP MODULE - Electro-static discharge (“ESD”) protection for a die of a multi-chip module is described. A contact has an externally exposed surface after formation of the die and prior to assembly of the multi-chip module. The contact is for a die-to-die interconnect of the multi-chip module. The contact is for an internal node of the multi-chip module after the assembly of the multi-chip module. A driver circuit is coupled to the contact and has a first input impedance. A discharge circuit is coupled to the contact for electrostatic discharge protection of the driver circuit and has a first forward bias impedance associated with a first discharge path. The first forward bias impedance is a fraction of the first input impedance. | 01-05-2012 |
20110316572 | TESTING DIE-TO-DIE BONDING AND REWORK - A method of testing a multi-die integrated circuit (IC) can include testing an inter-die connection of the multi-die IC. The inter-die connection can include a micro-bump coupling a first die to a second die. The method can include detecting whether a fault occurs during testing of the inter-die connection. Responsive to detecting the fault, the multi-die integrated circuit can be designated as including a faulty inter-die connection. Also described is an integrated circuit that includes a first die, a second die on which the first die may be disposed, a plurality of inter-die connections coupling the first die to the second die, and a plurality of probe pads, where each probe pad is coupled to at least one of the inter-die connections. | 12-29-2011 |
20110302356 | SCALABLE MEMORY INTERFACE SYSTEM - A memory interface system can include a memory controller configured to operate at a first operating frequency. A physical interface block can be coupled to the memory controller. The physical interface block can be configured to communicate with the memory controller at the first operating frequency and communicate with a memory device at a second operating frequency that is independent of the first operating frequency. | 12-08-2011 |
20110299351 | INPUT/OUTPUT BANK ARCHITECTURE FOR AN INTEGRATED CIRCUIT - An integrated circuit can include an input/output (I/O) bank. The I/O bank can include a plurality of byte clock groups. Each byte clock group can include at least one phaser configured to clock circuit elements of the byte clock group at a frequency at which a source synchronous device coupled to the byte clock group communicates data. | 12-08-2011 |
20110299347 | DYNAMIC DETECTION OF A STROBE SIGNAL WITHIN AN INTEGRATED CIRCUIT - A method of processing a strobe signal can include oversampling a strobe signal received from a source synchronous device and determining an amount of time between sending a read request to the source synchronous device and detecting a first pulse of the strobe signal according to the oversampling. The method also can include squelching the strobe signal for the amount of time responsive to at least one subsequent read request. | 12-08-2011 |
20110298511 | STROBE SIGNAL MANAGEMENT TO CLOCK DATA INTO A SYSTEM - A method of communicating with a source synchronous device can include determining an expected number of pulses of a strobe signal to be received in response to a first read request directed to the source synchronous device and receiving the strobe signal from the source synchronous device. Pulses in the strobe signal can be counted. Responsive to detecting a last pulse of the expected number of pulses of the strobe signal, the strobe signal can be replaced with a reference signal that is phase and frequency aligned with the strobe signal. | 12-08-2011 |
20110291758 | DIFFERENTIAL COMPARATOR CIRCUIT HAVING A WIDE COMMON MODE INPUT RANGE - In one embodiment of the invention, a circuit arrangement is provided. The circuit arrangement includes a plurality of differential amplifiers, coupled in parallel, including at least a first differential amplifier and a second differential amplifier. Each differential amplifier includes an adjustable current control circuit coupled to limit a tail current passing through the differential amplifier. | 12-01-2011 |
20110291287 | THROUGH-SILICON VIAS WITH LOW PARASITIC CAPACITANCE - A device has a silicon substrate with a via extending from a first surface of the silicon substrate having a conductor portion. A first dielectric portion surrounds the conductor portion. A second dielectric portion is disposed between a first silicon portion and the silicon substrate. | 12-01-2011 |
20110276321 | DEVICE SPECIFIC CONFIGURATION OF OPERATING VOLTAGE - A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined along with a default voltage value corresponding to a default gate-level delay. A voltage scaling factor corresponding to the minimum voltage and default voltage values is determined. The circuit design is synthesized such that the synthesized design includes the voltage scaling value. The synthesized design specifies setting an operating voltage to a value of a startup voltage value scaled by the voltage scaling value. | 11-10-2011 |
20110254602 | LOCKSTEP SYNCHRONIZATION AND MAINTENANCE - A method and circuit are provided for synchronizing a first circuit and a second circuit. The first and second circuits are signaled to each generate respective waveform outputs. A phase difference is determined between the generated waveform output from the first and second circuits. A clock of the first circuit and/or second circuit is adjusted by an amount corresponding to the determined phase difference. In response to the phase difference being less than a threshold value, the first and second circuits are signaled to begin normal operation. | 10-20-2011 |
20110252244 | METHOD AND INTEGRATED CIRCUIT FOR SECURE ENCRYPTION AND DECRYPTION - In one embodiment of the present invention, a secure cryptographic circuit arrangement is provided. The secure cryptographic circuit includes a cryptographic processing block, a spreading sequence generator, and a delay control circuit. The cryptographic processing block has a plurality of signal paths. One or more of the plurality of signal paths includes respective adjustable delay circuits. The spreading sequence generator is configured to output a sequence of pseudo-random numbers. The delay control circuit has an input coupled to an output of the spreading sequence number generator and one or more outputs coupled to respective delay adjustment inputs of the adjustable delay circuits. The delay control circuit is configured to adjust the adjustable delay circuits based on the pseudo-random numbers. | 10-13-2011 |
20110248811 | STACKED DUAL INDUCTOR STRUCTURE - The dual inductor structure can include a first inductor including a first plurality of coils. Each coil of the first plurality of coils can be disposed within a different one of a plurality of conductive layers. The coils of the first plurality of coils can be vertically stacked and concentric to a vertical axis. The dual inductor structure further can include a second inductor including a second plurality of coils. Each of the second plurality of coils can be disposed within a different one of the plurality of conductive layers. The coils of the second plurality of coils can be vertically stacked and concentric to the vertical axis. Within each conductive layer, a coil of the second plurality of coils can be disposed within an inner perimeter of a coil of the first plurality of coils. | 10-13-2011 |
20110248787 | VARACTOR CIRCUIT AND VOLTAGE-CONTROLLED OSCILLATION - A varactor circuit and voltage-controlled oscillation are described. The varactor circuit includes a first varactor, a second varactor, a third varactor, and a fourth varactor. A first source-drain node of the first varactor and a second source-drain node of the second varactor are coupled to a first input node. A first gate node for the first varactor is coupled to a first output node. A second gate node for the second varactor is coupled to a second output node. A third gate node for the third varactor and a fourth gate node for the fourth varactor are coupled to a second input node. A third source-drain node of the third varactor is coupled to the first output node. A fourth source-drain node of the fourth varactor is coupled to the second output node. In other embodiments, varactor circuits block and re-center VCO output CML. | 10-13-2011 |
20110222590 | SYSTEM AND METHOD FOR PILOT TONE ASSISTED SELECTED MAPPING - A method is provided for communicating a data value and pilot tone within the same communication sub-carrier of a communication channel. A first reference phase corresponding to a first data value is selected. A pilot tone having the first reference phase is generated. The generated pilot tone is transmitted. The transmitted pilot tone is received. A phase of the received pilot tone is determined. A second data value is determined from the phase of the received pilot tone. The second data value is stored in an electronic storage medium. | 09-15-2011 |
20110215834 | PROGRAMMABLE INTEGRATED CIRCUIT WITH MIRRORED INTERCONNECT STRUCTURE - A programmable integrated circuit (IC) with mirrored interconnect structure. The IC includes a plurality of arrangements, which are horizontally arranged. Each arrangement includes a first logic column, an interconnect column, and a second logic column. Each interconnect column includes programmable interconnect blocks ( | 09-08-2011 |
20110215465 | MULTI-CHIP INTEGRATED CIRCUIT - An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip. | 09-08-2011 |
20110210443 | SEMICONDUCTOR DEVICE HAVING BUCKET-SHAPED UNDER-BUMP METALLIZATION AND METHOD OF FORMING SAME - An embodiment of a method of forming a semiconductor device that includes a substrate having an active layer and interconnect formed on the active layer is described. The method includes: forming a dielectric layer above the interconnect having a tapered via exposing at least a portion of a first metal layer; forming an under-bump metallization (UBM) layer over the tapered via and the first metal layer to form a UBM bucket; and forming a dielectric cap layer over the dielectric layer and a portion of the UBM layer. The UBM bucket is configured to support a solder ball and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated. | 09-01-2011 |
20110191729 | Method and Apparatus for Interconnect Layout in an Integrated Circuit - An embodiment of the invention relates to a computer-implemented method of designing an integrated circuit (IC). In this embodiment, layout data describing conductive layers of the integrated circuit on a substrate is generated according to design specification data for the integrated circuit. The conductive layers include a topmost layer of bond pads. Metal structures in the layout data are modified to maximize metal density in a superimposed plane of the conductive layers within a threshold volume under each of the bond pads. A description of the layout data is generated on one or more masks for manufacturing the integrated circuit. By maximizing metal density in the superimposed plane, vertical channels through the dielectric material in the interconnect are reduced or eliminated. Thus, alpha particles cannot readily penetrate the interconnect and reach the underlying semiconductor substrate, reducing soft errors, such as single event upsets in memory cells. | 08-04-2011 |
20110147949 | HYBRID INTEGRATED CIRCUIT DEVICE - An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die. | 06-23-2011 |
20110125819 | MINIMUM MEAN SQUARE ERROR PROCESSING - A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication. | 05-26-2011 |
20110124333 | FEMTOCELL CONFIGURATION USING SPECTRUM SENSING - An embodiment of the present invention provides for the ad-hoc configuration of femtocells using spectrum sensing for the selection of spectrum channels. One or more embodiments of the invention determine frequency bands that are not reserved by macrocells in a location, and perform spectrum sensing to determine communication channels in unreserved frequency bands that are being used by other femtocells in range. In this manner, femtocells can be deployed and configured in an ad-hoc manner without external coordination or control between deployed femtocells. | 05-26-2011 |
20110121438 | EXTENDED UNDER-BUMP METAL LAYER FOR BLOCKING ALPHA PARTICLES IN A SEMICONDUCTOR DEVICE - An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion. | 05-26-2011 |
20110113401 | T-COIL NETWORK DESIGN FOR IMPROVED BANDWIDTH AND ELECTROSTATIC DISCHARGE IMMUNITY - A method of generating a circuit design comprising a T-coil network includes determining inductance for inductors and a parasitic bridge capacitance of the T-coil network. The parasitic bridge capacitance is compared with a load capacitance metric that depends upon parasitic capacitance of a load coupled to an output of the T-coil network. An amount of electrostatic discharge (ESD) protection of the circuit design that is coupled to the output of the T-coil network and/or a parameter of the inductors of the T-coil network is selectively adjusted according to the comparison. The circuit design, which can specify inductance of the inductors, the amount of ESD protection, and/or the width of windings of the inductors, is outputted. | 05-12-2011 |
20110095851 | HIGH IMPEDANCE ELECTRICAL CONNECTION VIA - Vias for differential signals are typically of a lower impedance than the signal lines connected to them. The noise and reflected signals resulting in impedance mismatch may require circuits to be operated at a frequency far lower than desired. One or more embodiments of the present invention avoid impedance mismatch in circuits and achieve an advance in the art by providing a via with higher impedance through the addition of split ring resonators (SSRs) to each end of the via. | 04-28-2011 |
20110058290 | SHARED ELECTROSTATIC DISCHARGE PROTECTION FOR INTEGRATED CIRCUIT OUTPUT DRIVERS - A system for protecting metal oxide semiconductor field effect transistor (MOSFET) output drivers within an integrated circuit (IC) from an electrostatic discharge (ESD) includes a first MOSFET output driver and a second MOSFET output driver positioned within a common IC diffusion material. The system includes a contact ring coupled to the common IC diffusion material and arranged along an outer edge of a perimeter surrounding the MOSFET output drivers. A centroid of each MOSFET output driver is common with a centroid of the perimeter surrounding both MOSFET output drivers. Each MOSFET output driver has a value of substrate resistance (R | 03-10-2011 |
20110026173 | ENHANCED IMMUNITY FROM ELECTROSTATIC DISCHARGE - Enhanced electrostatic discharge (“ESD”) protection for an integrated circuit is described. An embodiment relates generally to a circuit for protection against ESD. The circuit has an input/output node and a driver. The driver has a first transistor and a second transistor. A first source/drain node of the first transistor is coupled to the input/output node. A second source/drain node of the first transistor forms a first interior node capable of accumulating charge when electrically floating. A first current flow control circuit is coupled to a discharge node and the second source/drain node of the first transistor. The first current flow control circuit is electrically oriented in a bias direction for allowing accumulated charge to discharge from the first interior node via the first current flow control circuit to the discharge node. | 02-03-2011 |
20110012633 | APPARATUS AND METHOD FOR TESTING OF STACKED DIE STRUCTURE - An integrated circuit device is described that includes a stacked die and a base die having probe pads that directly couple to test logic of the base die so as to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts disposed on a back side of the base die and through-die vias coupled to the contacts and coupled to programmable logic of the base die. In addition, the base die includes a first probe pad configured to couple test input, a second probe pad configured to couple test output and a third probe pad configured to couple control signals. Test logic of the base die is configured to couple to additional test logic of the stacked die so as to implement a scan chain for testing of the integrated circuit device. In accordance with aspects of the present invention, the first probe pad, the second probe pad and the third probe pad are coupled directly to the test logic such that configuration of the programmable logic is not required for coupling the test input, the test output and the control signal between the base die and the stacked die so as to implement the scan chain. | 01-20-2011 |
20100322352 | SPHERE DETECTOR PERFORMING DEPTH-FIRST SEARCH UNTIL TERMINATED - Systems and methods detect a communication received at receiving antennas from transmitting antennas. Each transmitting antenna transmits a symbol in a constellation. A sphere detector performs a depth-first search until the depth-first search terminates in response to a terminate signal requesting the result from the sphere detector. The depth-first search evaluates respective distances of one or mode leaf nodes in response to the communication received at the receiving antennas. The depth-first search selects the result from these nodes in response to the respective distances. The result includes a selected leaf node that identifies a corresponding symbol in the constellation for each transmitting antenna, with this symbol detected as transmitted by the transmitting antenna. | 12-23-2010 |
20100308910 | APPARATUS AND METHOD FOR PREDICTIVE OVER-DRIVE DETECTION - A method and apparatus for efficient drive level selection for, e.g., power amplifiers utilized within a wireless communication system, which utilizes digital predistortion (DPD) to adaptively and predictively select drive level. The DPD, e.g., increases the power amplifier's efficiency while maintaining spectral mask compliance within the designated frequency band of transmission. The method first determines a peak amplitude of an undistorted waveform that is to be transmitted and then predicts the maximum power that is to be transmitted by the power amplifier after the undistorted signal has been predistorted. An over-drive metric is then calculated based upon the predicted drive level of the power amplifier, which indicates whether or not the cascade of the predistorter and the power amplifier is predicted to operate linearly. The over-drive metric may then be used to ensure optimal power amplifier performance, thereby eliminating the need to use overly conservative power amplifier drive settings. | 12-09-2010 |
20100272195 | PEAK-TO-AVERAGE POWER RATIO REDUCTION WITH BOUNDED ERROR VECTOR MAGNITUDE - Method and apparatus for signal processing to minimize the peak to average power ratio of an Orthogonal Frequency Division Multiplexing (“OFDM”) or Orthogonal Frequency Division Multiple Access (“OFDMA”) signal with bounded error vector magnitude for an integrated circuit are described. An Active Constellation Extension (“ACE”) iteration, using a constellation points adjustment module, is performed. Symbols outside of a bounded region after the ACE iteration are identified. The bounded region is determined responsive to an error vector magnitude target. The symbols identified are translated to the bounded region. | 10-28-2010 |
20100258877 | INTEGRATED CIRCUIT DEVICE WITH STRESS REDUCTION LAYER - An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a reduced-stress dual stress liner NMOS device having a stress reduction layer that extends between the tensile stress layer and the NMOS gate film stack, and a reduced-stress dual stress liner PMOS device having a stress reduction layer that extends between the compressive stress layer and the PMOS gate film stack. In embodiments of the invention additional reduced-stress dual stress liner NMOS devices and reduced-stress PMOS devices are formed by altering the thickness and/or the material properties of the stress reduction layer. | 10-14-2010 |
20100201883 | INTEGRATED CIRCUIT HAVING A CIRCUIT FOR AND METHOD OF PROVIDING INTENSITY CORRECTION FOR A VIDEO - A method of providing intensity correction for a video is disclosed. The method may comprise evaluating a portion of a frame of the video; determining a difference in intensity of a current block of the frame with the corresponding block of the previous frame; correcting all blocks of the frame with local intensity correction if a first set of parameters is met; and correcting the current block of the frame with both global intensity correction and local intensity correction if the first set of parameters is not met. An integrated circuit having a circuit for providing intensity correction for a video is also disclosed. | 08-12-2010 |
20100199136 | METHOD AND APPARATUS FOR DETECTING AND CORRECTING ERRORS IN A PARALLEL TO SERIAL CIRCUIT - A circuit has first portion that receives data at a first rate; a second portion that outputs data at a second rate synchronized to and different from the first rate; a third portion that transfers data from the first portion to the second portion; and a fourth portion that generates an error detected signal in response to a disruption in the synchronism between the first and second rates. A different aspect involves a method that includes: receiving data at a first rate in a first portion; transferring data from the first portion to a second portion; outputting data at a second rate from the second portion, the second rate being synchronized to and different from the first rate; and generating an error detected signal in response to detection of a disruption in the synchronism between the first and second rates. | 08-05-2010 |
20100193870 | TECHNIQUES FOR IMPROVING TRANSISTOR-TO-TRANSISTOR STRESS UNIFORMITY - An integrated circuit ( | 08-05-2010 |
20100193229 | BARRIER LAYER TO PREVENT CONDUCTIVE ANODIC FILAMENTS - A through hole is formed in a circuit board ( | 08-05-2010 |
20100192118 | METHOD OF AND CIRCUIT FOR IMPLEMENTING A FILTER IN AN INTEGRATED CIRCUIT - According to an embodiment of the invention, a method of configuring a filter in a circuit to be implemented in an integrated circuit is disclosed. The method comprises receiving a high level design of the circuit; identifying a filter in the high level design; analyzing coefficients of the filter; and transforming the filter of the high level design to a filter using a processing block of the circuit configured to accommodate a common coefficient, wherein the processing block is coupled to receive taps associated with the common coefficient. A computer program product and a circuit for configuring a filter in a circuit to be implemented in an integrated circuit are also disclosed. | 07-29-2010 |
20100191786 | DIGITAL SIGNAL PROCESSING BLOCK WITH PREADDER STAGE - A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus. | 07-29-2010 |
20100188787 | METHOD AND APPARATUS TO REDUCE FOOTPRINT OF ESD PROTECTION WITHIN AN INTEGRATED CIRCUIT - An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground. | 07-29-2010 |
20100188142 | CIRCUIT FOR AND METHOD OF REDUCING POWER CONSUMPTION IN INPUT PORTS OF AN INTEGRATED CIRCUIT - A circuit for reducing power consumption in input ports of an integrated circuit is disclosed. The circuit comprises a plurality of receiver circuits of the integrated circuit for receiving input signals coupled to the integrated circuit; and a bias current generator coupled to the plurality of receiver circuits, the bias current generator providing a bias voltage for each receiver circuit of the plurality of receiver circuits to mirror the current in the bias current generator in each of the receiver circuits. A method of reducing power consumption in input ports of an integrated circuit is also disclosed. | 07-29-2010 |
20100183081 | GENERIC BUFFER CIRCUITS AND METHODS FOR OUT OF BAND SIGNALING - Circuits and methods for a differential signal interface for coupling differential signals at a first frequency on a pair of opposite polarity signals to a multiple gigabit transceiver with generic buffers for receiving, transmitting or transceiving out of band signals at a second frequency lower than the first frequency are disclosed. Termination networks are provided coupling generic input buffers to respective ones of the pair of opposite polarity signals for receiving out of band signals where the opposite polarity signals are placed at voltages so that the differential voltage between them is below a threshold voltage. Methods for providing generic buffers with multiple gigabit transceivers for receiving and transmitting out of band signals on a differential signal interface are provided. Out of band signals are received when the out of band signaling protocol is not known. | 07-22-2010 |
20100142243 | DATA STORAGE SYSTEM WITH REMOVABLE MEMORY MODULE HAVING PARALLEL CHANNELS OF DRAM MEMORY AND FLASH MEMORY - A data storage system | 06-10-2010 |
20100127782 | Common Centroid Electrostatic Discharge Protection for Integrated Circuit Devices - A method of protecting a circuit design implemented within an integrated circuit (IC) from electrostatic discharge (ESD) can include positioning a device array pair comprising first and second device arrays on the IC to share a common centroid, wherein the first and second device arrays are matched. An ESD diode array pair comprising first and second ESD diode arrays can be positioned on the IC adjacent to a first perimeter encompassing the first and second device arrays, wherein the first and second ESD diode arrays share the common centroid and are matched. A cathode terminal of each ESD diode of the first ESD diode array can be coupled to an input of the first device array, and a cathode terminal of each ESD diode of the second ESD diode array can be coupled to an input of the second device array. | 05-27-2010 |
20100127351 | INTEGRATED CAPACITOR WITH INTERLINKED LATERAL FINS - A capacitor in an integrated circuit (“IC”) has a first node conductor formed in a first metal layer of the IC with a first spine extending along a first direction, a first vertical element extending from the first spine along a second direction perpendicular to the first direction. A first capital element extends along the first direction, and a first serif element extends from the capital element. The capacitor also has a second node conductor having a second spine, a second vertical element extending from the second spine toward the first spine, a second capital element, and a second serif element extending from the second capital between the first vertical element and the first serif element. | 05-27-2010 |
20100127349 | INTEGRATED CAPACITOR WITH ARRAY OF CROSSES - A capacitor in an integrated circuit (“IC”) has a first plurality of conductive crosses formed in a layer of the IC electrically connected to and forming a portion of a first node of the capacitor and a second plurality of conductive crosses formed in the metal layer of the IC. The conductive crosses in the second plurality of conductive crosses are electrically connected to and form a portion of a second node of the capacitor and capacitively couple to the first node. | 05-27-2010 |
20100127348 | INTEGRATED CAPICITOR WITH CABLED PLATES - A capacitor in an integrated circuit (“IC”) has a distribution grid formed in a first patterned metal layer of the integrated circuit and a first vertical conductive filament connected to and extending away from the distribution grid along a first direction. A second vertical conductive filament is connected to the distribution grid and extends in the opposite direction. First and second grid plates are formed in the metal layers above and below the first patterned metal layer. The grid plates surround the first and second vertical conductive filaments. The distribution grid, first vertical conductive filament and second vertical conductive filament are connected to and form a portion of a first node of the capacitor and the first grid plate and the second grid plate are connected to and form a portion of a second node of the capacitor. | 05-27-2010 |
20100127347 | SHIELDING FOR INTEGRATED CAPACITORS - A capacitor in an integrated circuit (“IC”) includes a core capacitor portion having first conductive elements electrically connected to and forming a part of a first node of the capacitor formed in a first layer and second conductive elements electrically connected to and forming a part of a second node of the capacitor formed in the first layer. The first and second conductive elements alternate in the first conductive layer. Third conductive elements electrically connected to and forming a part of the first node are formed in a second layer adjacent to the first layer. The capacitor also includes a shield capacitor portion having fourth conductive elements formed in at least first, second, third, and fourth layers. The shield capacitor portion is electrically connected to and forms a part of the second node of the capacitor and surrounds the first and third conductive elements. | 05-27-2010 |
20100127309 | INTEGRATED CAPACITOR WITH ALTERNATING LAYERED SEGMENTS - A capacitor in an integrated circuit (“IC”) has a first node plate link formed in a first metal layer of the IC electrically connected to and forming a portion of a first node of the capacitor extending along a first axis (y) and a second node plate link formed in a second metal layer of the IC extending along the axis and connected to the first node plate with a via. A third node plate link formed in the first metal layer is electrically connected to and forming a portion of a second node of the capacitor and extends along a second axis (x) of the node plate array transverse to the first node plate link, proximate to an end of the first node plate link and overlying a portion of the second node plate link. | 05-27-2010 |
20100079182 | METHOD AND APPARATUS FOR COUNTER-BASED CLOCK SIGNAL ADAPTATION - A method and apparatus to implement clock signal adaptation is provided to characterize an input clock signal that is to be adapted and in response, generate adaptation updates at each subsequent clock cycle of the input clock signal. In a first embodiment, clock signal adaptation occurs through duty cycle correction (DCC) to substantially achieve a 50% duty cycle. In an alternate embodiment, clock signal adaptation occurs through a multiplication operation that is applied to the clock signal to be adapted, whereby the multiplication operation is parameterizable to allow odd/even multiplication. In an alternate embodiment, clock signal adaptation occurs through a phase-shift operation that is applied to the clock signal to be adapted, whereby the phase-shift operation is parameterizable to allow all possible fractions and percentages of phase shifts. | 04-01-2010 |
20100070737 | ADDRESS GENERATION - Address generation by an integrated circuit is described. An aspect relates generally to an address generator which has first and second processing units. The second processing unit is coupled to receive a stage output from the first processing unit and configured to provide an address output. The stage output is in a first range, and the address output is in a second range. The first range is from −K to −1 for K a block size, and the second range is from 0 to K-1. | 03-18-2010 |
20100052780 | METHOD OF AND CIRCUIT FOR REDUCING DISTORTION IN A POWER AMPLIFIER - An integrated circuit having a circuit for reducing distortion in a power amplifier is disclosed. The integrated circuit comprises a predistortion circuit coupled to receive a signal to be amplified; sample capture buffers coupled to an output of the predistortion circuit and an input/output port of the integrated circuit; and an estimator circuit coupled to the sample capture buffers, wherein the estimator circuit generates parameters for the predistortion circuit based upon the output of the predistortion circuit and an output of the power amplifier received at the input/output port of the integrated circuit. A method of reducing distortion in a power amplifier is also disclosed. | 03-04-2010 |
20100040177 | MIMO Symbol Detection for SNR Higher and Lower than a Threshold - A system detects symbols communicated from multiple transmitting antennas to multiple receiving antennas. A first detector determines the symbols from respective partial distances of potential choices for symbols from a constellation. A second detector determines the symbols from respective partial distances of more potential choices. The first and second detectors determine their partial distances from signals received at the receiving antennas. The second detector has a lower bit error rate than the first detector. The potential choices for the second antenna are smaller than the potential choices for the first antenna in response to a signal-to-noise ratio (SNR) being higher than a threshold. An evaluator estimates the SNR of the signals received at the receiving antennas. The evaluator enables the first detector in response to the SNR being lower than the threshold, and the evaluator enables the second detector in response to the SNR being higher than the threshold. | 02-18-2010 |
20100008451 | Symbol Detection in a MIMO Communication System - Circuits are provided for detecting symbols transmitted from multiple transmitting antennas to multiple receiving antennas. A circuit includes distance blocks, selectors, and an identifier block. Each distance-block includes at least one sub-block, and each sub-block inputs a candidate for a corresponding transmitting antenna. The sub-block determines partial distances for pairings of the candidate and each symbol in a constellation from a partial distance of the candidate and signals received at the receiving antennas. At least one selector assigns each pairing for each candidate for a corresponding transmitting antenna to a bin having a range that includes the partial distance of the pairing. The selector selects candidates for a successive transmitting antenna from the bins having the smaller ranges. The identifier block selects a final candidate that is one of the pairings for a last transmitting antenna having a smaller partial distance. | 01-14-2010 |
20100007565 | Detecting In-Phase and Quadrature-Phase Amplitudes of MIMO Communications - Circuits detect communications from multiple transmitting antennas to multiple receiving antennas. A respective first block for each non-initial transmitting antenna determines partial distances for pairings of a first candidate and a quadrature-phase amplitude. A respective second block for the initial transmitting antenna determines partial distances for combinations of phase amplitudes. A respective second block for each non-initial transmitting antenna determines partial distances for pairings of a second candidate and an in-phase amplitude. A respective first selector for each non-initial transmitting antenna selects the first candidates from the pairings for the respective second block having smaller partial distances. A respective second selector for each non-initial transmitting antenna selects the second candidates from the pairings for the respective first block having smaller partial distances. An identifier circuit selects a final candidate with a smaller partial distance from the pairings of the respective second block for the last transmitting antenna. | 01-14-2010 |
20090290071 | CIRCUIT FOR AND METHOD OF RECEIVING VIDEO DATA - A circuit of an integrated circuit for receiving video data having a plurality of data streams of pixel data and a pixel clock is disclosed. The circuit comprises a plurality of data recovery circuits, each data recovery circuit coupled to receive a corresponding data stream of the plurality of data streams and having a phase shifter generating a clock signal used to receive the data stream; and a channel deskew circuit coupled to receive the output of each data recovery circuit and the pixel clock. A method of receiving video data is also disclosed. | 11-26-2009 |
20090289667 | Clock Generation Using a Fractional Phase Detector - Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output clock signal. The frequency of the output clock signal is a product from multiplying the frequency for the input signal and an integer ratio. The circuit includes an accumulator, a fractional phase detector, and a loop filter. The accumulator periodically adds a numerical offset value to a numerical phase value. The output clock signal is generated from this numerical phase value. The fractional phase detector generates from the numerical phase value a respective numerical phase error for each of the transitions of the input signal. The loop filter generates the numerical offset value from a filtering of the respective numerical phase errors. | 11-26-2009 |
20090276599 | CONFIGURABLE TRANSACTIONAL MEMORY FOR SYNCHRONIZING TRANSACTIONS - A configurable transactional memory synchronizes transactions from clients. The configurable transactional memory includes a memory buffer and a transactional buffer. The memory buffer includes allocation control and storage, and the allocation control is configurable to selectively allocate the storage between a transactional buffer and a data buffer for the data words. The transactional buffer stores state indicating each combination of a data word and a client for which the data word is referenced by a write access in the transaction in progress from the client. The transactional arbiter generates the completion status for the transaction in progress from each client. The completion status is either committed for no collision or aborted for a collision. A collision is an access that references a data word of the transaction from the client following a write access that references the data word of another transaction in progress from another client. | 11-05-2009 |
20090235222 | CREATING A STANDARD CELL CIRCUIT DESIGN FROM A PROGRAMMABLE LOGIC DEVICE CIRCUIT DESIGN - A computer-implemented method of converting a circuit design for a programmable logic device (PLD) to a standard cell circuit design can include unmapping a PLD circuit design to a gate level netlist ( | 09-17-2009 |
20090232254 | Detector Using Limited Symbol Candidate Generation for MIMO Communication Systems - A circuit detects symbols transmitted from multiple transmitting antennas to multiple receiving antennas. A distance block for an initial transmitting antenna in an ordering of the transmitting antennas determines a distance value for each symbol in a constellation. A selector block selects a limited number of candidates for the initial transmitting antenna from the symbols having smaller distance values. For each first and successive second transmitting antenna in the ordering, a distance-selector block selects a candidate for the second transmitting antenna for each candidate for the first transmitting antenna. The candidate for the second transmitting antenna is a pairing having a smaller distance value among the pairings of the candidate for the first transmitting antenna and the symbols. An identifier block selects a last candidate having a smaller distance value among the candidates for a last transmitting antenna in the ordering. The last candidate includes the detected symbols. | 09-17-2009 |
20090224400 | SEMICONDUCTOR ASSEMBLY HAVING REDUCED THERMAL SPREADING RESISTANCE AND METHODS OF MAKING SAME - Semiconductor assemblies having reduced thermal spreading resistance and methods of making the same are described. In an example, a semiconductor device includes a primary integrated circuit (IC) die and at least one secondary IC die mounted on the primary IC die. A heat extraction element includes a base mounted to the semiconductor device such that each of the at least one secondary IC die is between the primary IC die and the heat extraction element. At least one dummy fill is adjacent the at least one secondary IC die, and each thermally couples the primary IC die to the heat extraction element. | 09-10-2009 |
20090213947 | BLOCK BOUNDARY DETECTION FOR A WIRELESS COMMUNICATION SYSTEM - Method and apparatus for block boundary detection is described. A signal is received. The signal is quantized to provide a quantized signal to at least one correlator, the quantized signal being a sequence of samples. The sequence of samples and a reference template including totaling partial results from the at least one correlator are cross-correlated to provide a result, the result being a symbol timing synchronization responsive to the cross-correlation also known as block boundary detection. The cross-correlation is provided in part by combining by exclusive-ORing a regression vector obtained from the sequence of samples and a coefficient term vector obtained from the reference template. | 08-27-2009 |
20090213946 | PARTIAL RECONFIGURATION FOR A MIMO-OFDM COMMUNICATION SYSTEM - Partial reconfiguration of programmable logic for supporting a Multiple-input, Multiple-Output Orthogonal Frequency Division Multiplexing (“MIMO-OFDM”) communication system is described. A PHY block in a programmable device may be instantiated generally in part in programmable logic of the programmable device. Control information is obtained for a network node when deployed and/or from a wireless transmission of a packet or frame, which is demodulated in the PHY block. Responsive to the control information demodulated, bitstream information is obtained to configure the portion of the PHY block using the programmable logic of the programmable device. | 08-27-2009 |
20090210731 | CIRCUIT FOR AND METHOD OF MINIMIZING POWER CONSUMPTION IN AN INTEGRATED CIRCUIT DEVICE - A method of minimizing power consumption in an integrated device is disclosed. The method comprises providing a plurality of circuit blocks having circuits for performing logic functions, wherein each circuit block consumes power in a static state; coupling one of a plurality of operating voltages to each circuit block of the plurality of circuit blocks; enabling a reduction of power consumed by a first set of circuit blocks by way of a first power reduction signal; and enabling a reduction of power consumed by a second set of circuit blocks by way of a second power reduction signal. A circuit for minimizing power consumption in a device is also disclosed. | 08-20-2009 |
20090173520 | Reduction of jitter in a semiconductor device by controlling printed ciucuit board and package substrate stackup - A model and method are provided for lowering device jitter by controlling the stackup of PCB planes so as to minimize inductance between a FPGA and PCB voltage planes for critical core voltages within the FPGA. Furthermore, a model and method are provided for lowering jitter by controlling the stackup of package substrate planes so as to minimize inductance between a die and substrate voltage planes for critical core voltages within the die. | 07-09-2009 |
20090160482 | Formation of a hybrid integrated circuit device - Formation of a hybrid integrated circuit device ( | 06-25-2009 |
20090150892 | Interrupt controller for invoking service routines with associated priorities - An interrupt controller efficiently manages execution of tasks by a multiprocessor computing system. The interrupt controller has inputs for receiving service requests for invoking service routines. The service routines have higher priorities than the tasks executed on the processors. Associated with each processor is a register for storing the priority of the task executing on the processor. A comparator coupled to the processors determines the processor executing the task having a lower priority among the priorities of the tasks executing on the processors. For each service request received, a distributor generates an interrupt request for invoking the service routine of the service request on the processor with the lower priority. The register with the lower priority is set to the higher priority of the service routine in response to the interrupt request. For each processor, the interrupt controller has an output for transmitting the interrupt request to the processor. | 06-11-2009 |
20090121737 | CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCONNECT IMPACT ON SIGNAL DELAY - An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified. | 05-14-2009 |
20090116585 | ANALOG FRONT-END HAVING BUILT-IN EQUALIZATION AND APPLICATIONS THEREOF - An analog front-end having built-in equalization includes a control module and a tunable gain stage. The control module is operably coupled to provide a frequency response setting based on a channel response of a channel providing high-speed serial data to the analog front-end. The tunable gain stage includes a frequency dependent load and an amplifier input section. The frequency dependent load is adjusted based on the frequency response setting. The amplifier input section is operably coupled to the frequency dependent load and receives the high-speed serial data. In conjunction with the frequency dependent load, the amplifier input section amplifies and equalizes the high-speed serial data to produce an amplified and equalized serial data. | 05-07-2009 |
20090108337 | Method of and circuit for protecting a transistor formed on a die - A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed. | 04-30-2009 |
20090042389 | Double exposure semiconductor process for improved process margin - A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the critical dimensions of the polysilicon interconnect structure are formed without the need to execute a photoresist trimming procedure. Accordingly, only an etch process is executed, which provides higher resolution processing to create the critical dimensions needed during the second processing sequence. | 02-12-2009 |
20080303152 | Contact pad and method of forming a contact pad for an integrated circuit - A contact pad in an integrated circuit is disclosed. The contact pad comprises a flat portion comprising a base of the contact pad; a plurality of projections extending from and substantially perpendicular to the flat portion; and a solder ball attached to the projections and the flat portion. A method of forming a contact pad is also disclosed. | 12-11-2008 |