Super Talent Electronics, Inc. Patent applications |
Patent application number | Title | Published |
20120309231 | DUAL-PERSONALITY EXTENDED USB PLUGS AND RECEPTACLES USING WITH PCBA AND CABLE ASSEMBLY - A USB plug receptacle includes a connector substrate having a tongue portion having a first set of electrical contact pins disposed on a top surface of the tongue portion, a second set of a plurality of electrical pins disposed on a bottom surface of the tongue portion, a third set of electrical contact pins disposed on an opposite end of the tongue portion. The USB plug receptacle further includes a metal case made of a sheet of electrically conductive metal plate by blanking the sheet into a generally tubular shape to receive and enclose the connector substrate. When the connector substrate is inserted into the metal case, the third set of electrical contact pins are exposed outside of the metal case and the third set of electrical contact pins can be mounted on first and second sets of electrical contact pads of a printed circuit board assembly. | 12-06-2012 |
20120284587 | Super-Endurance Solid-State Drive with Endurance Translation Layer (ETL) and Diversion of Temp Files for Reduced Flash Wear - A flash drive has increased endurance and longevity by reducing writes to flash. An Endurance Translation Layer (ETL) is created in a DRAM buffer and provides temporary storage to reduce flash wear. A Smart Storage Switch (SSS) controller assigns data-type bits when categorizing host accesses as paging files used by memory management, temporary files, File Allocation Table (FAT) and File Descriptor Block (FDB) entries, and user data files, using address ranges and file extensions read from FAT. Paging files and temporary files are never written to flash. Partial-page data is packed and sector mapped by sub-sector mapping tables that are pointed to by a unified mapping table that stores the data-type bits and pointers to data or tables in DRAM. Partial sectors are packed together to reduce DRAM usage and flash wear. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails. | 11-08-2012 |
20120278543 | Flash-Memory Device with RAID-type Controller - A smart flash drive has one or more levels of smart storage switches and a lower level of single-chip flash devices (SCFD's). A SCFD contains flash memory and controllers that perform low-level bad-block mapping and wear-leveling and logical-to-physical block mapping. The SCFD report their capacity, arrangement, and maximum wear-level count (WLC) and bad block number (BBN) to the upstream smart storage switch, which stores this information in a structure register. The smart storage switch selects the SCFD with the maximum BBN as the target and the SCFD with the lowest maximum WLC as the source of a swap for wear leveling when a WLC exceeds a threshold that rises over time. A top-level smart storage switch receives consolidated capacity, arrangement, WLC, and BBN information from lower-level smart storage switch. Data is striped and optionally scrambled by Redundant Array of Individual Disks (RAID) controllers in all levels of smart storage switches. | 11-01-2012 |
20120042120 | BACKWARD COMPATIBLE EXTENDED USB PLUG AND RECEPTACLE WITH DUAL PERSONALITY - An extended Universal-Serial-Bus (USB) connector plug and socket each have a pin substrate with one surface that supports the four metal contact pins for the standard USB interface. An extension of the pin substrate carries another 8 extension metal contact pins that mate when both the connector plug and socket are extended. The extension can be an increased length of the plug's and socket's pin substrate or a reverse side of the substrate. Standard USB connectors do not make contact with the extension metal contacts that are recessed, retracted by a mechanical switch, or on the extension of the socket's pin substrate that a standard USB connector cannot reach. Standard USB sockets do not make contact with the extension metal contacts because the extended connector's extension contacts are recessed, or on the extension of the connector pin substrate that does not fit inside a standard USB socket. | 02-16-2012 |
20120030943 | Single Shot Molding Method For COB USB/EUSB Devices With Contact Pad Ribs - A dual-personality extended USB (EUSB) system supports both USB and EUSB memory cards using an extended 9-pin EUSB socket. Each EUSB device | 02-09-2012 |
20120026661 | USB Flash Drive With Deploying And Retracting Functionalities Using Retractable Cover/Cap - A pen-type computer peripheral device includes an elongated housing containing a PCBA having a plug connector, and cap/cover that is slidably connected to a front portion of the housing. Locking structures are respectively integrally molded onto opposing surfaces of the housing and cap/cover that cooperate to prevent separation of the cap/cover from the housing. By manually pushing (sliding) the cap/cover relative to the housing, the plug connector is effectively moved between a retracted position, in which the plug connector is disposed inside the cap/cover, and a deployed position in which the plug connector extends through a front housing opening of the cap/cover such that the plug connector is operably exposed for insertion into a host system. | 02-02-2012 |
20110300724 | EXTENDED USB PLUG, USB PCBA, AND USB FLASH DRIVE WITH DUAL-PERSONALITY FOR EMBEDDED APPLICATION WITH MOTHER BOARDS - An extended universal serial bus (USB) storage device is described herein. According to one embodiment, an extended USB storage device includes a printed circuit board assembly (PCBA) having a flash memory device and a flash controller mounted thereon, and an extended USB connector plug coupled to the PCBA for providing a USB compatible interface between an external device and the flash memory device and the flash controller, wherein the extended USB connector plug includes a first end used to couple to the external device and a second end coupled to the flash memory device and the flash controller. The extended USB connector plug includes multiple communication interfaces. Other methods and apparatuses are also described. | 12-08-2011 |
20110237099 | Flash Drive With Swivel Cover - A swivel-type portable flash device includes a C-shaped swivel cover that rotates (swivels) relative to a housing between an open position in which a plug connector is exposed for insertion in a host system, and a closed position in which the plug connector is covered and protected by the swivel cover. The swivel cover is permanently rotatably connected to the housing by way of ring-shaped protrusions that are movably engaged inside corresponding recessed ring-shaped grooves formed in upper/lower walls of the housing, whereby the swivel cover is manually rotatable relative to the housing between the opened and closed positions. The swivel cover also includes locking structures (e.g., locking notches) disposed on the ring-shaped protrusions, and the housing includes second locking structures disposed in the recessed ring-shaped grooves, where the first locking structures operably engage the second locking structures to prevent rotation of the swivel cover when the plug connector is in the closed position. | 09-29-2011 |
20110213921 | Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules - A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands. | 09-01-2011 |
20110197017 | High Endurance Non-Volatile Memory Devices - High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM. | 08-11-2011 |
20110179219 | HYBRID STORAGE DEVICE - A hybrid storage device comprises both solid-state disk (SDD) and at least one hard disk drive (HDD). The hybrid storage device has at least two operational modes: concatenation and safe. According to one aspect, the total capacity of hybrid storage device is the sum of SSD and at least one HDD in a concatenation or big mode, while the total capacity is the capacity of the HDD in a safe mode. In one embodiment, HDD is configured for storing a copy of the SSD's contents in a reserved area. In another, SSD comprises more than one identical flash memory devices controlled by a RAID controller. | 07-21-2011 |
20110145489 | HYBRID STORAGE DEVICE - A hybrid storage device comprises both solid-state disk (SDD) and at least one hard disk drive (HDD). The hybrid storage device has at least two operational modes: concatenation and safe. According to one aspect, the total capacity of hybrid storage device is the sum of SSD and at least one HDD in a concatenation or big mode, while the total capacity is the capacity of the HDD in a safe mode. | 06-16-2011 |
20110093653 | MEMORY ADDRESS MANAGEMENT SYSTEMS IN A LARGE CAPACITY MULTI-LEVEL CELL (MLC) BASED FLASH MEMORY DEVICE - Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM. | 04-21-2011 |
20110066920 | Single-Chip Multi-Media Card/Secure Digital (MMC/SD) Controller Reading Power-On Boot Code from Integrated Flash Memory for User Storage - A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program. | 03-17-2011 |
20110066837 | Single-Chip Flash Device with Boot Code Transfer Capability - A Multi-Media Card (MMC) Single-Chip Flash Device (SCFD) contains a MMC flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM. Boot code and control code are selectively overwritten during a code updating operation to eliminate stocking issues. | 03-17-2011 |
20110059636 | Lipstick-Type USB Device With Tubular Housing - A USB device including a tubular housing and a rear cap assembly including a handle structure that is rotatably connected to the tubular housing to facilitate deploying and retracting a plug connector through a front opening of the housing. The plug connector is fixedly connected onto the front end of a sliding rack assembly that is disposed in housing such that the sliding rack assembly is slidable along a longitudinal axis. The sliding rack assembly includes a carrier including a carrier tray for supporting electronic devices and an elongated positioning rod extending from a rear portion of the carrier tray. The positioning rod is operably engaged with an actuator portion such that manual rotation of the rear cap handle structure relative to the housing around the longitudinal axis causes the sliding rack assembly to slide inside the housing between retracted and deployed positions. | 03-10-2011 |
20110029723 | Non-Volatile Memory Based Computer Systems - Non-volatile memory based computer systems and methods are described. According to one aspect of the invention, at least one non-volatile memory module is coupled to a computer system as main storage. The non-volatile memory module is controlled by a northbridge controller configured to control the non-volatile memory as main memory. The page size of the at least one non-volatile memory module is configured to be the size of one of the cache lines associated with a microprocessor of the computer system. According to another aspect, at least one non-volatile memory module is coupled to a computer system as data read/write buffer of one or more hard disk drives. The non-volatile memory module is controlled by a southbridge controller configured to control the non-volatile memory as an input/out device. The page size of the at least one non-volatile memory module is configured in proportion to characteristics of the hard disk drives. | 02-03-2011 |
20110016267 | Low-Power USB Flash Card Reader Using Bulk-Pipe Streaming with UAS Command Re-Ordering and Channel Separation - A flash-card reader improves transmission efficiency by using bulk streaming of multiple pipes. A bulk data-out pipe carries host write data to the card reader and can operate in parallel with a bulk data-in pipe that carries host read data that was read from a flash card attached to the card reader. Status packets do not block data packets since the he status packets are buffered through a separate status pipe, and commands are buffered through a command pipe. Flash data from multiple flash cards are interleaved as separate endpoints that share the bulk data-in pipe. A data in/out streaming state machine controls streaming bulk data through the bulk data-in and data-out pipes, while a status streaming state machine controls streaming status packets through the status pipe. Transaction overhead is reduced using bulk streaming where packets for several commands are combined into the same bulk streams. | 01-20-2011 |
20110003514 | DUAL-PERSONALITY EXTENDED USB PLUGS AND RECEPTACLES USING WITH PCBA AND CABLE ASSEMBLY - An extended USB plug connector includes a connector substrate including a frontend having a first set of electrical contact pins disposed thereon and a backend having a second set of electrical contact pins disposed thereon. The first set includes a first row of electrical contact pins disposed on a top surface of the connector substrate and a second row of electrical contact pins disposed in parallel with the first row of electrical contact pins and interior to the first row of electrical contact pins, where the second row includes more electrical contact pins than the first row. The second set of electrical contact pins includes a number of electrical contact pins equal to the first row and second row of electrical contact pins in total. The second set of electrical contact pins are used to connect to corresponding electrical contact pads disposed on a printed circuit board assembly having a USB controller and flash memory devices disposed thereon. | 01-06-2011 |
20100281209 | Press-Push Flash Drive Apparatus With Metal Tubular Casing And Snap-Coupled Plastic Sleeve - A press-push type computer peripheral “flash drive” device includes an elongated (e.g., metal) tubular casing containing a PCBA having a plug connector. A plastic housing assembly includes front and rear cap portions mounted over the open ends of the tubular casing, and a fixed plastic sleeve portion disposed in the tubular casing. The PCBA is secured to a plastic sliding rack structure that is disposed in the tubular casing and includes an actuating button protruding through a slot formed in a wall of the tubular casing. When the actuating button is manually pushed and slid along the slot, a portion of the sliding rack structure slides against the plastic sleeve portion in deploying and retracting the USB connector out of the device. | 11-04-2010 |
20100275037 | Low-Power USB SuperSpeed Device with 8-bit Payload and 9-bit Frame NRZI Encoding for Replacing 8/10-bit Encoding - A Low-power flash-memory device uses a modified Universal-Serial-Bus (USB) 3.0 Protocol to reduce power consumption. The bit clock is slowed to reduce power and the need for pre-emphasis when USB cable lengths are short in applications. Data efficiency is improved by eliminating the 8/10-bit encoder and instead encoding sync and framing bytes as 9-bit symbols. Data bytes are expanded by bit stuffing only when a series of six ones occurs in the data. Header and payload data is transmitted as nearly 8-bits per data byte while framing is 9-bits per symbol, much less than the standard 10 bits per byte. Low-power link layers, physical layers, and scaled-down protocol layers are used. A card reader converter hub allows USB hosts to access low-power USB devices. Only one flash device is accessed, reducing power compared with standard USB broadcasting to multiple devices. | 10-28-2010 |
20100248512 | USB Device With Connected Cap - A USB device including a housing and a protective cap that are slidably and/or pivotably connected together such that the protective cap is able to slide and/or pivot between an open position, in which a plug connector extending from the front of the housing is exposed for operable coupling to a host system, and a closed position, in which the protective cap is disposed over the front end portion of the housing to protect the plug connector. A pivoting/sliding mechanism is provided on the housing and cap that secures the protective cap to the housing at all times, including during transitional movements of the protective cap between the opened and closed positions. | 09-30-2010 |
20100185808 | METHODS AND SYSTEMS FOR STORING AND ACCESSING DATA IN UAS BASED FLASH-MEMORY DEVICE - Methods and systems for storing and accessing data in UAS based flash memory device are disclosed. UAS based flash memory device comprises a controller and a plurality of non-volatile memories (e.g., flash memory) it controls. Controller is configured for connecting to a UAS host via a physical layer (e.g., plug and wire based on USB 3.0) and for conducting data transfer operations via two sets of logical pipes. Controller further comprises a random-access-memory (RAM) buffer configured for enabling parallel and duplex data transfer operations through the sets of logical pipes. In addition, a Smart Storage Switch configured for connecting multiple non-volatile memory devices is included in the controller. Finally, a security module/engine/unit is provided for data security via user authentication data encryption/decryption of the device. Furthermore, the flash memory device includes an optical transceiver configured for optical connection to a host also configured with an optical transceiver. | 07-22-2010 |
20100146256 | Mixed-Mode ROM/RAM Booting Using an Integrated Flash Controller with NAND-Flash, RAM, and SD Interfaces - A Secure Digital (SD) flash microcontroller includes a memory interface to SRAM or DRAM, a flash-memory interface, and a SD interface to an SD bus. The flash memory can be on a flash bus or on the SD bus. The microcontroller is booted from boot code stored in the flash memory. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM. | 06-10-2010 |
20100122021 | USB-Attached-SCSI Flash-Memory System with Additional Command, Status, and Control Pipes to a Smart-Storage Switch - An electronic flash-memory card has additional pipes for commands and status messages so that data pipes are not clogged with commands and status messages, allowing for a higher data throughput. The command and status pipes are activated when a UAS/BOT detector detects that a host is using a USB-Attached-SCSI (UAS) mode rather than a Bulk-Only-Transfer (BOT) mode. The host can send additional commands and data without waiting for completion of a prior command when operating in UAS mode but not while operating in BOT mode. A command queue (CQ) in the device re-orders commands for accessing flash memory and merges data in a RAM buffer. Smaller 1 KB USB packets in the data pipes are merged into larger 8 KB payloads in the RAM buffer, allowing for more efficient flash access. | 05-13-2010 |
20100110647 | Molded Memory Card With Write Protection Switch Assembly - A Secure Digital device including a PCBA having passive components mounted on a PCB using surface mount technology (SMT) techniques, and active components (e.g., controller and flash memory) mounted using chip-on-board (COB) techniques. The components are mounted only on one side of the PCB, and then a molded plastic casing is formed over both sides of the PCB such that the components are encased in the plastic, and a thin plastic layer is formed over the PCB surface opposite to the components. The molded plastic casing is formed to include openings that expose metal contacts provided on the PCB, and ribs that separate the openings. The molded plastic casing defines a pre-molded switch slot that facilitates an insert-in switch assembly process for mounting a write protect switch. The write protect switch includes a movable switch button engaged in the switch slot, and a switch cap secured over the switch slot. | 05-06-2010 |
20100105251 | Micro-SD To Secure Digital Adaptor Card And Manufacturing Method - A microSD-to-SD adaptor card includes a base substrate having a lead frame structure, a protective cap forming a chamber that encloses eight microSD contact pins of the lead frame structure, and a thermoset plastic casing formed over the protective cap and exposed portions of the base substrate to provide the adaptor card with standard SD card dimensions. A rear opening facilitates insertion of a standard microSD card, whereby the eight contact pads on the microSD card are contacted by the eight microSD contact pins inside the chamber to allow electrical signals generated by the microSD card to be transmitted to a host system by way of a standard SD socket. A grip anchor pin is disposed inside the chamber to engage a grip notch disposed on the microSD card. A pre-molded switch slot is provided on the molded plastic casing, and an insert-in write protect switch is mounted after molding. | 04-29-2010 |
20100082893 | Flash Memory Controller For Electronic Data Flash Card - An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming. | 04-01-2010 |
20100082892 | Flash Memory Controller For Electronic Data Flash Card - An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input— output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming. | 04-01-2010 |
20100075517 | Flash Drive With Spring-Loaded Swivel Connector - A swivel-type computer peripheral device includes a housing and a swivel rack assembly that swivels relative to the housing between a retracted position, in which a PCBA having a plug connector mounted on the swivel rack assembly is disposed inside the housing, and a deployed position, in which the swivel rack assembly is rotated outside of the housing such that the plug connector is positioned for insertion into a host computer socket. A torsion spring is connected between the housing and the swivel rack assembly and arranged to bias the swivel rack assembly either into the deployed position or into the retracted position. A locking mechanism controlled by a push button or another actuating mechanism is used to selectively lock the swinging rack in a retracted position and a deployed position. | 03-25-2010 |
20100049878 | Differential Data Transfer For Flash Memory Card - A flash memory card includes a differential datapath that enables communications between the flash memory card and a host device to be performed using differential signals. The differential datapath can translate between the differential signals and card-specific signals that control read/write operations to the memory array of the flash memory card. The card-specific signals can be standard MultimediaCard, Secure-Digital card, Memory Stick, or CompactFlash card signals, among others. A host device that provides differential data transfer capability can include a similar differential datapath. By using differential data transfer rather than conventional clocked data transfer, overall data bandwidth between a flash memory card and a host device can be significantly increased, while simultaneously decreasing power consumption and pin requirements. | 02-25-2010 |
20100039225 | SLIDE FLASH MEMORY DEVICES - A portable USB device with an improved configuration is described herein. According to one embodiment, a portable USB device includes a core unit having a USB plug connector coupled to one or more flash memory devices and a flash controller disposed therein, where the flash controller is capable of exchanging data with a host via the USB plug connector using a bulk-only-transfer protocol. The portable USB device further includes a housing for enclosing the core unit, including a front end opening to allow the USB plug connector to be deployed. The portable USB device further includes a core unit carrier for carrying the core unit for deploying and retracting the core unit, including a slide button to allow a finger of a user to slide the USB plug connector of the core unit in and out of the housing via the front end opening of the housing. | 02-18-2010 |
20100030961 | FLASH MEMORY CONTROLLER FOR ELECTRONIC DATA FLASH CARD - An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming. | 02-04-2010 |
20100027329 | Synchronous Page-Mode Phase-Change Memory with ECC and RAM Cache - Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks. | 02-04-2010 |
20100023682 | Flash-Memory System with Enhanced Smart-Storage Switch and Packed Meta-Data Cache for Mitigating Write Amplification by Delaying and Merging Writes until a Host Read - A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries are sub-divided and portions invalidated when a new command overlaps an older command in the FIFO. Host data is aligned to page boundaries with pre- and post-fetched data filling in to the boundaries. Repeated data patterns are detected and encoded by compressed meta-data codes that are stored in meta-pattern entries in a meta-pattern cache of a meta-pattern flash block. The sector data is not written to flash. The meta-pattern entries are located using a meta-data mapping table. Storing host CRC's for comparison to incoming host data can detect identical data writes that can be skipped, avoiding a write to flash. | 01-28-2010 |
20100000655 | Memory Module Assembly Including Heat Sink Attached To Integrated Circuits By Adhesive And Clips - A memory module assembly includes two-plate heat sink attached to one or more of the integrated circuits (e.g., memory devices) of a memory module PCBA by adhesive. The adhesive is either heat-activated or heat-cured. The adhesive is applied to either the memory devices or the heat-sink plates, and then compressed between the heat-sink plates and memory module using a fixture. The fixture is then passed through an oven to activate/cure the adhesive. The two heat sink plates are then secured by a clip to form a rigid frame. | 01-07-2010 |
20090316368 | USB Package With Bistable Sliding Mechanism - A USB device including a bistable mechanism that serves to bias a plug connector into one of two stable states, where the first stable state is associated with a retracted position in which the plug connector is fully retracted inside a housing, and the second stable state is associated with a deployed position in which the plug connector extends through the front opening for coupling to a host system. Movement of the plug connector form the retracted to the deployed position is performed by manually applying a force to a handle portion that protrudes through a slot defined in the housing. The bistable mechanism resists the deploying force until an equilibrium point is reach, after which the bistable mechanism releases stored potential energy to complete the deploying process and to maintain the plug connector is the deployed position. | 12-24-2009 |
20090275224 | Lipstick-Type USB Device - A USB device including a housing and a rear cap that is rotatably connected to the housing to facilitate deploying and retracting a plug connector through a front opening of the housing. The plug connector is fixedly connected onto the front end of a sliding rack assembly that is disposed in housing such that the sliding rack assembly is slidable along a longitudinal axis. The sliding rack assembly includes a carrier including a carrier tray for supporting electronic devices and an elongated positioning rod extending from a rear portion of the carrier tray. The positioning rod is operably engaged with an actuator portion such that manual rotation of the rear cap relative to the housing around the longitudinal axis causes the sliding rack assembly to slide inside the housing between retracted and deployed positions. | 11-05-2009 |
20090273096 | High Density Memory Device Manufacturing Using Isolated Step Pads - An electronic device includes multiple IC dies stacked in an offset stacking arrangement on a substrate. Each IC die includes electrically isolated step pads that facilitates transmitting a dedicated signal between a (beginning) substrate bonding pad and a selected (terminal) contact pad of any die by way of short bonding wires that extend up the stack between the electrically isolated step pads. A memory devices includes stacked memory IC die, wherein “shared” signal transmission paths are formed by associated bonding wires that link corresponding contact pads of each memory die, and dedicated select/control signals are transmitted to each memory die by separate transmission paths formed in part by associated electrically isolated step pads. Substrate space overhung by the stack is used for passive components and IC dies. Memory controller die may be mounted on the stack and connected by dedicated transmission paths utilizing the electrically isolated step pads. | 11-05-2009 |
20090258516 | USB Device With Connected Cap - A USB device including a housing and a protective cap that are slidably and/or pivotably connected together such that the protective cap is able to slide and/or pivot between an open position, in which a plug connector extending from the front of the housing is exposed for operable coupling to a host system, and a closed position, in which the protective cap is disposed over the front end portion of the housing to protect the plug connector. A pivoting/sliding mechanism is provided on the housing and cap that secures the protective cap to the housing at all times, including during transitional movements of the protective cap between the opened and closed positions. | 10-15-2009 |
20090240873 | Multi-Level Striping and Truncation Channel-Equalization for Flash-Memory System - Truncation reduces the available striped data capacity of all flash channels to the capacity of the smallest flash channel. A solid-state disk (SSD) has a smart storage switch salvages flash storage removed from the striped data capacity by truncation. Extra storage beyond the striped data capacity is accessed as scattered data that is not striped. The size of the striped data capacity is reduced over time as more bad blocks appear. A first-level striping map stores striped and scattered capacities of all flash channels and maps scattered and striped data. Each flash channel has a Non-Volatile Memory Device (NVMD) with a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory in the NVMD. Wear-leveling and bad block remapping are preformed by each NVMD. Source and shadow flash blocks are recycled by the NVMD. Two levels of smart storage switches enable three-level controllers. | 09-24-2009 |
20090240865 | Dual-Mode Switch for Multi-Media Card/Secure Digital (MMC/SD) Controller Reading Power-On Boot Code from Integrated Flash Memory for User Storage - A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program. | 09-24-2009 |
20090204872 | Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules - A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands. | 08-13-2009 |
20090204732 | Single-Chip Multi-Media Card/Secure Digital (MMC/SD) Controller Reading Power-On Boot Code from Integrated Flash Memory for User Storage - A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program. | 08-13-2009 |
20090203168 | Manufacturing Method for a Secure-Digital (SD) Flash Card with Slanted Asymmetric Circuit Board - A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an input/output interface circuit to an external computer over a Secure-Digital (SD) interface, and a processing unit to read blocks of data from the flash-memory chip. The PCBA is encased inside an upper case and a lower case, with SD contact pads on the PCB that fit through contact openings in the upper case. Supporting end ribs under each of the SD contact pads and middle ribs support the PCB at a slanted angle to the centerline of the device. The PCB slants upward at the far end to allow more thickness for the chips mounted to the bottom surface of the PCB, and slants downward at the insertion end to position the SD contact pads near the centerline. | 08-13-2009 |
20090194616 | Sporoderm-Broken Polypore Production - A cryogenic grinding mill for grinding organic base material pieces into sub-micron-sized powder particles. An upper grinding block is rotated relative to a stationary lower grinding block by a motor, and is maintained at a temperature below −150° C. by a cryogenic system including an annular liquid nitrogen chamber disposed around the grinding blocks. The upper grinding block defines a trench for receiving base material pieces fed by a feed system, and includes through-holes that extend from the trench to a grinding region formed between the grinding surfaces of the upper and lower blocks. When the upper grinding block is rotated, the base material pieces are gravity-fed from the trench to the grinding region, and ground powder material is forced to a peripheral edge of the grinding region. The powder material is then filtered, and particles having an undesirably large size are fed back into the trench for re-grinding. | 08-06-2009 |
20090193184 | Hybrid 2-Level Mapping Tables for Hybrid Block- and Page-Mode Flash-Memory System - A hybrid solid-state disk (SSD) has multi-level-cell (MLC) or single-level-cell (SLC) flash memory, or both. SLC flash may be emulated by MLC that uses fewer cell states. A NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Most data is block-mapped and stored in MLC flash, but some critical or high-frequency data is page-mapped to reduce block-relocation copying. A hybrid mapping table has a first-level and a second level. Only the first level is used for block-mapped data, but both levels are used for page-mapped data. The first level contains a block-page bit that indicates if the data is block-mapped or page-mapped. A PBA field in the first-level table maps block-mapped data, while a virtual field points to the second-level table where the PBA and page number is stored for page-mapped data. Page-mapped data is identified by a frequency counter or sector count. SRAM space is reduced. | 07-30-2009 |
20090190277 | ESD Protection For USB Memory Devices - ESD protection for a portable electronic device is provided by sandwiching a metal ground layer between prepreg (i.e., FR4 or other non-conductive PCB material) layers to form an ESD preventive PCB structure, where the metal ground layer is electrically connected to one or more of the integrated circuit (IC) components (e.g., at least one controller die, a non-volatile memory die, oscillator and passive components) that are mounted on the PCB by way of conductive via structures, and is accessible by way of one or more conductive anchor hole structures to external grounding structures. The one or more conductive anchor hole structures are positioned such that the metal ground layer is automatically electrically connected to the chassis ground of a host system when the portable device is coupled to a plug structure of the host system, e.g., by way of a metal connector jacket. | 07-30-2009 |
20090177835 | Flash Drive With Spring-Loaded Retractable Connector - A pen-type computer peripheral device includes an elongated housing containing a PCBA having a plug connector. The PCBA is secured to a positioning member that is actuated by way of a press-push button that is exposed through a slot defined in a wall of the housing. A spring-loaded mechanism includes a spring and a locking mechanism that locks the connector in a retracted position and a deployed position, and the spring biases the connector from the retracted position to the deployed position, or vice versa. | 07-09-2009 |
20090113121 | Swappable Sets of Partial-Mapping Tables in a Flash-Memory System With A Command Queue for Combining Flash Writes - A flash controller has a flash interface accessing physical blocks of multi-level-cell (MLC) flash memory. An Extended Universal-Serial-Bus (EUSB) interface loads host commands into a command queue where writes are re-ordered and combined to reduce flash writes. A partial logical-to-physical L2P mapping table in a RAM has entries for only 1 of N sets of L2P mapping tables. The other N−1 sets are stored in flash memory and fetched into the RAM when a L2P table miss occurs. The RAM required for mapping is greatly reduced. A data buffer stores one page of host write data. Sector writes are merged using the data buffer. The data buffer is flushed to flash when a different page is written, while the partial logical-to-physical mapping table is flushed to flash when a L2P table miss occurs, when the host address is to a different one of the N sets of L2P mapping tables. | 04-30-2009 |
20090100295 | RELIABLE MEMORY MODULE TESTING AND MANUFACTURING METHOD - A method of testing memory modules comprising jumping through all addressable memory blocks a first and second time is disclosed. Each jumped-to address is determined by first XORing the last two bits of the previous address, and then XORing the first result with a bit representation of the previous jump direction for a second result. The second result determines the direction of the next jump, either upwards or downwards. Each jumped-to address is XORed with its contents, and the result is written to the address. For initially empty and defect-free memory, this results in all 1 values written for the first time jumping, and all 0 values written for the second time jumping. Finally, after the second time jumping, all addressable memory values are checked, and any non-0 value addresses are identified as defective memory cells. | 04-16-2009 |
20090093136 | Single Shot Molding Method For COB USB/EUSB Devices With Contact Pad Ribs - A dual-personality extended USB (EUSB) system supports both USB and EUSB memory cards using an extended 9-pin EUSB socket. Each EUSB device 101 includes a PCBA having four standard USB metal contact pads disposed on an upper side of a PCB, and several extended purpose contact springs that extend through openings defined in the PCB. A single-shot molding process is used to form both an upper housing portion on the upper PCB surface that includes ribs extending between adjacent contact pads, and a lower molded housing portion that is formed over passive components and IC dies disposed on the lower PCB surface. The passive components are mounted using SMT methods, and the IC dies are mounted using COB methods. The extended 9-pin EUSB socket includes standard USB contacts and extended use contacts that communicate with the PCBA through the standard USB metal contacts and the contact springs. | 04-09-2009 |
20090055667 | MEMORY CARD WITH POWER SAVING - A memory system includes power saving arbitrator responsive to a clock oscillator and having a first clock rate. The power saving arbitrator includes an active enable circuit responsive to a host clock and a host command and operative to generate an active enable signal for causing the power saving arbitrator to generate a core logic/memories signal having a second clock rate that is adjustably lower in rate than the first clock rate, said active enable circuit operative to detect the absence of a host command for a predetermined period of time and when the predetermined period of time exceeds a threshold value, the power saving arbitrator operative to reduce the second clock rate. | 02-26-2009 |
20090049222 | PCI Express-Compatible Controller And Interface For Flash Memory - A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation. | 02-19-2009 |
20090037652 | Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules - A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands. | 02-05-2009 |
20080320214 | Multi-Level Controller with Smart Storage Transfer Manager for Interleaving Multiple Single-Chip Flash Memory Devices - A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device. | 12-25-2008 |
20080320209 | High Performance and Endurance Non-volatile Memory Based Storage Systems - High performance and endurance non-volatile memory (NVM) based storage systems are disclosed. According to one aspect of the present invention, a NVM based storage system comprises at least one intelligent NVM device. Each intelligent NVM device includes a control interface logic and NVM. Logical-to-physical address conversion is performed within the control interface logic, thereby eliminating the need of address conversion in a storage system level controller. In another aspect, a volatile memory buffer together with corresponding volatile memory controller and phase-locked loop circuit is included in a NVM based storage system. The volatile memory buffer is partitioned to two parts: a command queue; and one or more page buffers. The command queue is configured to hold received data transfer commands by the storage protocol interface bridge, while the page buffers are configured to hold data to be transmitted between the host computer and the at least one NVM device. | 12-25-2008 |
20080320207 | MULTI-LEVEL CELL (MLC) DUAL PERSONALITY EXTENDED FIBER OPTIC FLASH MEMORY DEVICE - A multi-level cell (MLC) dual-personality extended fiber optic flash drive includes a MLC dual-personality extended fiber optic Universal Serial Bus (USB) plug connector connected to a dual-personality extended fiber optic flash drive and being removably connectable to a host. The connector is adaptable to receive electrical data and optical data. A transceiver, located on the flash drive, is operative to convert received electrical data to optical data or to convert received optical data to electrical data. | 12-25-2008 |
20080318449 | MULTI-LEVEL CELL (MLC) DUAL PERSONALITY EXTENDED eSATA FLASH MEMORY DEVICE - A multi-level cell (MLC) dual-personality extended External Serial Advanced Technology Attachment (eSATA) flash drive includes a MLC dual-personality extended eSATA plug connector connected to a flash drive and removably connectable to a host. The connector is adaptable to receive electoral data from both a USB and eSATA interface. | 12-25-2008 |
20080298120 | Peripheral Devices Using Phase-Change Memory - Peripheral devices store data in non-volatile phase-change memory (PCM). PCM cells have alloy resistors with high-resistance amorphous states and low-resistance crystalline states. The peripheral device can be a Serial AT-Attachment (SATA) or integrated device electronics (IDE) PCM solid-state disk or a Multi-Media Card/Secure Digital (MMC/SD) card. A peripheral PCM controller accesses PCM mass storage devices containing PCM memory chips that form a mass-storage device that is block-addressable rather than randomly-addressable. SATA, IDE, or MMC/SD transactions from a host bus are read by a bus transceiver on the peripheral PCM controller. Various routines that execute on a CPU in the peripheral PCM controller are activated in response to commands in the host-bus transactions. A PCM controller in the peripheral controller transfers data from the bus transceiver to the PCM mass storage devices for storage. | 12-04-2008 |
20080286990 | Direct Package Mold Process For Single Chip SD Flash Cards - A Secure Digital device including a PCBA having passive components mounted on a PCB using surface mount technology (SMT) techniques, and active components (e.g., controller and flash memory) mounted using chip-on-board (COB) techniques. The components are mounted only on one side of the PCB, and then a molded plastic casing is formed over both sides of the PCB such that the components are encased in the plastic, and a thin plastic layer is formed over the PCB surface opposite to the components. The molded plastic casing is formed to include openings that expose metal contacts provided on the PCB, and ribs that separate the openings. In one embodiment the metal contacts are formed on the same side as the thin plastic layer, and in an alternate embodiment the metal contacts are formed on a block that is mounted on the PCB during the SMT process. | 11-20-2008 |
20080285334 | LOCAL BANK WRITE BUFFERS FOR ACCELERATING A PHASE-CHANGE MEMORY - Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data. The very long write-1 time may require wait states. To eliminate wait states for sequential accesses, the PCM cells are divided into 16 banks. Each bank has its own bank write latch that stores data locally at the bank while the bank is being written. Data lines to the banks are freed up to transfer data to other banks once the data is written into the local bank write latch, allowing the long set-current pulse to be applied locally to slowly grow crystals in the alloy resistors. External host data are buffered and applied to the data lines by an array data mux. | 11-20-2008 |
20080282128 | Method of Error Correction Code on Solid State Disk to Gain Data Security and Higher Performance - An electronic data storage device having a Reed Solomon (RS) decoder including a syndrome calculator block responsive to information including data and overhead and operative to generate a syndrome, in accordance with an embodiment of the present invention. The electronic data storage device further includes a root finder block coupled to receive said syndrome and operative to generate at least two roots, said RS decoder for processing said two roots to generate at least one error address identifying a location in said data wherein said error lies; and an erasure syndrome calculator block responsive to said information and operative to generate an erasure syndrome, said RS decoder responsive to said information identifying a disk crash, said RS decoder for processing said erasure syndrome to generate an erasure error to recover the data in said disk crash. | 11-13-2008 |
20080280490 | Press/Push Universal Serial Bus (USB) Flash Drive with Deploying and Retracting Functionalities with Elasticity Material and Fingerprint Verification Capability - Briefly, an embodiment of the present invention includes a portable flash memory drive with a simplified mechanism, based upon the resilient properties of the material used to create the parts, for reliable extension and retraction of the device's interface plug. The portable flash memory drive is comprised of a metal housing (or case), a printed circuit board (PCB) assembly, PCB support, PCB assembly end cap, an upper, and lower housing, and in some embodiments a fingerprint sensor and/or key ring assembly. The press/push switch mechanism is located on either the side of the portable flash memory device, or the top; and relies upon the resilient properties of the material used to create the metal housing or end cap, to create a smooth, locking mechanism for the extension or retraction of the interface (i.e., USB or firewire) plug. The switching/locking mechanism relies upon grooves or notches within the material of the upper and/or lower housing for tracking and locking, coupled with protrusion tabs on the sliding components of the end cap or metal housing. Alternatively, in some embodiments of the present invention, a fingerprint sensor is also extended or retracted contemporaneously with the interface plug, and allows the end user to secure and unlock the data contained, in whole or in part, therein. | 11-13-2008 |
20080278903 | Package and Manufacturing Method for Multi-Level Cell Multi-Media Card - An embodiment of the present invention includes an electronic data flash memory card (memory card) comprising a top cover (TC), a printed circuit board assembly (PCBA) and a bottom cover (BC). The TC includes a plurality of ultrasonic bonders, a plurality of breakaway tabs (tabs) and a connection device. The PCBA includes at least one memory integrated circuit (IC) and at least one controller IC. The BC includes a plurality of tabs. | 11-13-2008 |
20080278902 | Universal Serial Bus (USB) Flash Drive with Swivel Cap Functionalities with Two Locking Positions - A Universal Serial Bus (USB) flash drive includes a slim USB device having an end used to couple the USB flash drive to a host and an opposite end, and a swivel “strap shaped” metal cap having a circle cut out disposed on both cap legs. The snap coupling circle attachment allows the swivel cap to rotate substantially into a first and a second locking position and to rotate substantially 360 degrees about the z-axis of the USB device. The metal cap is generally in a locked position when the snap slot is aligned atop the snap lock tabs such that the protrusion snap ring is descended downward until the positioned flush against the snap lock groove. When unlocked the protrusion snap ring is raised up and rested upon the two snap lock tabs. | 11-13-2008 |
20080276099 | Universal Serial Bus (USB) Flash Drive Having Locking Pins and Locking Grooves for Locking Swivel Cap - In one embodiment of the present invention a Universal Serial Bus (USB) flash drive with locking swivel cap includes a USB device, a swivel cap having a top swivel cap face and a bottom swivel cap face. The swivel cap is connectably attached to the USB device, four locking pins, two of which disposed on the top swivel cap face and two of which disposed on the bottom swivel cap face, two top locking grooves disposed on a top surface of the USB device, and two bottom locking grooves disposed on a bottom surface of the USB device, wherein the locking pins disposed on top swivel cap face coupled with the two top locking grooves and the locking pins disposed on the bottom swivel cap face couple with the two bottom locking grooves allowing the swivel cap to lock in fully open (180 degrees) and fully closed (0 degree). A USB connector is connected to the USB device to couple the USB flash drive to a host device. A fingerprint sensor area is disposed on the top side of the USB device, the fingerprint sensor scans fingerprints of a user of the portable flash drive with swivel cap and optional fingerprint verification capability, and allowing access to data stored on the portable flash drive with swivel cap and optional fingerprint verification capability. | 11-06-2008 |
20080270811 | Fast Suspend-Resume of Computer Motherboard Using Phase-Change Memory - A personal computer motherboard has a main memory of phase-change-memory (PCM) chips in PCM memory modules. An operating system (OS) image is stored in the PCM memory modules and is retained during suspend since the PCM chips are non-volatile. The microprocessor can directly read the OS image retained in the PCM memory modules without copying an OS image from a hard disk to the main memory upon resume. Therefore a boot loader program in the boot ROM does not have to be fetched to the microprocessor for suspend/resume. The video memory can also be PCM, allowing the frame buffer to be retained during suspend/resume, yet be directly addressable by the microprocessor. The display is quickly activated since the frame buffer does not have to be re-constructed after suspend/resume. PCM cells use amorphous and crystalline states of a variable resistor to store data. | 10-30-2008 |
20080266991 | Synchronous Page-Mode Phase-Change Memory with ECC and RAM Cache - Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks. | 10-30-2008 |
20080266941 | 8/9 AND 8/10-BIT ENCODING TO REDUCE PEAK SURGE CURRENTS WHEN WRITING PHASE-CHANGE MEMORY - Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The memory cell's reset current can be double a set current, causing peak currents to depend on write data. When all data bits are reset to the amorphous state, a very high peak current is required. To reduce this worst-case peak current, the data is encoded before storage in the PCM cells. An 8/10 encoder adds 2 bits but ensures that no more than half of the data bits are reset. An 8/9 encoder adds an indicator bit, and inverts the 8 bits to ensure that no more than half of the bits are reset. The indicator bit indicates when the 8 bit are inverted, and when the 8 bits are uninverted. Peak currents are thus reduced by encoding to reduce reset data bits. | 10-30-2008 |
20080266816 | Light-Weight Solid State Drive With Rivet Sets - A Solid State Drive (SSD) device includes a printed circuit board assembly (PCBA) defining rivet holes, and a support structure including parallel side frame rails defining rivet openings and support platforms for receiving and supporting the PCBA. Compression-mated rivet sets are used to connect the PCBA to the support structure, each rivet set including a female rivet portion and an associated male rivet portion. The PCBA is mounted onto the support structure such that the rivet holes are aligned with the rivet openings of the plurality of rivet openings, and then the rivet sets are mounted and secured using an automatic rivet tool such that each rivet set extends through an associated rivet hole/opening and fixedly engaged such that the PCBA and the support structure are held between end caps of the respective male and female rivet portions. | 10-30-2008 |
20080261450 | PORTABLE AND RETRACTABLE FLASH DRIVE WITH OPTIONAL ROTARY DEPLOYING AND RETRACTING AND FINGERPRINT VERIFICATION CAPABILITY - In one embodiment of the present invention a portable and retractable flash drive with optional rotary deploying and retracting and fingerprint verification capability is disclosed to include a cylinder assembly. The cylinder assembly has a connector situated on one end, and a fingerprint sensor situated the surface. The portable and retractable flash drive with optional rotary deploying and retracting and fingerprint verification capability further includes a rotary tube at least partially enclosing the cylinder assembly for deploying the connector. An end tube is rotatably attached to one of the two ends of the rotary tube, and an end cap is attached to the other of the two ends of the rotary tube. The rotary tube is rotated relative to the end tube to slide the cylinder assembly back and forth inside the rotary tube to extend and retract the connector. | 10-23-2008 |
20080261449 | UNIVERSAL SERIAL BUS (USB) FLASH DRIVE HOUSING A SLIM USB DEVICE AND HAVING SWIVEL CAP FUNCTIONALITIES ALLOWING FOR TWO LOCKING POSITIONS - A Universal Serial Bus (USB) flash drive includes a slim USB device having an end used to couple the USB flash drive to a host and an opposite end and a swivel cap having a side slit that serves as an opening into which the slim USB device travels horizontally, the side slit being disposed along a lateral side of the swivel cap. The USB flash drive also includes a USB device rivet placed into the slim USB device and the swivel cap to pivotally connect them at one of the ends of the slim USB device, so that the slim USB device is pivotally extendable outwardly from the side slit in a closed or open position. The swivel rocker is pivotally extendable outwardly from the opposite end of the slim USB device and when the swivel rocker is extended outwardly, the slim USB device is caused to extend outwardly | 10-23-2008 |
20080256352 | Methods and systems of booting of an intelligent non-volatile memory microcontroller from various sources - Methods and systems of booting an intelligent non-volatile memory (NVM) microcontroller from various sources are described. According to one aspect of the present invention, a NVM microcontroller comprises multiple memory interfaces. Each of the memory interfaces may connect to one of the various sources for booting. The sources may include random access memory (RAM), read-only memory (ROM), Electrically Erasable Programmable ROM (EEPROM) (e.g., NOR flash memory, NAND flash memory). RAM may include static RAM (SRAM), dynamic RAM (DRAM), and synchronous dynamic RAM (SDRAM). Other sources include Secure Digital (SD) card and intelligent non-volatile memory devices. The NAND flash memory may include single-level cell (SLC) flash or multi-level cell (MLC) flash. SLC flash uses a single level per cell or two states per cell, while MLC flash stores four, eight or more states per cell. | 10-16-2008 |
20080256287 | Methods and systems of managing memory addresses in a large capacity multi-level cell (MLC) based flash memory device - Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM. | 10-16-2008 |
20080250195 | Multi-Operation Write Aggregator Using a Page Buffer and a Scratch Flash Block in Each of Multiple Channels of a Large Array of Flash Memory to Reduce Block Wear - A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is written to a target physical block if full, or combined with old data fragments in an Aggregating Flash Block (AFB) when the logical-sector addresses (LSA's) match. Thus small fragments are aggregated using the AFB, reducing erases and wear of flash blocks. The page buffer is copied to the AFB when a STOP command occurs. Each channel has one or more AFB's, which are tracked by an AFB tracking table. | 10-09-2008 |
20080248692 | Extended Memory Card and Manufacturing Method - An embodiment of the present invention includes an extended memory card comprising memory circuitry, extended memory controller circuitry, a plurality of first format connection fingers, and a plurality of second format connection fingers. The memory circuitry is operable to store data files therein. The extended memory controller circuitry is operable to control data file storage and retrieval to and from the memory circuitry. | 10-09-2008 |
20080235939 | Manufacturing Method For Micro-SD Flash Memory Card - A method for fabricating MicroSD devices includes forming a PCB panel having multiple PCB regions arranged in parallel rows. Passive components are attached by conventional surface mount technology (SMT) techniques. IC chips, including a MicroSD controller chip and a flash memory chip, are attached to the PCB by wire bonding or other chip-on-board (COB) technique. A molded layer is then formed over the IC chips and passive components using a mold that prevents formation of plastic on the upper surface of each PCB. The panel is then singulated using one of a laser cutting method, an abrasive water jet cutting method, and a mechanical grinding method such that the resulting PCB substrate and plastic housing have the width, height and length specified by MicroSD specifications. A front edge chamfer process is then performed. | 10-02-2008 |
20080235443 | Intelligent Solid-State Non-Volatile Memory Device (NVMD) System With Multi-Level Caching of Multiple Channels - A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security. | 09-25-2008 |
20080233798 | Multi-Level Cell (MLC) Slide Flash Memory - A portable USB device with an improved configuration is described herein. According to one embodiment, a portable USB device includes a core unit having a USB plug connector coupled to one or more multi-level cell (MLC) flash memory devices and an MLC flash controller disposed therein. The portable USB device further includes a housing for enclosing the core unit, including a front end opening to allow the USB plug connector to be deployed. The portable USB device further includes a core unit carrier for carrying the core unit for deploying and retracting the core unit, including a slide button to allow a finger of a user to slide the USB plug connector of the core unit in and out of the housing via the front end opening of the housing. | 09-25-2008 |
20080232060 | Multi-Level Cell (MLC) Rotate Flash Memory Device - A portable USB device is described herein. According to one embodiment, a portable USB device includes a core unit having a USB plug connector coupled to one or more multi-level cell (MLC) flash memory devices and an MLC flash controller disposed therein. The device further includes a housing for enclosing the core unit. The device further includes a swivel cap having a top surface and a bottom surface by bending a flat panel into a U-shape block having an opening end, a close end, and two side-openings, where the top and bottom surfaces of the swivel cap include a rivet opening align with each other. The housing having the core unit therein is sandwiched by the swivel cap using a set of rivets through the rivet openings of the housings and the swivel cap. The core unit can be rotated with respect to the rivet set in and out of the swivel cap. | 09-25-2008 |
20080228984 | Single-Chip Multi-Media Card/Secure Digital (MMC/SD) Controller Reading Power-On Boot Code from Integrated Flash Memory for User Storage - A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program. | 09-18-2008 |
20080218799 | Extended COB-USB With Dual-Personality Contacts - A dual-personality extended USB (EUSB) system supports both USB and EUSB memory cards using an extended 9-pin EUSB socket. Each EUSB memory card includes a PCBA having four standard USB metal contact pads disposed on an upper side of a PCB, and several extended purpose contact springs that extend through openings defined in the PCB. Passive components are mounted on a lower surface of the PCB using SMT methods, and IC dies are mounted using COB methods, and then the components and IC dies are covered by a plastic molded housing. The extended 9-pin EUSB socket includes standard USB contacts and extended use contacts that communicate with the PCBA through the standard USB metal contacts and the contact springs. The PCBA includes dual-personality electronics for USB and EUSB communications. | 09-11-2008 |
20080215802 | High Integration of Intelligent Non-volatile Memory Device - High integration of a non-volatile memory device (NVMD) is disclosed. According to one aspect of the present invention, a non-volatile memory device comprises an intelligent non-volatile memory (NVM) controller and an intelligent non-volatile memory module. The NVM controller includes a central processing unit (CPU) configured to handle data transfer operations to the NVM module to ensure source synchronous interface, interleaved data operations and block abstracted addressing. The intelligent NVM module includes an interface logic, a block address manager and at least one non-volatile memory array. The interface logic is configured to handle physical block management. The block address manager is configured to ensure a physical address is converted to a transformed address that is accessible to the CPU of the intelligent NVM controller. The transformed address may be an address in blocks, pages, sectors or bytes either logically or physically. | 09-04-2008 |
20080215800 | Hybrid SSD Using A Combination of SLC and MLC Flash Memory Arrays - Hybrid solid state drives (SSD) using a combination of single-level cell (SLC) and multi-level cell (MLC) flash memory arrays are described. According to one aspect of the present invention, a hybrid SSD is built using a combination SLC and MLC flash memory arrays. The SSD also includes a micro-controller to control and coordinate data transfer from a host computing device to either the SLC flash memory array of the MLC flash memory array. A memory selection indicator is determined by triaging data file based on one or more criteria, which include, but is not limited to, storing system files and user directories in the SLC flash memory array and storing user files in the MLC flash memory array; or storing more frequent access files in the SLC flash memory array, while less frequent accessed files in the MLC flash memory array. | 09-04-2008 |
20080212297 | Flash Memory Device Assembly Using Adhesive - A flash memory device includes one or two panels that are attached solely by a thermal bond adhesive to either a frame or integrated circuits (e.g., flash memory devices) disposed on a PCBA. The frame is disposed around the PCBA and supports peripheral edges of the panels. The thermal bond adhesive is either heat-activated or heat-cured, and is applied to either the memory devices, the frame or the panels, and then compressed between the panels and flash memory devices/frame using a fixture. The fixture is then passed through an oven to activate/cure the adhesive. An optional insulating layer is disposed between the panels and the ICs. An optional conforming coating layer is formed over the ICs for preventing oxidation of integrated circuit leads or soldering area, covering or protecting extreme temperature exposure either cold or hot, and waterproofing for certain military or industrial applications. | 09-04-2008 |
20080209114 | Reliability High Endurance Non-Volatile Memory Device with Zone-Based Non-Volatile Memory File System - Improved reliability high endurance non-volatile memory device with zone-based non-volatile memory file system is described. According to one aspect of the present invention, a zone-based non-volatile memory file system comprises a two-level address mapping scheme: a first level address mapping scheme maps linear or logic address received from a host computer system to a virtual zone address; and a second level address mapping scheme maps the virtual zone address to a physical zone address of a non-volatile memory module. The virtual zone address represents a number of zones each including a plurality of data sectors. Zone is configured as a unit smaller than data blocks and larger than data pages. Each of the data sector consists of 512-byte of data. The ratio between zone and the sectors is predefined by physical characteristics of the non-volatile memory module. A tracking table is used for correlating the virtual zone address with the physical zone address. Data programming and erasing are performed in a zone basis. | 08-28-2008 |
20080209112 | High Endurance Non-Volatile Memory Devices - High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM. | 08-28-2008 |
20080201622 | Non-Volatile Memory Device Manufacturing Process Testing Systems and Methods Thereof - Systems and methods of manufacturing and testing non-volatile memory (NVM) devices are described. According to one exemplary embodiment, a function test during manufacturing of the NVM modules is conducted with a system comprises a computer and a NVM tester coupling to the computer via an external bus. The NVM tester comprises a plurality of slots. Each of the slots is configured to accommodate respective one of the NVM modules to be tested. The NVM tester is configured to include an input/output interface, a microcontroller with associated RAM and ROM, a data generator, an address generator, a comparator, a comparison status storage space, a test result indicator and a NVM module detector. The data generator generates a repeatable sequence of data bits as a test vector. The known test vector is written to NVM of the NVM module under test. The known test vector is then compared with the data retrieved from the NVM module. | 08-21-2008 |
20080198545 | Open-frame solid-state drive housing with intrinsic grounding to protect exposed chips - An open-frame flash-memory drive has a printed-circuit board assembly (PCBA) with flash-memory chips, a controller chip, and a Serial AT-Attachment (SATA) connector soldered to it. The PCBA is only partially encased by left and right frames or by a U-shaped bracket frame. The frames have PCBA supports and guide posts that fit near edges of the PCBA. The frames do not cover the top and bottom of the PCBA, allowing chips on the PCBA to be ventilated by unblocked air flow. Screws that attach the PCBA to the frame have metal collars that ground the frame to the PCBA's ground plane. The screws form a current path to draw any electro-static-discharge (ESD) current off the frame and onto a PCBA ground. When the SATA connector is inserted into a host, the host ground sinks ESD currents collected by the open frame. | 08-21-2008 |