STEC, INC. Patent applications |
Patent application number | Title | Published |
20150254185 | System and Method to Cache Hypervisor Data - Systems and methods for caching data from a plurality of virtual machines are disclosed. In one particular exemplary embodiment, the systems and methods may be realized as a method for caching data from a plurality of virtual machines. The method may comprise detecting, using a computer processor executing cache management software, initiation of migration of a cached virtual machine from a first virtualization platform to a second virtualization platform, disabling caching for the virtual machine on the first virtualization platform, detecting completion of the migration of the virtual machine to the second virtualization platform, and enabling caching for the virtual machine on the second virtualization platform. | 09-10-2015 |
20140223244 | FLASH STORAGE DEVICE WITH READ DISTURB MITIGATION - A method for managing a flash storage device includes initiating a read request and reading requested data from a first storage block of a plurality of storage blocks in the flash storage device based on the read request. The method further includes incrementing a read count for the first storage block and moving the data in the first storage block to an available storage block of the plurality of storage blocks when the read count reaches a first threshold value. | 08-07-2014 |
20130318422 | READ LEVEL ADJUSTMENT USING SOFT INFORMATION - A method for calibrating read levels in a flash memory device is provided. The method includes receiving read information from flash memory in response to a read command, assigning soft information to the received read information, determining an error signal based on the assigned soft information, determining a read level offset based on the error signal, and adjusting a read level in the flash memory by the determined read level offset. | 11-28-2013 |
20130318391 | METHODS FOR MANAGING FAILURE OF A SOLID STATE DEVICE IN A CACHING STORAGE - Techniques for managing caching use of a solid state device are disclosed. In some embodiments, the techniques may be realized as a method for managing caching use of a solid state device. Management of the caching use may include receiving, at a host device, notification of failure of a solid state device. In response to the notification a cache mode may be set to uncached. In uncached mode input/output (I/O) requests may be directed to uncached storage (e.g., disk). | 11-28-2013 |
20130290612 | SOFT INFORMATION MODULE - A system and method for generating reliability information (aka “soft information”) from a flash memory device is disclosed. A plurality of memory cells are read by a data storage controller at a first read level to obtain a plurality of program values. On an error indicator being received in connection with reading the plurality of memory cells, the plurality of memory cells are read one or more times at one or more different read levels to categorize the plurality of memory cells into two or more cell program regions. A confidence value is then assigned to each memory cell based on a corresponding cell program region for the memory cell, the confidence value being representative of a likelihood that the memory cell is programmed to a corresponding program value read at the first read level. | 10-31-2013 |
20130254562 | POWER ARBITRATION FOR STORAGE DEVICES - Aspects of the subject disclosure relate to a storage device including a flash memory, a controller coupled to the flash memory, wherein the controller is configured to store data to the flash memory and a power arbiter unit coupled to the controller and to the flash memory via a plurality of flash channels, wherein the power arbiter unit is configured to receive a plurality of power requests via one or more of the plurality of flash channels and process the plurality of power requests based on a respective priority identifier associated with each of the plurality of power requests. Additionally, a computer-implemented method and power arbiter unit (PAB) are provided. | 09-26-2013 |
20130254467 | SYSTEM AND METHOD FOR SCANNING FLASH MEMORIES - A system and method for providing memory device readiness to a memory controller is disclosed. One example system includes a channel controller operably connected to a memory controller and a group of flash memory devices. The channel controller may receive, from the memory controller a request for a status of one or more memory devices in the group of flash memory devices. The channel controller may determine the status of the one or more memory devices, the status being determined while the memory controller is permitted to execute one or more other commands related to one or more other memory devices in a different group of memory devices. On determining that the one or more memory devices are in a ready status, the channel controller may provide the ready status to the memory controller. | 09-26-2013 |
20130242658 | SYSTEM AND METHOD FOR ACCESSING AND STORING INTERLEAVED DATA - A flash storage system includes a data buffer configured to receive and store a data block having data portions. The system further includes flash storage devices having storage blocks interleaved among the flash storage devices and a controller coupled to the data buffer and the flash storage devices. The controller is configured to initiate data transfers for writing the data portions of the data block asynchronously into the storage blocks, where the data transfers for writing the data portions of the data block asynchronously into the storage blocks include reading the data portions of the data block from the data buffer serially and writing the data portions of the data block into the storage blocks in parallel. | 09-19-2013 |
20130227362 | SYSTEMS AND METHODS OF USING DYNAMIC DATA FOR WEAR LEVELING IN SOLID-STATE DEVICES - Methods and systems for wear-leveling in flash storage devices are provided. A flash storage system performs wear-leveling by tracking data errors that occur when dynamic data is read from a first storage block in a first flash storage device and moving the dynamic data to a second storage block in a second flash storage device. Additionally, wear-leveling is achieved by identifying a third storage block containing static data and moves the static data to the storage block previously containing the dynamic data. | 08-29-2013 |
20130227200 | DETERMINING BIAS INFORMATION FOR OFFSETTING OPERATING VARIATIONS IN MEMORY CELLS BASED ON WORDLINE ADDRESS - Disclosed is an apparatus and method for providing memory cell bias information for use in memory operations. One or more memory die are selected from a group of memory die, and one or more memory blocks selected from the selected one or more memory die. A group of cells are programmed within the selected memory blocks, and one or more distributions of cell program levels associated with a group of wordlines are determined. A bias value for each wordline is then generated based on comparing one or more program levels in a distribution of program levels associated with the respective wordline with predetermined programming levels. The bias values are stored lookup table that is configured to be accessible at runtime by a memory controller for retrieval of the bias value during a program or read operation. | 08-29-2013 |
20130212451 | REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM - A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component. | 08-15-2013 |
20130194873 | SYSTEMS AND METHODS FOR AUTO-CALIBRATION OF A STORAGE MEMORY CONTROLLER - Systems and methods for auto-calibrating a storage memory controller are disclosed. In some embodiments, the systems and methods may be realized as a method for auto-calibrating a storage memory controller including instructing a controllable delay circuit to delay a read strobe signal at one of a plurality of delay settings, receiving data captured at a data latch using the delayed read strobe signal, selecting an adjustment factor from the plurality of delay settings using a multi-scale approach, based on an accuracy of the data captured at the data latch, and instructing the controllable delay circuit to delay the read strobe signal by the adjustment factor. | 08-01-2013 |
20130191581 | MULTI-LAYER INPUT/OUTPUT PAD RING FOR SOLID STATE DEVICE CONTROLLER - Some embodiments of the disclosed subject matter include an integrated circuit. The integrated circuit includes a solid state device controller configured to control a plurality of flash memory devices, a first set of input output IO pads, coupled to the solid state device controller, arranged as a first pad ring around a perimeter of the integrated circuit, and a second set of IO pads arranged adjacent to at least one side of the first pad ring, wherein one of the second set of IO pads includes a power source node configured to receive a power supply voltage for the solid state device controller, a ground node, and a bond pad configured to receive an external signal. | 07-25-2013 |
20130182506 | PROGRAMMING ALGORITHM FOR IMPROVED FLASH MEMORY ENDURANCE AND RETENTION - A method for programming a flash cell using a series of programming pulses, the method comprising providing a plurality of first successive programming pulses, wherein each of the first successive programming pulse is incremented by a first incremental amount and providing a plurality of second successive programming pulses, wherein each of the second successive programming pulses is incremented by a second incremental amount and wherein the second increment amount is smaller than the first incremental amount. A system and machine-readable media are also provided. | 07-18-2013 |
20130179480 | SYSTEM AND METHOD FOR OPERATING A CLUSTERED FILE SYSTEM USING A STANDALONE OPERATION LOG - Systems and methods are disclosed for operating a clustered file system using an operation log for a file system intended for standalone computers. A method for updating a file stored in a clustered file system using a file system intended for standalone computers includes receiving a command to update a file, writing the command to update the file to an operation log on a file system on a primary node, where the operation log tracks changes to one or more files, transmitting the updated operation log to a secondary node to initiate performance of the received command by the secondary node, and applying the requested changes to the file on the primary node. | 07-11-2013 |
20130176784 | ADJUSTING OPERATING PARAMETERS FOR MEMORY CELLS BASED ON WORDLINE ADDRESS AND CYCLE INFORMATION - Disclosed is an apparatus and method for adjusting operating parameters in a storage device. A controller in a solid state drive monitors current operating conditions for blocks of memory used to store data in the drive. When a block has been subjected to a predetermined number of program/erase cycles one or more stored bias values are retrieved from a storage location based on the wordline(s) associated with a current memory operation. The one or more parameters of the memory operation are then adjusted based on the one or more stored bias values, and the memory operation performed on the block of memory cells using the adjusted parameters. | 07-11-2013 |
20130166795 | SYSTEM AND METHOD FOR STREAMING DATA IN FLASH MEMORY APPLICATIONS - Systems and methods for streaming data are disclosed. In various implementations, the system comprises a hardware device and input streaming interface operably connected to the hardware device. The input streaming interface is configured to inform a data source, based on a determination that a receiving device will accept data transmitted by the hardware device, that the input streaming interface is ready to receive data, and then receive, in response to the detecting the activation of a source signal and a data initiation signal associated with the data source, source data transmitted by the data source over a data bus, and forward the source data to the hardware device. | 06-27-2013 |
20130163328 | INTER-CELL INTERFERENCE ALGORITHMS FOR SOFT DECODING OF LDPC CODES - Aspects of the subject technology relate to a method for reading information stored in a flash memory device. In some implementations, the method can include steps including, obtaining a first read signal of a first cell, wherein the first cell is located in a first word line and a first bit line in the flash memory device, obtaining a programming level of a second cell, wherein the second cell is located in a second word line and the first bit line, and wherein the second word line is adjacent to the first word line. In certain aspects, the method may further comprise steps for obtaining decoding information for the first cell based on the programming level of the second cell. A data storage system and article of manufacture are also provided. | 06-27-2013 |
20130163327 | WORD-LINE INTER-CELL INTERFERENCE DETECTOR IN FLASH SYSTEM - Aspects of the subject technology encompass a method for retrieving information stored in flash memory. In certain implementations, the method can include operations for reading a plurality of memory cells in a word line, generating a plurality of read signals based on the reading of the plurality of memory cells and identifying, from among the plurality of read signals, a first read signal associated with a first memory cell and a second read signal associated with a second memory cell, wherein the first memory cell is adjacent to the second memory cell in the word line. In certain aspects, the method can further include operations for generating an output for the first memory cell, wherein the output is based on the first and second read signals. A data storage system and article of manufacture are also provided. | 06-27-2013 |
20130159629 | METHOD AND SYSTEM FOR HASH KEY MEMORY FOOTPRINT REDUCTION - A system and method are disclosed for storing data in a hash table. The method includes receiving data, determining a location identifier for the data wherein the location identifier identifies a location in the hash table for storing the data and the location identifier is derived from the data, compressing the data by extracting the location identifier; and storing the compressed data in the identified location of the hash table. | 06-20-2013 |
20130159611 | SYSTEMS AND METHODS FOR PROVIDING LOAD ISOLATION IN A SOLID-STATE DEVICE - Systems for automatically calibrating a storage memory controller are disclosed. In some embodiments, the systems may be realized as a solid state device system with an electro-static discharge (ESD) protection capability. The system can include a memory controller electrically coupled to a channel, where the memory controller is configured to select at least one of a plurality of flash memory devices. The system can also include at least one isolation device including an ESD protection circuit, configured to electrically couple the channel to the at least one of the plurality of flash memory devices and to decouple the channel from the remaining of the plurality of flash memory devices. | 06-20-2013 |
20130145059 | DATA STORAGE SYSTEM WITH PRIMARY AND SECONDARY COMPRESSION ENGINES - Aspects of the subject technology relate to a data storage system controller including a host interface configured to be coupled to a host device, to receive data from the host device, and to send data to the host device. In certain aspects, the data storage system includes a primary compression engine configured to compress data received from the host device via the host interface, and a secondary compression engine configured to decompress and compress data associated with operations internal to the data storage system. In some implementations, the data storage systems can further include a processor configured to transfer data between the host interface and the primary compression engine, between the primary compression engine and a non-volatile storage medium, between a memory and the secondary compression engine, and between the secondary compression engine and the memory. A data storage system is also provided. | 06-06-2013 |
20130132647 | OPTIMIZED GARBAGE COLLECTION ALGORITHM TO IMPROVE SOLID STATE DRIVE RELIABILITY - A method for managing memory operations in a storage device having a plurality of data blocks, the method including steps for determining a number of invalid pages, in each of the plurality of data blocks, determining a number of page reads for each of the plurality of data blocks and determining a dwell time for each of the plurality of data blocks. In certain aspects, the method further comprises steps for selecting a data block, from among the plurality of data blocks, for memory reclamation based on the number of invalid pages, the number of page reads, and the dwell time of the selected data block. A flash storage system and computer-readable media are also provided. | 05-23-2013 |
20130124945 | DYNAMIC LDPC CODE RATE SOLUTION - The subject technology includes adjusting an error correcting code rate in a solid-state drive. A first plurality of memory operations are performed on a flash memory device of the solid-state drive using a first code rate. During operation of the drive, a controller monitors an operating condition associated with one or more memory units of the flash memory device for a trigger event. On the trigger event, the first code rate is adjusted in accordance with the operating condition to produce a second code rate, and a second plurality of memory operations is performed on the flash memory device using the second code rate. | 05-16-2013 |
20130124931 | TRANSMISSION ERROR DETECTOR FOR FLASH MEMORY CONTROLLER - In one aspect, the present disclosure provides a storage device for accounting for transmission errors to improve a usable life span of memory blocks. In some embodiments, the storage device includes: a memory array including a plurality of memory blocks; and a memory controller in communication with the memory array via an interface, wherein the memory controller is configured to detect an error event associated with data from one of the plurality of memory blocks; determine an origin of the error event; increment an error count if the origin of the error event indicates a data error in the one of the plurality of memory blocks and not if the origin of the error event indicates a transmission error; compare the error count to a threshold value; and mark the one of the plurality of memory blocks as bad when the error count exceeds the threshold value. | 05-16-2013 |
20130124792 | ERASE-SUSPEND SYSTEM AND METHOD - A method for suspending an erase operation performed on a group of memory cells in a flash memory circuit is disclosed. One example method includes initiating an erase operation on one or more memory cells, the erase operation including a plurality of erase pulses, checking for receipt of a memory command after a predetermined number of erase pulses, suspending, after the predetermined number of erase pulses, the erase operation if the memory command was received, and performing a memory operation associated with the memory command. | 05-16-2013 |
20130117625 | SYSTEM AND METHOD FOR REDUCING MEMORY IN A MULTI-CHANNEL PARALLEL ENCODER SYSTEM - A memory includes matrix data stored thereon for use by the plurality of encoders. An arbiter unit determines, for the plurality of encoders, respective times for the encoders to receive a portion of the matrix data stored in the shared memory, and facilitates providing a portion of the matrix data to the plurality of encoders according to the determined times for use in respective encoding operations. | 05-09-2013 |
20130111474 | SYSTEM AND METHOD TO CACHE HYPERVISOR DATA | 05-02-2013 |
20130111118 | SYSTEM AND METHOD FOR STORING DATA USING A FLEXIBLE DATA FORMAT | 05-02-2013 |
20130107468 | APPARATUS AND METHOD FOR STACKING INTEGRATED CIRCUITS | 05-02-2013 |
20130097433 | SYSTEMS AND METHODS FOR DYNAMIC RESOURCE MANAGEMENT IN SOLID STATE DRIVE SYSTEM - The disclosed subject matter relates to methods and systems for dynamically controlling the power consumed by solid state drive. One embodiment includes a method that measures the power consumed by the solid state drive system and configures a programmable resource manager to grant the usage/activation of flash memory devices, thereby maintaining the power consumed by the flash memory devices and, as a result, the power consumed by the whole drive, within a specified power budget. | 04-18-2013 |
20130097365 | REDUCING A NUMBER OF CLOSE OPERATIONS ON OPEN BLOCKS IN A FLASH MEMORY - The disclosed subject matter includes a memory system with a flash memory and a flash memory controller. The flash memory controller is configured to divide the flash memory into virtual segments, each segment including blocks of flash memory cells. The controller is also configured to receive a write request to a location designated by a memory identifier and to map the memory identifier to a segment. When the segment matches an open segment and an open block can store the data, the controller is configured to retrieve the open segment and the open block from a collection tracking open blocks and to write the data to the open block. When the segment is different from the open segment, the controller is configured to close the open block, to write the data to a block in the segment, and to update the collection with the block in the segment. | 04-18-2013 |
20130054880 | SYSTEMS AND METHODS FOR REDUCING A NUMBER OF CLOSE OPERATIONS IN A FLASH MEMORY - The disclosed subject matter includes a memory system with a flash memory and a flash memory controller. The flash memory has a plurality of blocks, where each block is configured to store data. The flash memory controller is configured to maintain a queue having a plurality of slots, where each of the plurality of slots is configured to maintain an identifier of an open block in the flash memory. The controller is also configured to store data to a target block in the flash memory. Furthermore, the controller is configured to remove an identifier of one of the open blocks from the queue and to add an identifier of the target block to the queue. | 02-28-2013 |
20130047052 | HIGH SPEED HARD LDPC DECODER - The subject disclosure describes a method for performing error code correction, the method comprising, loading a code word comprising a plurality of encoded bits into a memory array, initializing, into one or more of a plurality of memory units, a plurality of bits associated with each of the encoded bits, wherein the plurality of bits initialized for each of the encoded bits is based on a value of the associated encoded bit and wherein the plurality of encoded bits and the plurality of bits initialized for each of the encoded bits comprises soft information. In certain aspects, the method further comprises decoding the code word using the soft information and outputting the decoded code word from the memory array. A decoder and flash storage device are also provided. | 02-21-2013 |
20130047045 | ERROR INDICATOR FROM ECC DECODER - The subject disclosure provides a method for generating a read-level error signal, comprising, correcting a plurality of bits read from a flash memory, determining a first error rate of a first error type corrected in the bits and determining a second error rate of a second error type corrected in the bits. In certain aspects, methods of the subject technology further provides steps for comparing the first error rate with the second error rate and generating a read-level error signal based on the comparison of the first error rate and the second error rate. A decoder and flash storage device are also provided. | 02-21-2013 |
20130047044 | OPTIMAL PROGRAMMING LEVELS FOR LDPC - The subject disclosure describes a method for reducing a sector error rate in a flash memory device, the method comprising, identifying a first program verify level having a first value, selecting an adjustment value for the first program verify level and programming the adjustment value to the first program verify level to replace the first value and to shift a first programming distribution associated with the first program verify level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, wherein the shift in the first programming distribution is associated with an increase in a bit error rate. A flash storage device and computer-readable media are also provided. | 02-21-2013 |
20130031438 | MULTI-RATE LDPC DECODING - The subject technology provides a decoding solution that supports multiple choices of code rates. A decoder may be configured to receive a selected code rate from a plurality of code rates. On the selection of the code rate, the decoder may determine a circulant size based on the code rate, and, on receiving the codeword, update, during one or more parity-check operations, a number of confidence values proportional to the circulant size in each of a plurality of memory units, each number of confidence values corresponding to a portion of the codeword. | 01-31-2013 |
20130031301 | BACKEND ORGANIZATION OF STORED DATA - A data units received from a host system are divided and/or redistributed among a plurality of data payloads, wherein boundaries of the data units are not aligned with boundaries of the data payloads. The plurality of data payloads are encoded into a respective plurality of codewords, and the plurality of codewords stored in the flash memory. Boundaries of the codewords are aligned with boundaries of the pages in the flash memory. | 01-31-2013 |
20130024644 | METHODS FOR OPTIMIZING DATA MOVEMENT IN SOLID STATE DEVICES - Techniques for optimizing data movement in electronic storage devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for optimizing data movement in electronic storage devices comprising maintaining, on the electronic storage device, a data structure associating virtual memory addresses with physical memory addresses. Information can be provided regarding the data structure to a host which is in communication with the electronic storage device. Commands can be received from the host to modify the data structure on the electronic storage device, and the data structure can be modified in response to the received command. | 01-24-2013 |
20120324299 | FLASH STORAGE WEAR LEVELING DEVICE AND METHOD - A flash storage device performs wear-leveling by tracking data errors that occur when dynamic data is read from a storage block of the flash storage device and moving the dynamic data to an available storage block of the flash storage device. Additionally, the flash storage device identifies a storage block containing static data and moves the static data to the storage block previously containing the dynamic data. | 12-20-2012 |
20120324150 | SYSTEM AND METHOD OF RECOVERING DATA IN A FLASH STORAGE SYSTEM - A data storage method, comprising, receiving host data to be written to a plurality of flash storage devices, allocating the host data to one or more data units of a plurality of data units, allocating pad data to one or more data units of the plurality of data units that have not been filled with host data and generating redundant data in a redundant data unit based on the plurality of data units. In certain aspects, the method further comprises steps for writing the plurality of data units and the redundant data unit to a stripe across the plurality of flash storage devices, wherein each of the plurality of data units and the redundant data unit is written in the respective flash storage devices at a common physical address. | 12-20-2012 |
20120317406 | FLASH STORAGE SYSTEM AND METHOD FOR ACCESSING A BOOT PROGRAM - The subject technology relates to a flash storage system for accessing a boot program for a computing system, the flash storage system comprising a flash storage, a random access memory and a flash controller coupled to the flash storage and the random access memory, the flash controller configured to load the boot program from the flash storage into the random access memory. In certain aspects, the flash control is further configured to generate a ready signal indicating the boot program is accessible from the random access memory. Computing systems and methods are also provided. | 12-13-2012 |
20120297125 | SOLID-STATE DEVICE WITH LOAD ISOLATION - Systems and methods are provided for coupling multiple flash devices to a shared bus utilizing isolation switches within a SSD device. The SSD device is operable at a speed of about 400 MT/s or higher with high signal integrity. The SSD device includes a controller, a channel in electrical communication with the controller, a plurality of isolation devices in electrical communication with channel, and a plurality of flash memory devices, wherein each flash memory device is in electrical communication with the channel and controller through the one of the isolation devices. | 11-22-2012 |
20120290777 | MANAGING SECURITY IN SOLID-STATE DEVICES - A computing device and method for managing security of a memory or storage device without the need for administer privileges. To access the secure memory, a host provides a data block containing a control command and authentication data to the memory device. The memory device includes a controller for controlling access to a secure memory in the memory device. The memory device identifies the control command in the data block, authenticates the control command bused on the authentication data, and executes the control command to allow the host device to access the secure memory. | 11-15-2012 |
20120290776 | SECURE MEMORY DEVICES AND METHODS OF MANAGING SECURE MEMORY DEVICES - A computing device and method for managing security of a memory or storage device without the need for administer privileges. To access the secure memory, a host provides a data block containing a control command and authentication data to the memory device. The memory device includes a controller for controlling access to a secure memory in the memory device. The memory device identifies the control command in the data block, authenticates the control command based on the authentication data, and executes the control command to allow the host device to access the secure memory. | 11-15-2012 |
20120260009 | DATA STORAGE SYSTEM WITH COMPRESSION/DECOMPRESSION - A data storage system includes a host interface configured to be coupled to a host device, to receive data from the host device, and to send data to the host device and a memory. The data storage system further includes a primary compression engine coupled to the host interface and to the memory, wherein the primary compression engine is configured to compress data received from the host device via the host interface and to store the compressed data in the memory, and wherein the primary compression engine is further configured to decompress compressed data stored in the memory prior to the decompressed data being sent to the host device via the host interface. The data storage system further includes a secondary compression engine coupled to the memory, wherein the secondary compression engine is configured to compress data stored in the memory and to store the compressed data back in the memory, and wherein the secondary compression engine is further configured to decompress compressed data stored in the memory and to store the decompressed data back in the memory. The data storage system further includes a non-volatile storage medium and a processor configured to transfer compressed data from the memory to the non-volatile storage medium in response to a write command received from the host device and to transfer compressed data from the non-volatile storage medium to the memory in response to a read command received from the host device. | 10-11-2012 |
20120257454 | FLASH STORAGE DEVICE WITH DATA INTEGRITY PROTECTION - A flash storage device includes a power hold circuit including a double layer capacitor. A power source supplies power to the flash storage device and charges the double layer capacitor. The double layer capacitor supplies power for maintaining integrity of data during a data transfer occurring in the flash storage device when the power supplied by the power source is disrupted. Additionally, the flash storage device can inhibit subsequent data transfers until the power supplied by the power source is restored. | 10-11-2012 |
20120254515 | ERASE-SUSPEND SYSTEM AND METHOD - A method for suspending an erase operation performed on a group of memory cells in a flash memory circuit is disclosed. One example method includes providing to the memory circuit a command to erase the group of memory cells via a plurality of erase pulses. After applying an erase pulse, if it is determined that another operation has a priority higher than a predetermined threshold, the method suspends the erase operation, performs the other operation, and then resumes the erase operation. | 10-04-2012 |
20120240012 | APPARATUS AND METHOD FOR MULTI-MODE OPERATION OF A FLASH MEMORY DEVICE - Disclosed is an apparatus and method for operating a multi-level cell (MLC) flash memory circuit. Data is read from a memory block of a plurality of memory blocks in the MLC flash memory circuit, wherein each of the plurality of memory blocks can operate in one of at least three modes of operation comprising an MLC mode, a single-level cell (SLC) mode and a defective mode, and wherein the memory block is initially operating in the MLC mode. Error correction is performed on the read data to correct read errors in the read data. A determination is made if a number of bits corrected by the error correction exceeds a predetermined threshold value. If the number of bits corrected by the error correction exceeds the predetermined threshold value, the operating mode of the memory block is switched from the MLC mode to the SLC mode. | 09-20-2012 |
20120240007 | LDPC DECODING FOR SOLID STATE STORAGE DEVICES - A solid state storage device includes a flash memory and a controller configured to store data in the flash memory via a plurality of channels. The stored data is encoded using a low-density parity-check code. Hard-decision decoders are configured to decode encoded data received from the flash memory via respective channels of the plurality of channels using the low-density parity-check code and to provide decoded data to the controller in response to one or more read commands from the controller. A soft-decision decoder is configured to decode the encoded data received from the flash memory using the low-density parity-check code and to provide the decoded data to the controller in response to one of the plurality of hard-decision decoders failing to decode the encoded data. The encoded data is obtained by the soft-decision decoder using a plurality of read-retry operations. | 09-20-2012 |
20120240006 | TRELLIS-CODED MODULATION IN A MULTI-LEVEL CELL FLASH MEMORY DEVICE - A method and system for storing data in a multi-level cell (MLC) flash memory device are described. The method includes receiving data for storage in the flash memory device, the flash memory device comprising an array of MLC flash memory cells, and encoding the received data into non-binary symbols according to a trellis-coded modulation scheme. The method further includes writing each of the non-binary symbols to a respective flash memory cell set, wherein each flash memory cell set comprises a plurality of MLC flash memory cells. | 09-20-2012 |
20120239991 | APPARATUS AND METHOD FOR DETERMINING AN OPERATING CONDITION OF A MEMORY CELL BASED ON CYCLE INFORMATION - Disclosed is an apparatus and method for adjusting a memory parameter in a non-volatile memory circuit. On a trigger event, a parameter is determined in accordance with a circuit characteristic associated with the memory block. The parameter may be a new read level voltage to apply to a page of a memory block, or a program verify level voltage used to program a page of a memory block. On determining the parameter a command is sent to the memory circuit to apply the parameter to the page of the memory block. The method can be triggered by an event such as P/E cycle times and the condition is dynamically adjusted to extend the life of the memory circuit. | 09-20-2012 |
20120239990 | FLASH STORAGE DEVICE WITH READ DISTURB MITIGATION - A method for managing a flash storage device includes initiating a read request and reading requested data from a first storage block of a plurality of storage blocks in the flash storage device based on the read request. The method further includes incrementing a read count for the first storage block and moving the data in the first storage block to an available storage block of the plurality of storage blocks when the read count reaches a first threshold value. | 09-20-2012 |
20120239976 | APPARATUS AND METHOD FOR DETERMINING A READ LEVEL OF A FLASH MEMORY AFTER AN INACTIVE PERIOD OF TIME - Disclosed is an apparatus and method for determining a dwell time in a non-volatile memory circuit after a shutdown of the memory circuit. A voltage shift is calculated by comparing a first read level voltage required to read a test block stored before the shutdown and a second read level voltage required to read a second test block stored after the shutdown. A shutdown time is determined from a look up table indexed by the voltage shift and a number of program/erase cycles. The dwell time is calculated as a function of the drive temperature, a clock, and a block time stamp. Once the dwell time is calculated, a controller calculates a new read level voltage based, in part, on the dwell time and provides one or more programming commands representative of the new read level voltage to the memory circuit to read the memory circuit. | 09-20-2012 |
20120239858 | APPARATUS AND METHOD FOR DETERMINING AN OPERATING CONDITION OF A MEMORY CELL BASED ON CYCLE INFORMATION - Disclosed is an apparatus and method for determining a parameter for programming a non-volatile memory circuit. On receiving write or erase operation a parameter is determined as a function of a circuit characteristic associated with a memory block. An adjusted condition, for example, read or write time, or the standard deviation of voltage thresholds in a distribution of cells, is then determined as a function of the parameter, and a command provided to the memory circuit to use the parameter in the next write or erase operation performed on the memory block. The method can be triggered by an event such as P/E cycle times and the condition is dynamically adjusted to extend the life of the memory circuit. | 09-20-2012 |
20120239855 | SOLID-STATE STORAGE DEVICE WITH MULTI-LEVEL ADDRESSING - A solid-state storage device with multi-level addressing is provided. The solid-state storage device includes a plurality of flash memory devices, a volatile memory, and a controller. The controller is configured to store data received from a host in the plurality of flash memory devices in response to a write command and to read the data stored in the plurality of flash memory devices in response to a read command. The controller is further configured to maintain a multi-level address table that maps logical addresses received from the host identifying the data stored in the plurality of flash memory devices to physical addresses in the plurality of flash memory devices containing the data. A first level of the multi-level address table is maintained by the controller in the volatile memory and second and third levels of the multi-level address table are maintained by the controller in the plurality of flash memory devices. | 09-20-2012 |
20120239854 | FLASH STORAGE DEVICE WITH READ CACHE - A flash storage device includes a first memory, a flash memory comprising a plurality of physical blocks, each of the plurality of physical blocks comprising a plurality of physical pages, and a controller. The controller is configured to store, in the first memory, copies of data read from the flash memory, map a logical address in a read request received from a host system to a virtual unit address and a virtual page address, and check a virtual unit cache tag table stored in the first memory based on the virtual unit address. If a hit is found in the virtual unit cache tag table, a virtual page cache tag sub-table stored in the first memory is checked based on the virtual page address, wherein the virtual page cache tag sub-table is associated with the virtual unit address. If a hit is found in the virtual page cache tag sub-table, data stored in the first memory mapped to the hit in the virtual page cache tag sub-table is read in response to the read request received from the host system. | 09-20-2012 |
20120239853 | SOLID STATE DEVICE WITH ALLOCATED FLASH CACHE - A flash storage device, and methods for a flash storage device, having improved write performance are provided. Data is received from a host system, the data comprising a data segment, the data segment is temporarily stored in a data buffer of the random access memory, the data segment is assigned to a logical block address, and the data segment is written to an allocated cache portion of the flash memory. Subsequently, the data segment is written from the allocated cache portion of the flash memory to a main storage portion of the flash memory. | 09-20-2012 |
20120239852 | HIGH SPEED INPUT/OUTPUT PERFORMANCE IN SOLID STATE DEVICES - A method of transferring data in a flash storage device comprising a random access memory and a plurality of channels of a flash array is provided. The method comprises receiving a plurality of data segments from a host system, storing the plurality of data segments in the random access memory, allocating the plurality of data segments among the plurality of channels of the flash array, and writing the allocated data segments from the random access memory to the respective channels of the flash array. | 09-20-2012 |
20120239851 | PRIORITIZED ERASURE OF DATA BLOCKS IN A FLASH STORAGE DEVICE - Methods and systems for the prioritized erasure of data blocks in a flash storage device are provided. A data block in the flash storage device is selected for erasure based upon the number of valid data segments therein, thereby minimizing the number of data segments that are carried over to another data block before erasing the selected data block. The overhead of write operations in the flash storage device is therefore greatly reduced, and the overall performance thereof greatly increased. A method for managing memory operations in a flash storage device having a plurality of data blocks comprises the steps of selecting one of the plurality of data blocks for erasure based upon a number of valid data segments therein, and erasing the selected one of the plurality of data blocks. | 09-20-2012 |
20120236656 | APPARATUS AND METHOD FOR DETERMINING A READ LEVEL OF A MEMORY CELL BASED ON CYCLE INFORMATION - Disclosed is an apparatus and method for determining a read level voltage to apply to a block of memory cells in a non-volatile memory circuit. A prediction value is compared to a prediction indicator to determine whether a new read level voltage to be applied to read the memory cells should be estimated. If a new read level should be estimated the new read level is calculated as a function of an initial read level and a dwell time and a number of program/erase cycles. A controller provides one or more programming commands representative of the new read level voltage to the memory circuit to read the cells. | 09-20-2012 |
20120236651 | SYSTEM AND METHOD FOR DETERMINING DATA DEPENDENT NOISE CALCULATION FOR A FLASH CHANNEL - Disclosed is an system and method for determining a probability that a memory cell was programmed to a certain input level. An output level is received from a memory cell and a probability is determined that the output level corresponds to each of a plurality of programming levels. Each probability is determined as a function of the output level, a mean value of a distribution corresponding to the programming level, and a variance from the mean value with the variance being determined by a relative position of the output level with respect to the mean value. A probability value is generated as a function of the plurality of determined probabilities and then provided for use at a demodulator. | 09-20-2012 |
20120236643 | INTERLEAVED FLASH STORAGE SYSTEM AND METHOD - A flash storage system accesses data interleaved among flash storage devices. The flash storage system receives a data block including data portions, stores the data portions in a data buffer, and initiates data transfers for asynchronously writing the data portions into storage blocks interleaved among the flash storage devices. Additionally, the flash storage system may asynchronously read data portions of a data block interleaved among the storage blocks, store the data portions in the data buffer, and access the data portions from the data buffer. | 09-20-2012 |
20120236489 | SOLID STATE STORAGE DEVICE WITH REMOVABLE POWER BACKUP - A solid state storage device includes a printed circuit board assembly, a memory arranged on the printed circuit board assembly, and a storage medium arranged on the printed circuit board assembly. The storage device further includes a processor arranged on the printed circuit board assembly, wherein the processor is coupled to the memory and to the storage medium via the printed circuit board assembly, and wherein the processor is configured to store data in the memory and the storage medium and to read data from the memory and the storage medium. The storage device further includes a removable power pack comprising a plurality of capacitors serially arranged in a housing, wherein the plurality of capacitors is detachably connected to the printed circuit board assembly to supply backup power to the processor, the memory, and the storage medium when the removable power pack is mounted in the solid state storage device. | 09-20-2012 |
20120226851 | ISOLATION DEVICES FOR HIGH PERFORMANCE SOLID STATE DRIVES - Systems and methods are provided for coupling multiple flash devices to a shared bus utilizing isolation switches within a SSD device. The SSD device is operable at a speed of about 400 MT/s or higher with high signal integrity. The SSD device includes a controller, a channel in electrical communication with the controller, a plurality of isolation devices in electrical communication with channel, and a plurality of flash memory devices, wherein each flash memory device is in electrical communication with the channel and controller through the one of the isolation devices. | 09-06-2012 |
20120198136 | FLASH BACKED DRAM MODULE INCLUDING LOGIC FOR ISOLATING THE DRAM - A memory device for use with a primary power source including: non-volatile memory; volatile memory; an interface for connecting to a backup power source; isolation logic for controlling access to the volatile memory by a host processor, said isolation logic having a first mode during which the isolation logic provides the host processor with access to the volatile memory for storing or reading data and a second mode during which the isolation logic isolates the volatile memory from access by the host processor; and a controller controlling the isolation logic, said controller programmed to place the isolation logic in the first mode when the volatile memory is being powered by the primary power source and, when power to the volatile memory from the primary power source is interrupted, to place the isolation logic in the second mode and transfer data from the volatile memory to the non-volatile memory. | 08-02-2012 |
20120137054 | METHODS AND SYSTEMS FOR OBJECT LEVEL DE-DUPLICATION FOR SOLID STATE DEVICES - In one aspect, the present disclosure relates to a method of de-duplicating data in a solid state storage device. The method can include receiving a block of data to be written to a solid state storage device, wherein the block of data comprises header portion and a payload, wherein the header portion comprises context information; and determining whether the payload should be de-duplicated prior to storage, based on the context information stored within the header portion; if the payload is determined to be de-duplicated, de-duplicating the payload; and storing the de-duplicated payload to the solid state storage device. | 05-31-2012 |
20110029808 | SYSTEM AND METHOD OF WEAR-LEVELING IN FLASH STORAGE - A flash storage device tracks performs wear-leveling by tracking data errors that occur when dynamic data is read from a storage block of the flash storage device and moving the dynamic data to an available storage block of the flash storage device. Additionally, the flash storage device identifies a storage block containing static data and moves the static data to the storage block previously containing the dynamic data. | 02-03-2011 |
20110029717 | FLASH STORAGE DEVICE WITH FLEXIBLE DATA FORMAT - A flash storage device includes a flash storage for storing data and a controller for receiving a command containing data and selecting a sector size for the data. The controller allocates the data among data sectors having the sector size and writes the data sectors to the flash storage. In some embodiments, the controller generates system data and stores the system data in the data sectors or a system sector, or both. | 02-03-2011 |
20110029716 | SYSTEM AND METHOD OF RECOVERING DATA IN A FLASH STORAGE SYSTEM - A flash storage system includes a system controller that generates redundant data based on data stored in flash storage devices of the flash storage system. The system controller stores the redundant data in one or more of the flash storage devices. Additionally, the system controller identifies data that has become unavailable in one or more of the flash storage device, recovers the unavailable data based on the redundant data, and stores the recovered data into one or more other flash storage devices of the flash storage system. | 02-03-2011 |
20110026328 | SYSTEM AND METHOD OF MAINTAINING DATA INTEGRITY IN A FLASH STORAGE DEVICE - A flash storage device includes a power hold circuit including a double layer capacitor. A power source supplies power to the flash storage device and charges the double layer capacitor. The double layer capacitor supplies power for maintaining integrity of data during a data transfer occurring in the flash storage device when the power supplied by the power source is disrupted. Additionally, the flash storage device can inhibit subsequent data transfers until the power supplied by the power source is restored. | 02-03-2011 |
20110022829 | FLASH STORAGE SYSTEM AND METHOD FOR ACCESSING A BOOT PROGRAM - A computing system includes a flash storage device that loads a boot program from a flash storage of the flash storage device to a random access memory of the flash storage device. A processor of the computing system then accesses the boot program from the random access memory and executes the boot program. | 01-27-2011 |
20110022783 | FLASH STORAGE WITH INCREASED THROUGHPUT - A flash storage system includes a flash storage controller coupled to storage modules of a flash storage array via universal serial buses. Each storage module includes at least one flash memory device. The flash storage controller receives a programming command of a communication protocol and generates universal serial bus commands based on the programming command. The flash storage controller issues the universal serial bus commands to storage modules in the flash storage array via the universal serial buses. The storage modules process the universal serial bus commands to access data in the flash storage devices of the storage modules. | 01-27-2011 |
20110022782 | FLASH STORAGE WITH ARRAY OF ATTACHED DEVICES - A flash storage system includes a flash storage controller coupled to storage modules of a flash storage array via universal serial buses. Each storage module includes at least one flash memory device. The flash storage controller receives a programming command of a communication protocol and generates universal serial bus commands based on the programming command. The flash storage controller issues the universal serial bus commands to storage modules in the flash storage array via the universal serial buses. The storage modules process the universal serial bus commands to access data in the flash storage devices of the storage modules. | 01-27-2011 |
20110022777 | SYSTEM AND METHOD FOR DIRECT MEMORY ACCESS IN A FLASH STORAGE - A flash storage device provides direct memory access based on a first communication protocol. A host selects the first communication protocol and provides a request to the flash storage device for a direct memory access. Additionally, the host provides data blocks to the flash storage device for the direct memory access. In the first communication protocol, the host need not provide an address to the flash storage device for the direct memory access. The flash storage device stores the data blocks at sequential addresses starting at a predetermined address in the flash storage device. Another host may then select a second communication protocol and transfer the data blocks in the flash storage by using the second communication protocol. | 01-27-2011 |
20110019475 | INTERLEAVED FLASH STORAGE SYSTEM AND METHOD - A flash storage system accesses data interleaved among flash storage devices. The flash storage system receives a data block including data portions, stores the data portions in a data buffer, and initiates data transfers for asynchronously writing the data portions into storage blocks interleaved among the flash storage devices. Additionally, the flash storage system may asynchronously read data portions of a data block interleaved among the storage blocks, store the data portions in the data buffer, and access the data portions from the data buffer. | 01-27-2011 |
20100327436 | APPARATUS AND METHOD FOR STACKING INTEGRATED CIRCUITS - A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack. | 12-30-2010 |
20100205470 | FLASH BACKED DRAM MODULE WITH STATE OF HEALTH AND/OR STATUS INFORMATION ACCESSIBLE THROUGH A CONFIGURATION DATA BUS - A memory device includes: volatile memory; an interface for connecting to a backup power source; non-volatile memory; a first configuration data bus for accessing parameters describing substantially permanent characteristics of the volatile memory; a second configuration data bus for accessing at least one of state of health information of the backup power source and status information of the memory device, wherein the first configuration data bus and the second configuration data bus implement a same bus protocol; a controller programmed to detect a loss of power of a primary power source and move data from the volatile memory to the non-volatile memory, wherein configuration information of the controller is at least one of readable and writable through the first configuration data bus; and wherein at least one of the state-of-health information and the status information is at least one of readable and writable through the second configuration data bus. | 08-12-2010 |
20100205349 | SEGMENTED-MEMORY FLASH BACKED DRAM MODULE - A memory device for use with a primary power source, includes volatile memory including a plurality of memory segments defined by at least one starting addresses and a corresponding at least one ending address; an interface for connecting to a backup power source; a non-volatile memory; and a controller in communication with the volatile memory and the non-volatile memory programmed to detect a loss of power of the primary power source and in response to move data from the volatile memory to the non-volatile memory based on the at least one starting address and the at least one ending address. In some aspects, there is only one starting address and one ending address and only data that is stored in the volatile memory at addresses between the one starting address and one ending address is moved to the non-volatile memory. | 08-12-2010 |
20100205348 | FLASH BACKED DRAM MODULE STORING PARAMETER INFORMATION OF THE DRAM MODULE IN THE FLASH - A device includes volatile memory; one or more non-volatile memory chips, each of which is for storing data moved from the volatile-memory; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from a primary power source; a controller in communication with the volatile memory and the non-volatile memory, wherein: the controller is programmed to move data from the volatile memory to the non-volatile memory chips upon a loss of power of the primary power source of the volatile memory; and parameters describing the volatile memory are stored in at least one of the non-volatile memory chips that store the data moved from the volatile memory. In some aspects the parameters include serial presence detect information. | 08-12-2010 |
20100202240 | STATE OF HEALTH MONITORED FLASH BACKED DRAM MODULE - A device includes: non-volatile memory; a controller in communication with the non-volatile memory, wherein the controller is programmed to move data from a volatile memory to the non-volatile memory upon a loss of power of a primary power source of the volatile memory; and a backup power supply providing temporary power to the controller and the volatile memory upon the loss of power of the primary power source, including: a capacitor bank with an output terminal; a connection to a voltage source that charges the capacitor bank to a normal operating voltage; and a state-of-health monitor that is programmed to generate a failure signal based on a voltage at the output terminal of the capacitor bank. | 08-12-2010 |
20100202239 | STAGED-BACKUP FLASH BACKED DRAM MODULE - A memory device for use with a primary power source includes: volatile memory including a plurality of memory portions each of which has a normal operating state and a low-power state; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from the primary power source; a non-volatile memory; and a controller in communication with the volatile memory and the non-volatile memory programmed to detect a loss of power of the primary power source and in response to move data from the volatile memory to the non-volatile memory at least one memory portion at a time, and while moving data from the volatile memory to the non-volatile memory place the memory portions from which data is being moved into a normal operating state and the memory portions from which data is not being moved into a low-power state. | 08-12-2010 |
20100202238 | FLASH BACKED DRAM MODULE INCLUDING LOGIC FOR ISOLATING THE DRAM - A memory device for use with a primary power source including: non-volatile memory; volatile memory; an interface for connecting to a backup power source; isolation logic for controlling access to the volatile memory by a host processor, said isolation logic having a first mode during which the isolation logic provides the host processor with access to the volatile memory for storing or reading data and a second mode during which the isolation logic isolates the volatile memory from access by the host processor; and a controller controlling the isolation logic, said controller programmed to place the isolation logic in the first mode when the volatile memory is being powered by the primary power source and, when power to the volatile memory from the primary power source is interrupted, to place the isolation logic in the second mode and transfer data from the volatile memory to the non-volatile memory. | 08-12-2010 |
20100202237 | FLASH BACKED DRAM MODULE WITH A SELECTABLE NUMBER OF FLASH CHIPS - A memory device for use with a primary power source and a backup power source, includes: volatile memory; an interface for connecting to a backup power source; a plurality of ports, each of which is for receiving a different corresponding non-volatile memory chip; a plurality of interfaces, each of which is for communicating through a different corresponding one of the plurality of ports with any non-volatile memory connected to that port; a controller that is programmed to activate a selectable set of the plurality of interfaces depending on which ports are to receive non-volatile memory chips, wherein said controller is also programmed to react to a loss of power from the primary power source by moving data from the volatile memory through the selected interfaces to whatever non-volatile memory is connected to the selectable set of interfaces. | 08-12-2010 |
20100042901 | SUPPORTING VARIABLE SECTOR SIZES IN FLASH STORAGE DEVICES - A flash storage device comprises a plurality of data blocks, each data block comprising a plurality of data segments, a system memory, and a controller. The controller is configured to cache in the system memory a plurality of data sectors to be written, to write to a first one of the plurality of data segments a first one of the plurality of data sectors, to write to the first one of the plurality of data segments a first portion of a second one of the plurality of data sectors, and to write to a second one of the plurality of data segments a second portion of the second one of the plurality of data sectors. | 02-18-2010 |
20100023714 | PARALLEL DATA STORAGE SYSTEM - A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the host system and a buffer configured to store data sectors received from the host system via the interface. A switch is used to selectively connect the interface and the data storage devices to the buffer to facilitate the transfer of data into and out of the buffer. The data sectors are transferred by segmenting each sector into multiple smaller data cells and distributing these data cells among the data storage devices using an arbitrated distribution method. | 01-28-2010 |
20090327840 | REDUNDANT DATA DISTRIBUTION IN A FLASH STORAGE DEVICE - A flash storage device comprises a plurality of channels of flash storage, a system memory, and a controller. The controller is configured to cache, in the system memory, data to be written, to partition the data into a plurality of data portions, to generate error correction information based on the plurality of data portions, to write the error correction information to a first one or more of the plurality of channels of flash storage, and to write each of the plurality of data portions to a different one of the plurality of channels of flash storage other than the first one or more thereof. | 12-31-2009 |
20090327804 | WEAR LEVELING IN FLASH STORAGE DEVICES - A method of wear leveling in a flash storage device comprising a plurality of data blocks is provided. The method comprises the steps of detecting a data error in a read of dynamic data from a first data segment of a first data block of the plurality of data blocks, correcting the data error, and moving the dynamic data from the first data segment to a second data segment in a second one of the plurality of data blocks. | 12-31-2009 |
20090327591 | SLC-MLC COMBINATION FLASH STORAGE DEVICE - Flash memory drives and related methods are disclosed that operate to keep frequently written data, which results in frequently erased blocks, in SLC flash, and relatively static data in MLC flash. A flash drive according to the present disclosure keeps track of the number of times that data for each logical block address (LBA) has been written to the flash memory, and determines whether to store newly received data associated with a particular LBA in SLC flash or in MLC flash depending on the number of writes that have occurred for that particular LBA. For each logical block sent to the flash drive, a comparison is made of the write count of the associated LBA to a threshold. If the write count is above the threshold, the logical block is written to SLC flash. If the write count is below the threshold, the logical block is written to MLC flash. | 12-31-2009 |
20090327590 | ENHANCED MLC SOLID STATE DEVICE - Flash memory drives and related methods are disclosed that operate to keep frequently written data, which results in frequently erased blocks, in SLC-mimicking MLC flash, and relatively static data in normal MLC flash. A flash drive according to the present disclosure keeps track of the number of times that data for each logical block address (LBA) has been written to the flash memory, and determines whether to store newly received data associated with a particular LBA in SLC-mimicking MLC flash or in normal MLC flash depending on the number of writes that have occurred for that particular LBA. Dynamic allocation can occur between the two types of MLC. Related methods and software are also described. | 12-31-2009 |
20090327589 | TABLE JOURNALING IN FLASH STORAGE DEVICES - A method of table journaling in a flash storage device comprising a volatile memory and a plurality of non-volatile data blocks is provided. The method comprises the steps of creating a first copy in a first one or more of the plurality of non-volatile data blocks of an addressing table stored in the volatile memory, writing transaction log data to a second one or more of the plurality of non-volatile data blocks, and updating the first copy of the addressing table based on changes to the addressing table stored in the volatile memory after the second one or more of the plurality of non-volatile data blocks have been filled with transaction log data. | 12-31-2009 |
20090300276 | ENHANCED DATA ACCESS IN A STORAGE DEVICE - A flash storage device having improved write performance is provided. The device includes a storage block having a plurality of physical pages and a controller configured to allocate subsets of the plurality of physical pages to a plurality of logical addresses, respectively, and to write data to the plurality of physical pages. Each of the subsets of physical pages includes more than one physical page. Upon receiving a first write request for one of the logical addresses, data from the first write request is written to a first physical page of the physical pages allocated to the logical address. Upon receiving a second write request for one of the logical address, the data from the second write request is written to a second physical page allocated to the logical address and the first physical page allocated to the logical address is invalidated. | 12-03-2009 |
20090124129 | REMOVABLE STORAGE DEVICE - An adapter for removable memory cards including a housing configured to receive a memory card, a connector for connection to a host system, an interface circuit interconnecting the memory card and connector and adapted to allow communication therebetween and at least one movable cover pivotably engaged with the housing and which, in a closed position, with the housing, defines a substantially enclosed cavity configured to retain the memory card. The adapter has a generally rounded and smooth outer contour and is relatively small and light weight to provide convenient carry on the person. The adapter is made of strong materials and by fully enclosing the memory card provides a physically robust removable storage device. | 05-14-2009 |
20090046513 | Enhanced erase for flash storage device - A flash storage device includes flash storage units that are erased in response to a condition or command while allowing the flash storage device to be used subsequent to the erase. A flash controller interface receives a command for erasing the flash storage device and provides an erase command to flash controllers in the flash storage device. Alternatively, the flash storage device detects a condition in response to which the flash controller interface provides an erase command to the flash controllers. Each flash controller independently erases a flash storage unit in response to receiving the purge command such that the flash storage units are erased substantially in parallel with each other and the erase operations overlap. Subsequent to the erase, certain control data is reconstructed to allow subsequent use of the flash storage device. | 02-19-2009 |
20080288717 | SINGLE SECTOR WRITE OPERATION IN FLASH MEMORY - A flash storage device having improved write performance is provided. The device includes a storage block having a plurality of physical pages and a controller for mapping the plurality of physical pages to a plurality of logical addresses and for writing data to the plurality of physical pages. When updating data previously written to one of the plurality of logical addresses, the controller is configured to write the updated data to a second physical page which is mapped to the logical address. Each of the logical addresses may be associated with a pointer field, which is for storing a pointer value indicating the invalidity of a physical page and/or the location of another physical page. | 11-20-2008 |
20080253199 | PARALLEL DATA STORAGE SYSTEM - A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the host system and a buffer configured to store data sectors received from the host system via the interface. A switch is used to selectively connect the interface and the data storage devices to the buffer to facilitate the transfer of data into and out of the buffer. The data sectors are transferred by segmenting each sector into multiple smaller data cells and distributing these data cells among the data storage devices using an arbitrated distribution method. | 10-16-2008 |
20080250223 | FLASH MEMORY ALLOCATION FOR IMPROVED PERFORMANCE AND ENDURANCE - A flash storage device having improved write performance is provided. The device includes a storage block having a plurality of physical pages and a controller for mapping the plurality of physical pages to a plurality of logical addresses and for writing data to the plurality of physical pages. When updating data previously written to one of the plurality of logical addresses, the controller is configured to write the updated data to a second physical page which is mapped to the logical address. Each of the logical addresses may be associated with a pointer field, which is for storing a pointer value indicating the invalidity of a physical page and/or the location of another physical page. | 10-09-2008 |
20080228895 | DIRECT FILE TRANSFER HOST PROCESSOR - A computing host includes a communication processor that receives a file request from a computer network for transferring a file between the computer network and a storage device. If the file is directly transferable between the computer network and the storage device without a need for processing the file by a host processor of the computing host, the communication processor performs the file transfer. Otherwise, the host processor processes the file and performs the file transfer. | 09-18-2008 |
20080201661 | Remote flash storage management - A computing host executes a web browser to access a utility application for managing or altering one or more storage devices connected to the computing host. Management or alteration of each storage device may include various purging of the storage device, encrypting the storage device, password protecting the storage device, purging the data or the firmware of the storage device, updating firmware of the storage device, updating programmable hardware of the storage device, erasing the storage device, sanitizing the storage device, logging events occurring in the storage device, and maintaining statistics on operation of the storage device. | 08-21-2008 |
20080201520 | Flash firmware management - A computing host executes a web browser to access a utility application for managing one or more storage devices connected to the computing host. Management of each storage device may include making queries about the storage spaces and contents of the storage device, updating firmware of the storage device, updating programmable hardware of the storage device, erasing the storage device, sanitizing the storage device, logging events occurring in the storage device, and maintaining statistics on operation of the storage device. | 08-21-2008 |
20080201342 | Data storage device management system and method - A computing host executes a web browser to access a utility application for managing one or more storage devices connected to the computing host. Management of each storage device may include updating firmware of the storage device, updating programmable hardware of the storage device, erasing the storage device, sanitizing the storage device, logging events occurring in the storage device, and maintaining statistics on operation of the storage device. | 08-21-2008 |