FARADAY TECHNOLOGY CORP. Patent applications |
Patent application number | Title | Published |
20160087636 | CLOCK GENERATING APPARATUS AND FRACTIONAL FREQUENCY DIVIDER THEREOF - A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit. | 03-24-2016 |
20160077535 | VOLTAGE REGULATOR CIRCUIT - A voltage regulator circuit is provided, which includes a main regulator and at least one auxiliary regulator. The main regulator provides an output voltage and regulates the output voltage according to the output voltage and a reference voltage. Each auxiliary regulator is coupled to the main regulator. Each auxiliary regulator also provides the output voltage and regulates the output voltage according to the output voltage and the reference voltage. Each of the main regulator and the at least one auxiliary regulator provides a branch current of the same magnitude. An output current of the voltage regulator circuit includes the branch currents provided by the main regulator and the at least one auxiliary regulator. | 03-17-2016 |
20150304680 | MOTION DETECTION CIRCUIT AND METHOD - A motion detection circuit and a motion detection method are provided. The motion detection circuit includes a motion vector (MV) filtering unit and a MV decision unit. According to a relationship between a MV of a current macro-block (MB) and MVs of spatial neighboring MBs, or according to a relationship between the MV of the current MB and the MV of temporal neighboring MB, the MV filtering unit determines whether to filter the MV of the current MB for obtaining a first filtered information of the current MB. The MV decision unit receives the first filtered information, and determines whether the current MB is a motion MB according to the first filtered information. | 10-22-2015 |
20150271914 | INTEGRATED CIRCUIT - An integrated circuit (IC) is provided. The IC includes a chip/die and a package. The chip/die includes a first bonding pad, a second bonding pad, a core circuit and a resistance unit. The first bonding pad is coupled to a signal path of the core circuit. The two ends of the resistance unit are respectively coupled to the first bonding pad and the second bonding pad. The package includes a pin and a low-pass circuit. The pin is electrically connected to the first bonding pad. The low-pass circuit is electrically connected to the second bonding pad. | 09-24-2015 |
20150271459 | IMAGE SENSING APPARATUS AND COLOR-CORRECTION MATRIX CORRECTING METHOD AND LOOK-UP TABLE ESTABLISHING METHOD - An image sensing apparatus, a color-correction matrix correcting method and a look-up table establishing method are provided. The image sensing apparatus calculates a block statistics value corresponding to a block of pixels in an image sensor array. Based on a look-up table, the image sensing apparatus determines a covariance value corresponding to a current gain value. According to the covariance value and the block statistics value, the image sensing apparatus corrects a color-correction matrix corresponding to the block of pixels. The image sensing apparatus can use an amended color-correction matrix to correct the color of the pixel, so as to reduce chroma noise or other noise. | 09-24-2015 |
20150189182 | METHOD AND APPARATUS FOR REDUCING JITTERS OF VIDEO FRAMES - A method for reducing the jitters of video frames is provided, which includes the steps of dividing a frame into multiple blocks, selecting at least one block according to a variance of each block, determining a global motion vector of the frame in a direction according to the selected block(s), and performing motion compensation on the frame in the direction according to the global motion vector. | 07-02-2015 |
20150187051 | METHOD AND APPARATUS FOR ESTIMATING IMAGE NOISE - In a method for estimating image noise, plural sample blocks of an image are determined; a mean of at least one color component of each of the sample blocks and a standard deviation of at least one color component of each of the sample blocks are calculated; the sample blocks are distributed into plural segments according to the means of the sample blocks; a weighted average of the standard deviations of all of the sample blocks of each of the segments is calculated according to at least one threshold value that is determined according to the minimum standard deviation among the standard deviations of all of the sample blocks of the segment. The weighted average may be applied to noise reduction, edge detection, or motion detection of the image. | 07-02-2015 |
20150162077 | STATIC MEMORY CELL - A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data. | 06-11-2015 |
20150131766 | APPARATUS AND METHOD FOR FREQUENCY LOCKING - An apparatus and a method for frequency locking are provided. The apparatus includes a phase-locked loop (PLL), a local clock generator, a data buffer unit and a control unit. The PLL locks the phase and the frequency of a radio frequency signal to generate a recovery clock signal and received data. The data buffer unit writes the received data into an elastic buffer of the data buffer unit according to the frequency of the recovery clock signal, and reads the received data from the elastic buffer according to the frequency of a local clock signal generated by the local clock generator. The control unit obtains a write-in address and a read-out address in the elastic buffer, and sends a control signal to the local clock generator for adjusting the frequency of the local clock signal according to relationship between the write-in address and the read-out address. | 05-14-2015 |
20150010213 | IMAGE SURVEILLANCE SYSTEM AND IMAGE SURVEILLANCE METHOD - An image surveillance system and an image surveillance method are provided. The image surveillance method includes following steps. An image is captured, and at least one reference target is defined in the captured image. A monitored object in the image is identified. A distance between the monitored object and each of the at least one reference target is individually calculated. Whether to announce at least one warning is determined according to a relationship between at least one threshold and the distance. | 01-08-2015 |
20140310502 | MEMORY MANAGEMENT APPARATUS AND MEMORY MANAGEMENT METHOD THEREOF - A memory management apparatus and method thereof are disclosed. The memory management apparatus includes a micro translation look-aside buffers, a main translation look-aside buffer, a page address history table and a controller. The page address history table is used to record the space size information for a plurality of page table entry which are written to the main translation look-aside buffer. The controller decides to whether access a page table entry or not from the main translation look-aside buffer according to the page address history table. | 10-16-2014 |
20140146231 | DISPLAY APPARATUS AND IMAGE CAPTURING METHOD THEREOF - A display apparatus and an image capturing method are provided. The display apparatus includes a receiving unit, a processing unit, a display panel, a display output interface, and a capturing unit. The receiving unit is coupled to a data bus and receives video stream data provided by an external video source. The processing unit is coupled to the data bus and processes the video stream data to generate display data. The display output interface is coupled to the processing unit and the display panel, receives the display data, and drives the display panel to display an image frame. The capturing unit is coupled to the data bus and captures all or part of the image frame according to a capturing command issued by an external device, so as to obtain captured target data. The capturing unit also transmits the captured target data back to the external device. | 05-29-2014 |
20130088801 | ELECTROSTATIC DISCHARGE PROTECTION APPARATUS - An electrostatic discharge (ESD) protection apparatus includes at least one first transistor and at least one second transistor. The first transistor includes a control terminal, a first terminal, a second terminal, and a bulk. The control terminal and the second terminal of the first transistor are coupled to each other. The first terminal of the first transistor is coupled to one of a pad and a power rail line. Likewise, the second transistor also includes a control terminal, a first terminal, and a second terminal. The first terminal of the second transistor is coupled to the bulk of the first transistor, the bulk of the second transistor is coupled to the second terminal of the first transistor, and the second terminal of the second transistor is coupled to the other of the pad and the power rail line. | 04-11-2013 |
20130002320 | DELAY-LOCKED LOOP - A delay-locked loop (DLL) which receives a reference clock signal and outputs an output clock signal is provided. The DLL includes a phase detector, a delay chain, an anti-false lock (AFL) circuit, and a loop filter. The phase detector outputs a first comparison signal according to a phase comparison between the reference clock signal and the output clock signal. The delay chain generates a plurality of strobe clock signals and the output clock signal by delaying the reference clock signal for different intervals. The AFL circuit outputs a second comparison signal according to a phase comparison between the reference clock signal and the strobe clock signals. The loop filter controls the delay time of the output clock signal according to the first and the second comparison signals in order to lock the delay time of the output clock signal at a preset value. | 01-03-2013 |
20120290791 | PROCESSOR AND METHOD FOR EXECUTING LOAD OPERATION THEREOF - A processor and a method for executing load operation and store operation thereof are provided. The processor includes a data cache and a store buffer. When executing a store operation, if the address of the store operation is the same as the address of an existing entry in the store buffer, the data of the store operation is merged into the existing entry. When executing a load operation, if there is a memory dependency between an existing entry in the store buffer and the load operation, and the existing entry includes the complete data required by the load operation, the complete data is provided by the existing entry alone. If the existing entry does not include the complete data, the complete data is generated by assembling the existing entry and a corresponding entry in the data cache. | 11-15-2012 |
20120138961 | SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor package structure includes a package substrate, at least a chip, solder balls, a light emitting/receiving device, a optical intermediary device and an optical transmission device. The package substrate has a first surface, a second surface, a circuit and solder ball pads, wherein each solder ball pad is electrically connected to the circuit. The chip is disposed on the first surface and electrically connected to the circuit. The solder balls are respectively disposed on the solder ball pads. The light emitting/receiving device is disposed on the package substrate and electrically connected to the circuit. The optical intermediary device is disposed above the light emitting/receiving device. The optical transmission device is inserted in the optical intermediary device, wherein a light emitting by the light emitting/receiving device is emitted to the optical transmission device via the optical intermediary device so that an optical signal is transmitted through the optical transmission device. | 06-07-2012 |
20110231685 | HIGH SPEED INPUT/OUTPUT SYSTEM AND POWER SAVING CONTROL METHOD THEREOF - A high speed input/output (HSIO) system and a power saving control method for the HSIO system are provided. The HSIO system has a plurality of transmission speed modes. When an external device is connected to the HSIO system and an auto-configuration link is completed, the power saving control method forcibly sets an interface controller to any desired transmission speed specification in accordance with an actual transmission speed of to-be-transmitted data. Therefore, transmission speed mode of a single physical layer can be changed to achieve a low power transmission. | 09-22-2011 |
20110149449 | HIGH-VOLTAGE-TOLERANT ESD CLAMP CIRCUIT WITH LOW LEAKAGE CURRENT FABRICATED BY LOW-VOLTAGE CMOS PROCESS - An electrostatic discharge (ESD) clamp circuit is provided, which includes a plurality of identical module circuits. The anode of the first module circuit is coupled to the cathode of the ESD clamp circuit. The anode of each of the other module circuits is coupled to the cathode of the previous module circuit. The cathode of the last module circuit is coupled to the ground terminal of the ESD clamp circuit. Each module circuit includes a conduction path and a detection circuit. The detection circuit is coupled to the anode, the cathode and the conduction path of the module circuit. When the rising speed of the voltage at the anode of the module circuit surpasses a threshold value, the detection circuit makes the conduction path conducting. | 06-23-2011 |
20110129014 | MOTION DETECTING METHOD AND MOTION DETECTOR - A motion detecting method and a motion detector are provided. The motion detecting method includes the following steps. When the type of the current macro block (MB) is intra-type (I-type) or predictively-coded type (P-type), a first procedure or a second procedure is performed. The first procedure includes setting the active flag of the current | 06-02-2011 |
20100289529 | POWER-ON DETECTOR AND METHOD THEREOF - A power-on detector and a method thereof are provided. The power-on detector includes four transistors, two resistors, and a comparator. The power-on detector can detect an input voltage and then determine whether the power is turned on or not. The power-on determination is substantially immune to temperature variation. The power-on detector is noise-free and stable in various temperatures. | 11-18-2010 |
20100283507 | CURRENT SOURCE APPLICABLE TO A CONTROLLABLE DELAY LINE AND DESIGN METHOD THEREOF - A current source and a method for designing the current source are provided. The current source is designed by a recursive rule and enables controllable delay lines to provide linear delay and occupy smaller area than conventional controllable delay lines with thermometer code current sources do. | 11-11-2010 |
20100281222 | CACHE SYSTEM AND CONTROLLING METHOD THEREOF - A cache system and a method for controlling the cache system are provided. The cache system includes a plurality of caches, a buffer module, and a migration selector. Each of the caches is accessed by a corresponding processor. Each of the caches includes a plurality of cache sets and each of the cache sets includes a plurality of cache lines. The buffer module is coupled to the caches for receiving and storing data evicted due to conflict miss from a source cache line of a source cache set of a source cache among the caches. The migration selector is coupled to the caches and the buffer module. The migration selector selects, from all the cache sets, a destination cache set of a destination cache among the caches according to a predetermined condition and causing the evicted data to be sent from the buffer module to the destination cache set. | 11-04-2010 |
20100250850 | PROCESSOR AND METHOD FOR EXECUTING LOAD OPERATION AND STORE OPERATION THEREOF - A processor and a method for executing load operation and store operation thereof are provided. The processor includes a data cache and a store buffer. When executing a store operation, if the address of the store operation is the same as the address of an existing entry in the store buffer, the data of the store operation is merged into the existing entry. When executing a load operation, if there is a memory dependency between an existing entry in the store buffer and the load operation, and the existing entry includes the complete data required by the load operation, the complete data is provided by the existing entry alone. If the existing entry does not include the complete data, the complete data is generated by assembling the existing entry and a corresponding entry in the data cache. | 09-30-2010 |
20100235691 | MEMORY MODULE AND ON-LINE BUILD-IN SELF-TEST METHOD THEREOF FOR ENHANCING MEMORY SYSTEM RELIABILITY - A memory module including a plurality of memory banks, a memory control unit, and a built-in self-test (BIST) control unit is provided. The memory banks store data. The memory control unit accesses the data in accordance with a system command. The BIST control unit generates a BIST command to the memory control unit when a BIST function is enabled in the memory module. While the system command accessing the data in a specific memory bank exists, the memory command control unit has the priority to execute the system command instead of the BIST command testing the specific memory bank. Memory reliability of a system including the memory module is enhanced without reducing the system effectiveness. | 09-16-2010 |
20100161951 | PROCESSOR AND METHOD FOR RECOVERING GLOBAL HISTORY SHIFT REGISTER AND RETURN ADDRESS STACK THEREOF - A method for recovering global history shift register (GHSR) and return address stack (RAS) is provided, which is applicable to an instruction pipeline of a processor and includes the following steps. First, provide a branch recovery table (BRT) and a backup stack. Whenever a branch instruction enters a predetermined stage of the instruction pipeline, add a record in the BRT according to the branch instruction. Whenever a return address is popped from the RAS of the instruction pipeline, push the return address into the backup stack. When flushing the instruction pipeline, determine a removal range of the BRT according to the condition which triggers the pipeline flush. Recover the RAS according to the records in the removal range and the backup stack. Remove all records in the removal range. Recover the GHSR of the instruction pipeline according to the removed records. | 06-24-2010 |
20100127670 | BATTERY CHARGING SYSTEM HAVING HIGH CHARGE RATE - A charger including a regulator, a controller and a compensation-adjusting unit for accurately charging to a battery device is provided. The regulator provides a charging current to the battery device. The controller is coupled to the regulator for controlling the charging current. The compensation-adjusting unit is coupled to the regulator and the battery device for receiving a first reference voltage. In a first operation mode, the compensation-adjusting unit outputs the first reference voltage to the regulator. In a second operation mode, the controller instructs the regulator to transiently generate a first charging current and a second charging current. Responsive to the first and the second charging currents, the output voltage of the battery device presents a first output voltage and a second output voltage. The compensation-adjusting unit pre-estimates a parasitic resistance of the battery device by detecting the first and the second output voltage, thus compensating the first reference voltage. | 05-27-2010 |
20100086009 | SPREAD-SPECTRUM CLOCK GENERATOR AND SPREAD-SPECTRUM CLOCK GENERATING METHOD - A spread-spectrum clock generator (SSCG) and a spread-spectrum clock generating method are provided. The SSCG includes a first spread-spectrum module, a second spread-spectrum module, and a waveform module. The first spread-spectrum module generates a first spread-spectrum clock signal by modulating the frequency of a first input clock signal with a parallel delay configuration. The second spread-spectrum module generates a second spread-spectrum clock signal by modulating the frequency of a second input clock signal with the same parallel delay configuration. The waveform module is coupled to the first spread-spectrum module and the second spread-spectrum module for generating an output spread-spectrum clock signal according to the first and the second spread-spectrum clock signals. | 04-08-2010 |
20100082953 | RECOVERY APPARATUS FOR SOLVING BRANCH MIS-PREDICTION AND METHOD AND CENTRAL PROCESSING UNIT THEREOF - A recovery apparatus for solving a branch mis-prediction, and a method and a central processing unit (CPU) thereof are provided. The recovery apparatus includes an instruction buffer, at least one circular instruction buffer, and a decoding and pairing circuit. The decoding and pairing circuit is coupled to the instruction buffer and the circular instruction buffer. The instruction buffer stores a plurality of instructions, and the circular instruction buffer stores a recovery instruction queue corresponding to the instructions, wherein the recovery instruction queue includes a plurality of recovery instructions. The decoding and pairing circuit decodes and pairs the instructions and the recovery instructions. When the branch mis-prediction occurs, the decoding and pairing circuit outputs the recovery instructions to an instruction execution and processing circuit which is externally connected to the decoding and pairing circuit. | 04-01-2010 |
20100073045 | FREQUENCY DETECTION CIRCUIT AND DETECTION METHOD FOR CLOCK DATA RECOVERY CIRCUIT - A frequency detection circuit and a detection method thereof suitable for a clock data recovery (CDR) circuit are provided. The frequency detection circuit includes a phase detector, a first delayer, a frequency detector, and a logic circuit. The phase detector samples a data signal according to a first clock signal provided by the CDR circuit and provides a phase instruction signal according to the sampling. The first delayer delays the first clock signal to obtain a second clock signal. The frequency detector samples the data signal according to the second clock signal and provides a frequency instruction signal according to the sampling. The logic circuit generates a clock instruction signal according to the phase instruction signal and the frequency instruction signal. The CDR circuit adjusts the frequency of the first clock signal according to the status of the clock instruction signal. | 03-25-2010 |
20100052645 | REFERENCE CURRENT GENERATOR CIRCUIT FOR LOW-VOLTAGE APPLICATIONS - A reference current generator circuit suitable for low-voltage applications is provided. The generator circuit is fabricated in a chip for generating a precise reference current based on a precise reference voltage and a precise external resistor. The generator circuit provides an equivalent resistance coupled in parallel with the external resistor to provide resistance compensation and reduce the impedance of seeing into the chip from a chip pad. In addition to the resistance compensation, only moderate capacitance compensation is required to enhance the phase margin of the generator circuit, so as to achieve a stable loop. Therefore, chip area and cost can be reduced in low-voltage applications. In addition, the generator circuit reproduces the reference current generated by the external resistor by utilizing current mirrors, so as to eliminate the effect on currents caused by parallel coupling of the equivalent resistance and the external resistor. | 03-04-2010 |
20100050030 | HIGH SPEED ATPG TESTING CIRCUIT AND METHOD - The invention provides an internal comparison circuits for speeding up the ATPG test. During test, an external test machine transfers original test patterns into at least one scan chain of a chip to be tested. A bi-directional output buffer of the chip also receives the test patterns from the test machine. A comparator of the chip compares the original test patterns from the test machine via the bi-directional output buffer group with scanned-out test patterns from the scan chain, to produce a comparison signal indicating whether the chip passes or fails the test. | 02-25-2010 |
20100049947 | PROCESSOR AND EARLY-LOAD METHOD THEREOF - A processor and an early-load method thereof are provided. In the early-load method, an instruction is fetched and determined in an instruction fetch stage to obtain a determination result. Whether to early-load an early-loaded data corresponding to the instruction is determined according to the determination result. A target data is fetched according to the instruction in an instruction execution stage if the early-loaded data is not loaded correctly. The early-loaded data is served as the target data if the early-loaded data is loaded correctly. | 02-25-2010 |
20100045327 | TEST CIRCUIT AND TEST METHOD FOR POWER SWITCH - For on-chip testing an on-chip power switch coupled to a core logic and to a decoupling capacitance, after the power switch enters a test mode, the decoupling capacitance is pre-charged or discharged; the power switch is turned ON or OFF according to test patterns; and a voltage level at the decoupling capacitance is analyzed or a leakage current flowing the power switch is measured. So that, whether the power switch is passed or failed is identified. | 02-25-2010 |
20100017691 | AUDIO CODEC AND BUILT-IN SELF TEST METHOD FOR THE SAME - An audio codec and a BIST method adapted for the audio codec are provided. The BIST method includes the following steps. A first channel digital-to-analog converter (DAC) of the audio codec converts a test signal into an analog signal. A first channel analog-to-digital converter (ADC) of the audio codec converts the analog signal into a digital signal. Use a second channel DAC of the audio codec and a second channel ADC of the audio codec to calculate the magnitudes of a plurality of spectral components of the DFT of the digital signal. Determine whether the audio codec passes the test according to the magnitudes of the spectral components. | 01-21-2010 |
20090285315 | APPARATUS AND METHOD FOR ADAPTIVE CHANNEL ESTIMATION AND COHERENT BANDWIDTH ESTIMATION APPARATUS THEREOF - An apparatus and a method for adaptive channel estimation and a coherent bandwidth estimation apparatus are provided. The adaptive channel estimation apparatus includes a first channel estimator, a coherent bandwidth estimator and a second channel estimator. The first channel estimator uses a predetermined approach to calculate a first channel response of each tone of an orthogonal frequency-division multiplexing (OFDM) signal. The coherent bandwidth estimator is coupled to the first channel estimator for calculating a coherent bandwidth according to the first channel responses. The second channel estimator is coupled to the first channel estimator and the coherent bandwidth estimator. For each of the tones, the second channel estimator calculates a weighted average according to the coherent bandwidth and the first channel responses of several adjacent tones including the aforementioned tone. The second channel estimator outputs the weighted average as the second channel response of the aforementioned tone. | 11-19-2009 |
20090271133 | CLOCK JITTER MEASUREMENT CIRCUIT AND INTEGRATED CIRCUIT HAVING THE SAME - Provided is a measurement circuit for measuring a jitter of a clock signal. Delay elements delay the clock signal into delayed clock signal. Latches latch the delayed clock signals to indicate whether transition edges of the clock signal is within a window value which is corresponding to delays of the delay elements. Based on the latch result from the latches, a finite state machine generates control signals for controlling the delay elements. If the latch result indicates that the transition edges of the clock signal is not within the window value, the control signals adjust the delays of the delay elements and the window value. The jitter of the clock signal is measured based on the delays of the delay elements and the window value. | 10-29-2009 |
20090256629 | PHASE DETECTOR FOR HALF-RATE BANG-BANG CDR CIRCUIT - A phase detector, including a sampling device, a comparing device, and an output device, is provided. The sampling device samples a data signal according to a plurality of clock signals, so as to provide a plurality of corresponding sampling values. The clock signals have the same frequency and different phases. The comparing device is coupled to the sampling device, and provides a plurality of corresponding comparison values according to comparison results of each of the sampling values comparing with the next sampling value. The output device is coupled to the comparing device, and outputs two of the comparison values in response to edges of the clock signals. The two outputted comparison values serve as a first instruction signal and a second instruction signal respectively. The first and the second instruction signals are referred to in controlling the frequency and the phase of the foregoing clock signals. | 10-15-2009 |
20090251872 | POWER SUPPLY ARCHITECTURE FOR STRUCTURAL ASIC - A power supply architecture for a structural application-specific integrated circuit (ASIC) is provided. The power supply architecture includes a first conductor and a second conductor. The first conductor is coupled to a fixed voltage. The first conductor at least passes through two edges of a cell. The first conductor and the second conductor are connected through a contact. The second conductor at most passes through one edge of the cell. The structural ASIC includes a first metal layer and a second metal layer. The first metal layer includes the first conductor. The second metal layer includes the second conductor. | 10-08-2009 |
20090219056 | SIGNAL DETECTION CIRCUIT WITH DEGLITCH AND METHOD THEREOF - A signal detection circuit is used for detecting signal squelch of a differential input signal to generate a corresponding digital output signal. The signal detection circuit includes: a reference voltage generator for generating a reference voltage of which the common mode voltage tracks the common mode voltage of the input signal; a real-time signal judgment circuit, real-time rectifying and amplifying a difference between the input signal and the reference voltage; and a deglitch circuit, sampling and/or amplifying an output signal of the real-time signal judgment circuit, and transforming sampling results into the digital output signal to reflect signal squelch of the differential input signal. | 09-03-2009 |
20090185742 | METHOD FOR IMAGE COMPENSATION - In an image compensation method, formats of images are identified based on ambient color quantity information. If the image is in text format or of high contrast, over compensation is barred to avoid edge effect. A compensation coefficient is set basing on edge eigenvalue of images. The compensation value is fine tuned based on a threshold value to obtain finer compensation result. | 07-23-2009 |
20090158104 | METHOD AND APPARATUS FOR MEMORY AC TIMING MEASUREMENT - A timing measurement circuit inside a memory chip delays balanced test signals for generating delayed test signals. Each of the delayed test signals is input a corresponding input pin of a memory subsystem of the memory chip. By adjusting delay amount of the delayed test signals, AC timing parameters of the memory subsystem are tested and measured. When the timing measurement circuit is in ring oscillation, a resolution thereof is measured. | 06-18-2009 |
20090147550 | FULL DIGITAL SOFT-START CIRCUIT AND POWER SUPPLY SYSTEM USING THE SAME - A full digital soft-start circuit adapted for a power supply system is provided. The full digital soft-start circuit includes a ring oscillator, a pulse generator, a counter, and a multiplexer. The ring oscillator generates a plurality of clock signals which are different in phase, while equivalent in duty cycle and frequency. The pulse generator generates a plurality of pulse signals with different duty cycles. The counter generates a multi-bit counting signal. The multiplexer determines whether to transmit the pulse signals generated by the pulse generator so as to generate an output pulse which becomes stable as time going on. | 06-11-2009 |
20090134913 | SIGNAL COMPARISON CIRCUIT - A signal comparison circuit is provided. The signal comparison circuit includes a first amplifier, a second amplifier, a peak detector, and a comparator. The first amplifier is a zero-peaking amplifier. The first amplifier receives and amplifies a data signal. The second amplifier receives and amplifies a reference voltage. The peak detector is coupled to the first and the second amplifiers for detecting and maintaining maximum values of the amplified data signal and the amplified reference voltage, and then outputting the maintained data signal and the maintained reference voltage. The comparator is coupled to the peak detector for comparing the maintained data signal with the maintained reference voltage and outputting a result of the comparison. | 05-28-2009 |
20090125763 | PROGRAMMABLE MEMORY BUILT-IN SELF-TEST CIRCUIT AND CLOCK SWITCHING CIRCUIT THEREOF - A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip area and lower the cost by means of an instruction decoder and a built-in self-test controller. The present invention also provides some peripheral control circuits of a memory. The control circuits occupies less area and enables the memory to be tested more flexibly. The present invention further provides a clock switching circuit enabling a chip to be correctly tested under different clock speeds, which benefits to advance the testability and the analyzability of the memory embedded in a chip and thereby increase fault coverage. | 05-14-2009 |
20090122890 | OFDM DCM DEMODULATION METHOD - An OFDM DCM demodulation method is provided. The OFDM DCM demodulation method mainly includes the following steps. First, calculate a log likelihood of a first demodulation mode. Then calculate a log likelihood of a second demodulation mode. Finally, calculate a demodulation output according to the log likelihoods of the first demodulation mode and the second demodulation mode. The demodulation output may serve as an output of a demodulator of a receiving end of a DCM communication system. | 05-14-2009 |
20090110102 | SIGNAL ROUTING METHOD - A signal routing method adapted to a DWA structure is provided. The signal routing method at least includes following steps. An M-bit input digital signal is provided. The odd bit in the input digital signal is routed into a low-bit signal of an output digital signal, and the even bit in the input digital signal is routed into a high-bit signal of the output digital signal, wherein the output digital signal has M bits. | 04-30-2009 |
20090102929 | WEB CAMERA MODULE AND OPERATION METHOD THEREOF - A web camera module and an operation method thereof are provided. The web camera module includes a sensor and a back-end circuit coupled to the sensor. The sensor provides an image signal. The back-end circuit receives a firmware program from a personal computer and executes the firmware program to perform an image processing on the image signal, and then the back-end circuit provides a result of the image processing to the personal computer. | 04-23-2009 |
20090097342 | BUILT-IN SELF REPAIR CIRCUIT FOR A MULTI-PORT MEMORY AND METHOD THEREOF - A built-in self repair (BISR) circuit for a multi-port memory and a method thereof are provided. The circuit includes a test-and-analysis module (TAM) and a defect locating module (DLM) coupled to the TAM. The TAM tests a repairable multi-port memory to generate a fault location and determines whether the test generates a port-specific fault candidate according to the fault location. If a port-specific fault candidate is generated, the DLM generates a defect location based on the fault location and provides the defect location to the TAM so that the TAM can determine how to repair the repairable multi-port memory according to the defect location. If no port-specific fault candidate is generated in the test, the TAM determines how to repair the repairable multi-port memory according to the fault location. | 04-16-2009 |
20090096439 | BUILT-IN JITTER MEASUREMENT CIRCUIT - A jitter measurement circuit and a method for calibrating the jitter measurement circuit are disclosed. The jitter measurement circuit includes a synchronous dual-phase detector and a decision circuit. In a test mode, a probability distribution function (PDF) of the jitter of a clock signal output by a circuit under test is obtained. In a calibration mode, a random clock, which is externally generated or generated by a free-run oscillator in the circuit under test, is used to calibrate the synchronous dual-phase detector. The decision circuit performs logic operations, data latching and counting on a phase relationship detected by the synchronous dual-phase detector in order to obtain a counting value and a PDF relative to the jitter of the clock signal. | 04-16-2009 |
20090089548 | METHOD FOR PRELOADING DATA IN A CPU PIPELINE - A method for preloading data in a CPU pipeline is provided, which includes the following steps. When a hint instruction is executed, allocate and initiate an entry in a preload table. When a load instruction is fetched, load a piece of data from a memory into the entry according to the entry. When a use instruction which uses the data loaded by the load instruction is executed, forward the data for the use instruction from the entry instead of from the memory. When the load instruction is executed, update the entry according to the load instruction. | 04-02-2009 |
20090049333 | BUILT-IN REDUNDANCY ANALYZER AND METHOD FOR REDUNDANCY ANALYSIS - A built-in redundancy analyzer and a redundancy analysis method thereof for a chip having a plurality of repairable memories are provided. The method includes the following steps. First, the identification code of a repairable memory containing a fault (“fault memory” for short) is identified and a parameter is provided according to the identification code. The parameter includes the length of row address, the length of column address, the length of word, the number of redundancy rows, and the number of redundancy columns of the fault memory. Since the parameter of every individual repairable memory is different, the fault location is converted into a general format according to the parameter for easier processing. A redundancy analysis is then performed according to the parameter and the converted fault location, and the analysis result is converted from the general format to the format of the fault memory and output to the fault memory. | 02-19-2009 |
20090040086 | DWA STRUCTURE AND METHOD THEREOF, DIGITAL-TO-ANALOG SIGNAL CONVERSION METHOD AND SIGNAL ROUTING METHOD - A data weighted average (DWA) structure including a first delay unit, a binary to thermometer code converter, an adder, a second delay unit, a decoder, a barrel shifter, and a plurality of signal lines is provided. The first delay unit delays an input digital signal. The binary to thermometer code converter converts an output signal of the first delay unit into a thermal code. The second delay unit delays an output signal of the adder. The adder adds the input digital signal to an output signal of the second delay unit. The decoder decodes the output signal of the second delay unit. The barrel shifter generates an output signal from the thermal code in accordance with an output signal of the decoder. The signal lines route the output signal of the barrel shifter into two independent control signal groups. | 02-12-2009 |
20090037695 | DATA FETCH CIRCUIT AND METHOD THEREOF - A data fetch circuit and a method thereof are provided. A multi-phase clock signal is generated according to an input clock, and an input data is over-sampled according to the multi-phase clock signal in order to detect transition points of the input data. One of reference phases of the multi-phase clock signal is selected according to the detected transition point for fetching the input data and obtaining enough setup/hold time margin. Accordingly, appropriate data fetch points is found without complicated negative feed-back mechanism. Besides, a periodical monitoring mechanism may be further adopted for improving the accuracy of data fetch. | 02-05-2009 |
20090014801 | DECOUPLING CAPACITOR CIRCUIT AND LAYOUT FOR LEAKAGE CURRENT REDUCTION AND ESD PROTECTION IMPROVEMENT - In order to reduce the leakage current and increase the ESD protection performance, several MOS capacitors are serially connected. The E field between the gate and the source/drain of the MOS transistor is lowered and so is the gate leakage current. Besides, because the ESD voltage is distributed on the gates of the MOS capacitors, the MOS capacitors have good ESD protection performance. | 01-15-2009 |
20090010339 | IMAGE COMPENSATION CIRCUIT, METHOD THEREOF, AND LCD DEVICE USING THE SAME - Input image signals are spatially and temporally compensated. First, gray scales of a target pixel in a current frame and in a previous frame are compared to determine whether to spatially and temporally compensate the input image signals or not. Next, in accordance to weight parameters and gray scales of pixels adjacent to the target pixel, the target pixel of the current frame is spatially compensated. Further, based on the gray scale of the target pixel of the previous frame, the target pixel of the current frame after spatial compensation is temporally compensated. | 01-08-2009 |
20090010053 | COMBO MEMORY CELL - A combo memory cell comprising a SRAM cell and a mask-ROM code programmer. The SRAM cell comprises first and second inverters. The first inverter comprises a first PMOS transistor and a first NMOS transistor. Gates of the first PMOS and NMOS transistors are commonly connected to a first input node and drains thereof commonly connected to a first output node. The second inverter comprises a second PMOS transistor and a second NMOS transistor. Gates of the second PMOS and NMOS transistors are commonly connected to a second input node and drains thereof commonly connected to a second output node. The first input node and the second output node are connected, as are the second input node and the first output node. The mask-ROM code programmer is coupled to the sources of the first and second PMOS transistors or the first and second NMOS transistors. | 01-08-2009 |
20090003385 | TX EVM IMPROVEMENT OF OFDM COMMUNICATION SYSTEM - In a wireless communication method and system, a data/pilot constellation is modulated and generated based on input information bits. Channel estimation (CE) sequence in frequency-domain is off-line generated. The frequency-domain channel estimation sequence is transformed into a time-domain channel estimation sequence by ideal IFFT to avoid IFFT (Inverse Fast Fourier Transform) impact to EVM (Error Vector Magnitude) performance. Off-line resealing the time-domain CE sequence, multiplied by a rescaling coefficient, in time-domain improves EVM performance. Further, the time-domain channel estimation sequence is off-line quantized. | 01-01-2009 |
20080303499 | CONTROL CIRCUIT AND METHOD FOR MULTI-MODE BUCK-BOOST SWITCHING REGULATOR - A control circuit of a multi-mode buck-boost switching regulator and a method thereof are provided. The control circuit imposes ON/OFF timing sequences on switches according to the relationship between two controlling triangle waves and the load fluctuation. In each working cycle of each mode of the regulator, at most two switches perform switching operations. The control circuit is simple to design, which only includes simple digital elements, such as comparators, logic gates etc., instead of complicated analog circuits. | 12-11-2008 |
20080298475 | CIRCUIT AND METHOD FOR BASELINE WANDERING COMPENSATION - A circuit and a method for baseline wandering compensation for solving the problem of baseline wandering in receivers of a communication system are provided. Two paths of baseline wandering compensation are provided on the basis of a slicer error. One of the paths adjusts a direct current (DC) bias of an input signal, and the other path adjusts the determining levels of the slicer, and thus, the present invention avoids input saturation of an analog-to-digital converter, enhances the signal-to-noise ratio, and achieves a precise baseline wandering compensation. | 12-04-2008 |
20080297497 | CONTROL CIRCUIT AND METHOD OF LIQUID CRYSTAL DISPLAY PANEL - A control circuit of a liquid crystal display (LCD) panel and a method thereof are provided. The circuit includes a frame memory, a look-up table (LUT) module, and a signal processor. The frame memory provides a previous value of a pixel, and the previous value includes at least one bit of a previous frame data of the pixel. The LUT module provides a plurality of basic values according to the previous value and a current value of the pixel, and the current value includes at least one bit of a current frame data of the pixel. The signal processor produces a driving value according to the basic values and replaces the current frame data with the driving value. | 12-04-2008 |
20080297207 | DOUBLE DATA RATE TRANSMITTER AND CLOCK CONVERTER CIRCUIT THEREOF - A double data rate (DDR) transmitter and a clock converter circuit are provided. The clock converter circuit includes a first logic circuit and a second logic circuit. The first logic circuit receives a clock signal as a trigger signal, performs a sequential logic operation based on the clock signal, and outputs a result of the sequential logic operation. The second logic circuit is coupled to the first logic circuit. The second logic circuit performs a combinational logic operation based on the output of the first logic circuit and outputs a result of the combinational logic operation as a converted signal. The converted signal has the same waveform and frequency as those of the clock signal, and the phases of the clock signal and the converted signal are the same or only slightly different. | 12-04-2008 |
20080297131 | BANDGAP REFERENCE CIRCUIT - A bandgap reference circuit includes a reference current generator for respectively generating a first reference current on a first current path and a second reference current on a second current path, a current mirror for generating a third reference current on a third current path based on the first and second reference currents, an operation amplifier for rendering the first reference current substantially identical to the second reference current and a feedback circuit for rendering a node voltage on the first current path substantially identical to another node voltage on the third current path, so as to eliminate possible errors caused by a channel length modulation effect in the current mirror. | 12-04-2008 |