Texas Instruments Inc Patent applications |
Patent application number | Title | Published |
20150244363 | LINE RECEIVER CIRCUIT WITH ACTIVE TERMINATION - A circuit for receiving digital signals over a transmission line. A feedback circuit is coupled to an input node of the transmission line and adjusts the input impedance of the receiver circuit to match the characteristic impedance of the transmission line. The feedback circuit includes a first current source controlled by a first voltage and having a first transconductance, and a second current source controlled by the first voltage and having a second transconductance equal to the first transconductance times a first scaling factor. The feedback circuit includes a first resistance element having a resistance equal to the first scaling factor plus one, times the characteristic impedance of the transmission line, and is coupled between the outputs of the first and second current sources. Finally, the feedback circuit also includes a differential amplifier that compares the output of the first current source to a reference value then generates the first voltage output to control each of the first and second current sources. | 08-27-2015 |
20150030058 | CQI FEEDBACK FOR MIMO DEPLOYMENTS - The present disclosure provides a receiver, a transmitter and methods of operating a receiver and a transmitter. In one embodiment, the receiver includes a receive portion employing transmission signals from a transmitter, having multiple transmit antennas, that is capable of transmitting at least one spatial codeword and adapting a transmission rank. The receiver also includes a feedback generator portion configured to provide a channel quality indicator that is feedback to the transmitter, wherein the channel quality indicator corresponds to at least one transmission rank. | 01-29-2015 |
20130327792 | HIGH VISCOSITY RE-CIRCULATION PROBE - The present invention relates to apparatus and method for re-circulating high viscosity liquids. The apparatus comprises a recirculating probe coupled to a fluid storage and dispensing vessel by a connector, and the recirculating probe comprises: (a) a dip tube defining an output flow path; (b) an output port; (c) a recirculating port; and (d) a return flow path. The output flow path and the return flow path preferably have substantially equal cross-sectional areas, which reduce or eliminate the unbalance between the discharge pressure in the output line and that in the re-circulation line, and prevent premature wearing-out of the dispensing/recirculating pump. The output flow path and the return flow path can also be concentric to each other, which not only maximizes the effective flow area for both output and return flow paths within the limited cross-sectional area of the opening of the fluid vessel, but also avoids liquid turbulence and/or formation of air bubbles caused by free-fall drip introduction of the re-circulated liquid that is commonly observed in conventional recirculating probe designs. | 12-12-2013 |
20130088276 | DRIVER OUTPUT PAD LEAKAGE CURRENT COMPENSATION - A device includes a sense circuit configured to detect a leakage current from a driver output pad. A current mirror responds to the sense circuit and compensates for the leakage current detected at the driver output pad. A scaled compensation circuit can supply compensation current to the current mirror. | 04-11-2013 |
20130026444 | SYNTHESIZING GRAPHENE FROM METAL-CARBON SOLUTIONS USING ION IMPLANTATION - A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface. | 01-31-2013 |
20120319736 | Comparator and method with adjustable speed and power consumption - A comparator ( | 12-20-2012 |
20110317786 | System and Method for Estimating a Transmit Channel Response and/or a Feedback Channel Response Using Frequency Shifting - Systems and methods for identifying a transmission channel response and a feedback channel response from a plurality of composite system responses are disclosed. A plurality of shifted feedback signals are created by shifting a feedback signal frequency by a plurality of first offset values and/or by shifting a transmission signal frequency by a plurality of second offset values. The feedback signals are compared to an input signal to identify the transmission channel response and/or a feedback channel response. A control signal is generated for a pre-distortion circuit to modify the input signal by an inverse of the transmission channel response. The composite system response is measured at a plurality of operating frequencies and at the plurality of offset values. The measurements are stored in a matrix and singular value decomposition is applied to the matrix of measurements to calculate the transmission channel response and feedback channel response. | 12-29-2011 |
20110314310 | Low-Power Data Loop Recorder - A system and method are disclosed for capturing pre- and post-event data for random events using minimum power. Real-time data is captured and stored in a continuous loop in a segment of a first memory. Upon detection of a designated event, a second memory is powered-on and post-event data is stored to a segment of the second memory. After a designated data capture window, the second memory is powered-off and real-time data is captured in an unused segment of the first memory. The post-event data may be captured in the unused segment of the first memory and later transferred to the second memory. Auto-address logic monitors and controls the storage and retrieval of pre- and post-event in the first and second memory. An energy management system determines and controls which segments of the first and second memory should be powered-on or kept in the stasis mode to store event data. | 12-22-2011 |
20110158115 | Power Efficiency and Packet Delivery Ratio Through Micro Rate Control at Access Point Functionality Enabled Devices - Embodiments of the invention provide a method to allow a software access point (SAP)-enabled device to go to sleep as much as possible without sacrificing throughput and latency across networks. The SAP-enabled device defers transmissions from client stations if maximum end-to-end throughput that can be supported by the networks is below the maximum throughput supported by a connection to the client station. | 06-30-2011 |
20110129979 | Method of Manufacturing a Semiconductor Device Having Improved Transistor Performance - In one aspect provides a method of manufacturing a semiconductor device having improved transistor performance. In one aspect, this improvement is achieved by conducting a pre-deposition spacer deposition process wherein a temperature of a bottom region of a furnace is higher than a temperature of in the top region and is maintained for a predetermined period. The pre-deposition temperature is changed to a deposition temperature, wherein a temperature of the bottom region is lower than a temperature of the top region. | 06-02-2011 |
20110091647 | GRAPHENE SYNTHESIS BY CHEMICAL VAPOR DEPOSITION - Processes for synthesizing graphene films. Graphene films may be synthesized by heating a metal or a dielectric on a substrate to a temperature between 400° C. and 1,400° C. The metal or dielectric is exposed to an organic compound thereby growing graphene from the organic compound on the metal or dielectric. The metal or dielectric is later cooled to room temperature. As a result of the above process, standalone graphene films may be synthesized with properties equivalent to exfoliated graphene from natural graphite that is scalable to size far greater than that available on silicon carbide, single crystal silicon substrates or from natural graphite. | 04-21-2011 |
20110090725 | Systems and Methods of Synchronous Rectifier Control - Systems and methods for synchronous rectifier control are provided. A synchronous rectifier includes parasitic drain inductance and parasitic source inductance. Compensation inductance is introduced to offset the effects of parasitic inductance. Compensation inductance may be formed from the trace inductance on the semiconductor die. In certain semiconductor packages, the parasitic inductance may be substantially fixed such that the layout can be modified to generate fixed compensation inductance. | 04-21-2011 |
20100278065 | Traffic Load Estimation for Access Point Functionality Enabled Mobile Devices - Embodiments of the invention comprise a system and method for estimating a traffic load on a wireless network. An access point notifies a station that the access point will not receive transmissions during a first quiet period. After the first quiet period, the access point monitors the wireless network during a first monitoring period. If no transmissions are received during the first monitoring period, the access point notifies the station that it will not receive transmissions during a second quiet period. The second quiet period has an equal or longer duration than the first quiet period. The access point alternates between monitoring periods and quiet periods and progressively expands the duration of the quiet periods as long as no transmissions are received during the monitoring periods. If a station notifies the access point that packets are pending at the device, the monitoring period is extended to handle these packets immediately. | 11-04-2010 |
20100276783 | SELECTIVE PLASMA ETCH OF TOP ELECTRODES FOR METAL-INSULATOR-METAL (MIM) CAPACITORS - A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the bottom electrode, wherein a thickness of the dielectric layer is <1,000 A. A top electrode layer is formed on the dielectric layer. A patterned masking layer is formed on the top electrode layer. Etching using dry-etching at least in part is used to etch the top electrode layer outside the patterned masking layer to reach the dielectric layer, which removes ≦100 A of the thickness of the dielectric layer. The dry etch process includes using a first halogen comprising gas, a second halogen comprising gas that comprises fluorine, and a carrier gas. | 11-04-2010 |
20100253840 | AUTOMATIC DETECTION OF GRAPHICS FORMAT FOR VIDEO DATA - A method for automatic format detection, video decoder and video display devices therefrom. A video input having an algorithm-based first graphics format is received that carries an RGB video signal, Hsync signal and a Vsync signal. From the Hsync signal and Vsync signal, a plurality of different measured timing parameters are generated including a total number of vertical lines per frame, a total number of vertical lines per pulse width of the Vsync signal, a total number of reference clock cycles per vertical line, and measured polarity information for the Vsync and Hsync signal. An algorithm automatically generates a format detection result that represents the first graphics format using the plurality of different measured timing parameters and the measured polarity information, including a plurality of horizontal and vertical timing information for configuring a video display for the algorithm-based first graphics format. | 10-07-2010 |
20100228515 | MULTI-FRAME TEST SIGNALS MODULATED BY DIGITAL SIGNAL COMPRISING SOURCE FOR TESTING ANALOG INTEGRATED CIRCUITS - A method of generating multi-frame test signals, a testing apparatus, and method for testing integrated circuits (ICs) with the multi-frame test signals. An analog source generates an analog source signal at a constant power and a constant frequency that is modulated with a first modulating signal (e.g., I) to output a first test signal having first signal parameters including a power level, a frequency and a modulation scheme. The modulating is repeated with a second modulating signal (e.g., Q) to output a second test signal having second signal parameters including a power level, a frequency and a modulation scheme. At least one of the first and second signal parameters are different. The modulating signals are generated by a digital signal source. The first and second test signal are combined by placing the first test signal on the first frame (frame | 09-09-2010 |
20100224851 | SYNTHESIZING GRAPHENE FROM METAL-CARBON SOLUTIONS USING ION IMPLANTATION - A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface. | 09-09-2010 |
20100202354 | Frame Structure for Medium Access in Body Area Networks (BAN) - A system and method for providing a variety of medium access and power management methods are disclosed. A defined frame structure allows a hub and a node to use said methods for secured or unsecured communications with each other. Contended access is available during a random access phase. The node uses an alternate doubling of a backoff counter to reduce interference and resolve collisions with other nodes attempting to communicate with the hub in the random access phase. Non-contended access is also available, and the hub may schedule reoccurring or one-time allocation intervals for the node. The hub and the node may also establish polled and posted allocation intervals on an as needed basis. The node manages power usage by being at active mode at times during the beacon period when the node is expected to transmit or receive frames. | 08-12-2010 |
20100199095 | Password-Authenticated Association Based on Public Key Scrambling - A system and method for establishing a mutual entity authentication and a shared secret between two devices using a password without giving any useful information for finding the password is disclosed. Unique first private keys and first public keys are assigned to both devices. A shared password is provided to both devices. The public keys are scrambled using the shared password and then exchanged between the two devices. Both devices descramble their respectively received scrambled public keys using the shared password to recover the public keys. Both devices compute a shared secret from their own private keys and the recovered public keys. Both devices compute, exchange, and verify their hashes of the shared secret. If verification is successful, both devices use the shared secret to generate a shared master key, which is used either directly or via a later-generated session key for securing message communications between the two devices. | 08-05-2010 |
20100199094 | Pairwise Temporal Key Creation for Secure Networks - A system and method for establishing a pairwise temporal key (PTK) between two devices based on a shared master key and using a single message authentication codes (MAC) algorithm is disclosed. The devices use the shared master key to independently compute four MACs representing the desired PTK, a KCK, and a first and a second KMAC. The Responder sends its first KMAC to the Initiator, which retains the computed PTK only if it verifies that the received first KMAC equals its computed first KMAC and hence that the Responder indeed possesses the purportedly shared master key. The Initiator sends a third message including the second KMAC to the Responder. The Responder retains the computed PTK only if it has verified that the received second KMAC equals its computed second KMAC and hence that the Initiator indeed possesses the purportedly shared master key. | 08-05-2010 |
20100199091 | Authentication and Encryption for Secure Data Transmission - A system and method for authenticating and encrypting messages for secure transmission is disclosed. A frame to be transmitted between devices comprises a frame header and a frame body. The frame body includes a security sequence number (SSN), frame payload, and message integrity code (MIC). The SSN is incremented by one for each frame transmitted using a same pairwise temporal key (PTK). A nonce is formed using the frame header and the SSN. Counter blocks Ctr | 08-05-2010 |
20100195664 | Smart Adjustment of Backoff Counter and Contention Window for Improved Random Access - A method and system for random access control is disclosed. A backoff counter is used to determine the start time of a contended allocation for a device. The backoff counter is set to an integer randomly drawn from the interval [1, CW], where CW is a contention window value selected based upon the priority of the traffic to be transmitted. The backoff counter is decremented for each idle contention slot detected. When the backoff counter reaches zero, the device attempts to transmit in the next contention slot. If the device receives no acknowledgement or an incorrect acknowledgment, then the transmission has failed. After a failed transmission, CW is set by alternately doubling the CW value up to a CWmax value for the user priority. CW is unchanged, if it was doubled in the last setting; and CW is doubled, if it was unchanged in the last setting. | 08-05-2010 |
20100195603 | Mitigation of Interference Between Wireless Networks - A system and method for minimizing or preventing interference between wireless networks is disclosed. A network hub broadcasts a beacon signal within repeating beacon periods. The position of the beacon signal shifts within each beacon period based upon a predetermined pseudo-random sequence. The beacon signal includes data identifying the current beacon shift sequence and the current phase of the sequence. Neighboring hubs independently or jointly determine and broadcast their own beacon shift sequences and phases for their respective networks from a predetermined list. Nodes connected with the network hubs are assigned allocation intervals having a start time that is set relative to the beacon signal. The start time and duration of the allocation interval wraps around the beacon period if the allocation-interval would otherwise start or continue in a next beacon period. | 08-05-2010 |
20100195552 | Access and Power Management for Centralized Networks - A system and method for managing power in a subnet having a hub in communication with one or more nodes is disclosed. The hub and nodes communicate using one or more non-contention access methods, such as scheduled, polled or posted access. The node may enter a sleep or hibernation state while no scheduled, polled or posted allocation interval is pending. The hibernation state allows the node to hibernate through one or more entire beacon periods. In the sleep state, the node may be asleep between any scheduled, polled and posted allocation intervals for the node or during another node's scheduled allocation interval in a current beacon period. By selecting which access scheme is in use, the node and hub can increase the node's chances to be in hibernation or sleep state and minimize power consumption. | 08-05-2010 |
20100181655 | ESTABLISHING A UNIFORMLY THIN DIELECTRIC LAYER ON GRAPHENE IN A SEMICONDUCTOR DEVICE WITHOUT AFFECTING THE PROPERTIES OF GRAPHENE - A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation layer for graphene. The metal or semiconductor layer may be subjected to an oxidation process. A thin dielectric layer may then be formed on the graphene layer after the metal or semiconductor layer is oxidized. As a result of synthesizing a metal-oxide layer on graphene, which acts as a nucleation layer for the gate dielectric and buffer to graphene, a uniformly thin dielectric layer may be established on graphene without affecting the underlying characteristics of graphene. | 07-22-2010 |
20100171226 | IC HAVING TSV ARRAYS WITH REDUCED TSV INDUCED STRESS - An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV array includes a plurality of TSVs. The TSVs are positioned in rows including a plurality of interior rows and a pair of exterior rows and a plurality of columns including a plurality of interior columns and a pair of exterior columns. At least a portion of the TSVs in the array are electrically connected TSVs that are coupled to a TSV terminating metal interconnect level selected from the plurality of metal interconnect levels. At least one of the exterior rows or exterior columns include a lower number of electrically connected TSVs compared to a maximum number of electrically connected TSVs in the interior rows and interior columns, respectively. | 07-08-2010 |
20100164006 | GATE DIELECTRIC FIRST REPLACEMENT GATE PROCESSES AND INTEGRATED CIRCUITS THEREFROM - A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed. | 07-01-2010 |
20100161256 | Circuit and Method of Output Power Detection for a Converter Circuit - A circuit and method of determining the power output for a converter circuit includes determining a time averaged voltage from a rectified voltage of a winding of the transformer and multiplying the time averaged voltage by a constant determined at least in part by an average current of a winding of the transformer. By one approach, a rectified voltage from a primary side of the transformer is time averaged using a filter circuit. The current can be known or preset or controlled by the converter circuit such that the time averaged voltage reading, assuming a constant current, can be compared to a preset voltage such that the voltage reading approximates a power reading for the transformer. By another approach, the time averaged voltage is multiplied by the current to obtain a power output reading. | 06-24-2010 |
20100158166 | Noise Injection Circuit and Method for Signal Processing - A signal processing circuit is configured to calculate a gain ratio to efficiently reduce a peak to average signal ratio for an input signal by identifying signal peaks and determining the signal peak magnitudes. A window function in combination with the gain ratio is applied to a portion of the input stream having a peak signal to create a cancellation pulse to be applied to that peak signal. The cancellation pulse phase is aligned with the signal phase, thereby causing minimal phase distortion in the resultant output signal and accurate peak cancellation. The cancellation pulse can also include a finite impulse response filter portion to efficiently handle wide bandwidth signals. The hardware may be configured to process multiple signal streams in parallel to reduce hardware requirements. An algorithm can determine the effect of multiple corrections to the input stream to avoid overcorrection in the signal processing process. | 06-24-2010 |
20090291524 | COMBINED METALLIC BONDING AND MOLDING FOR ELECTRONIC ASSEMBLIES INCLUDING VOID-REDUCED UNDERFILL - A method for forming electronic assemblies includes providing a plurality of IC die each having IC bonding conductors and a workpiece having workpiece bonding conductors. A curable dielectric film is applied to the IC bonding conductors or the workpiece surface. The plurality of IC die are placed on the workpiece surface so that the plurality of IC bonding conductors are aligned to and face the plurality of workpiece bonding conductors to provide a first bonding. The placing is performed at a vacuum level corresponding to a pressure <1 kPa, and at a temperature sufficient to provide tackiness to the curable dielectric film. The plurality of IC die are then pressed to provide a second bonding. A temperature during pressing cures the curable dielectric film to provide an underfill and forms metallic joints between the plurality of IC bonding conductors and the plurality of workpiece bonding conductors. | 11-26-2009 |
20090289360 | WORKPIECE CONTACT PADS WITH ELEVATED RING FOR RESTRICTING HORIZONTAL MOVEMENT OF TERMINALS OF IC DURING PRESSING - A method of forming an electronic assembly including a plurality of IC die having bonding terminals that have a solderable material thereon and a workpiece. The workpiece includes workpiece contact pads including an elevated ring having a ring height at least 5 μm above a minimum contact pad height in an indented bonding region that is within the elevated ring. The bonding terminals and/or the plurality of workpiece contact pads include solder thereon. A plurality of IC die are mounted on the workpiece. Heat is applied so that the solder becomes tacky while remaining below its melting temperature to obtain a tacked position. The plurality of IC die are pressed using a pressing tool to heat the solder to a peak temperature that is above the melting temperature. The elevated ring resists horizontal movement of the plurality of IC die from their tacked positions during pressing. | 11-26-2009 |
20090289324 | MASK OVERHANG REDUCTION OR ELIMINATION AFTER SUBSTRATE ETCH - A method of forming IC devices includes providing a substrate and forming a patterned masking layer including at least one masked region having at least one masking layer, and a feature region bounded by the masking layer. Etching forms an etched feature in the substrate, wherein undercutting during the etching forms at least one mask overhang region over a surface portion of the etched feature that is recessed relative to an outer edge of the masking layer. A pullback etch process exclusive of any additional patterning step laterally etches the masking layer. The conditions for the pullback etch retain at least a portion of the masking layer and reduce a length of the mask overhang region by at least 50%, or eliminate the mask overhang region entirely. The etched feature is then filled after the pullback etch process to form a filled etched feature. | 11-26-2009 |
20090280740 | AUDIENCE AND SPEAKER INTERACTIVE COMMUNICATIONS SYSTEM - An audience and speaker interactive communications system is described. In one embodiment, it includes a server coupled to a loudspeaker, which server includes an application module for receiving and decoding speech samples and transmitting the speech samples to a loudspeaker over an unlicensed wireless communication frequency spectrum. The system also includes a mobile communications device with a connectivity application for gaining access to the server over an unlicensed wireless communication frequency spectrum as well as a client application module for encoding and transmitting speech samples to the server. | 11-12-2009 |
20090278245 | PACKAGED ELECTRONIC DEVICES WITH FACE-UP DIE HAVING TSV CONNECTION TO LEADS AND DIE PAD - A packaged electronic device includes a leadframe including a die pad, a first, second, and third lead pin surrounding the die pad. An IC die is assembled in a face-up configuration on the lead frame. The IC die includes a substrate having an active top surface and a bottom surface, wherein the top surface includes integrated circuitry including an input pad, an output pad, a power supply pad, and a ground pad, and a plurality of through-substrate vias (TSVs) including an electrically conductive filler material and a dielectric liner. The TSVs couple the input pad to the first lead pin, the output pad to the second lead pin, the power supply pad to a third lead pin or a portion of the die pad. A fourth TSV couples pads coupled to the ground node to the die pad or a portion of the die pad for a split die pad. | 11-12-2009 |
20090278244 | IC DEVICE HAVING LOW RESISTANCE TSV COMPRISING GROUND CONNECTION - A semiconductor device includes an integrated circuit (IC) die including a substrate, and at least one through substrate via (TSV) that extends through the substrate to a protruding integral tip that includes sidewalls and a distal end. The protruding integral tip has a tip height between 1 and 50 μm. A metal layer is on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. A semiconductor device can include an IC die that includes TSVs and a package substrate such as a lead-frame, where the IC die includes a metal layer and an electrically conductive die attach adhesive layer, such as a solder filled polymer wherein the solder is arranged in an electrically interconnected network, between the metal layer and the die pad of the lead-frame. | 11-12-2009 |
20090278238 | TSVS HAVING CHEMICALLY EXPOSED TSV TIPS FOR INTEGRATED CIRCUIT DEVICES - A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch. | 11-12-2009 |
20090256212 | LATERAL DRAIN-EXTENDED MOSFET HAVING CHANNEL ALONG SIDEWALL OF DRAIN EXTENSION DIELECTRIC - An integrated circuit ( | 10-15-2009 |
20090194801 | FERROELECTRIC CAPACITOR MANUFACTURING PROCESS - A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C. | 08-06-2009 |
20090161410 | SEVEN TRANSISTOR SRAM CELL - The present disclosure provides a seven transistor static random access memory (7T SRAM) cell. In one embodiment, the 7T SRAM cell includes a pair of cross-coupled inverters configured to provide a memory element having first and second storage nodes. The 7T SRAM cell also includes a Read isolation transistor having a control element connected to one of the storage nodes of the cross-coupled transistor inverters and configured to provide a buffered Read output. The 7T SRAM cell further includes a Read pass gate transistor controlled by a Read word line and connected between the Read isolation transistor and a read bit line. Additionally, the 7T SRAM cell still further includes a Write pass gate transistor controlled by a Write word line and connected between one of the storage nodes of the cross-coupled inverters and a Write bit line to write either state of the memory element. | 06-25-2009 |
20090057889 | Semiconductor Device Having Wafer Level Chip Scale Packaging Substrate Decoupling - One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the microchip and near the outermost surface. A first UBM contact is located on the outermost surface and between the first and second bond pads. The first UBM contact is offset from the first bond pad. A second UBM contact is located on the outermost surface and between the first and second bond pads. The second UBM contact is offset from the second bond pad, and a capacitor supported by the microchip is located between the first and second UBM contacts. | 03-05-2009 |
20080293193 | USE OF LOW TEMPERATURE ANNEAL TO PROVIDE LOW DEFECT GATE FULL SILICIDATION - Provided is a method for manufacturing a semiconductor device that includes forming a gate structure over a substrate, wherein the gate structure includes a gate dielectric and a gate electrode. The method further includes forming a metal layer over the gate electrode, and forming a fully silicided gate electrode using the metal layer. The fully silicided gate electrode may be formed by subjecting the gate electrode to a first anneal in a presence of the metal layer to form a silicided gate electrode, wherein a maximum temperature of the first anneal does not exceed about 340° C. The fully silicided gate electrode may further be formed by removing any unreacted portions of the metal layer after the first anneal, and subjecting the silicided gate electrode to a second anneal to form the fully silicided gate electrode subsequent to the removing. A maximum temperature of the second anneal exceeds about 400° C. | 11-27-2008 |
20080291185 | Method and System for Controlling Spatial Light Modulator Interface Buses - In accordance with the teachings of the present disclosure, a method and system for controlling spatial light modulator buses are provided. In accordance with one embodiment of the present disclosure, a bus controller includes a configurable bus interface having first and second modes of operation. The first mode of operation is configured to interface with a single spatial light modulator. The second mode of operation is configured to interface in parallel with a plurality of spatial light modulators. In accordance with another embodiment of the present disclosure, a method of controlling a bus includes configuring a bus interface of a bus controller to interface in parallel with a plurality of digital micromirror devices. | 11-27-2008 |
20080290427 | USE OF DOPANTS TO PROVIDE LOW DEFECT GATE FULL SILICIDATION - The invention provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming an NMOS gate structure over a substrate, wherein the NMOS gate structure includes an NMOS gate dielectric and an NMOS gate electrode. The method further includes forming n-type source/drain regions within the substrate proximate the NMOS gate structure, and forming a metal alloy layer over the NMOS gate electrode. The method additionally includes incorporating the metal alloy into the NMOS gate electrode to form an NMOS gate electrode fully silicided with the metal alloy. | 11-27-2008 |