STMicroelectronics (Rousset) SAS Patent applications |
Patent application number | Title | Published |
20160141032 | EEPROM ARCHITECTURE WHEREIN EACH BIT IS FORMED BY TWO SERIALLY CONNECTED CELLS - An integrated circuit memory includes memory cells arranged in an array with rows and columns, each column including a first bit line and a second bit line. Each memory cell is formed by: a first select transistor with a first source-drain path; a second select transistor with a second source-drain path; a first floating gate transistor with a third source-drain path; and a second floating gate transistor with a fourth source-drain path. The first, second, third and fourth source-drain paths are coupled in series between the first bit line and the second bit line. The word line for each row of the memory is coupled to the gate terminals of the first and second select transistors. The control gate line for each row in coupled to the gate terminals of the first and second floating gate transistors. | 05-19-2016 |
20160133582 | DEVICE FOR DETECTING A LASER ATTACK IN AN INTEGRATED CIRCUIT CHIP - A device for detecting a laser attack made on an integrated circuit chip comprises a bipolar transistor of a first type formed in a semiconductor substrate, that bipolar transistor comprising a parasitic bipolar transistor of a second type. A buried region, forming the base of the parasitic bipolar transistor, operates as a detector of the variations in current flowing caused by impingement of laser light on the substrate. | 05-12-2016 |
20160093696 | INTEGRATED CIRCUIT COMPRISING COMPONENTS, FOR EXAMPLE NMOS TRANSISTORS, HAVING ACTIVE REGIONS WITH RELAXED COMPRESSIVE STRESSES - An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate. | 03-31-2016 |
20160064339 | METHOD FOR FABRICATION OF AN INTEGRATED CIRCUIT RENDERING A REVERSE ENGINEERING OF THE INTEGRATED CIRCUIT MORE DIFFICULT AND CORRESPONDING INTEGRATED CIRCUIT - An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks. | 03-03-2016 |
20150340426 | COMPONENT, FOR EXAMPLE NMOS TRANSISTOR, WITH AN ACTIVE REGION UNDER RELAXED COMPRESSIVE STRESS, AND ASSOCIATED DECOUPLING CAPACITOR - An integrated circuit includes a substrate and a circuit component (such as a MOS device or resistance) disposed at least partially within an active region of the substrate limited by an insulating region. A capacitive structure including a first electrode (for connection to a first potential such as ground) and a second electrode (for connection to a second potential such as a supply voltage) is provided in connection with the insulating region. One of the first and second electrodes is situated at least in part within the insulating region. The capacitive structure is thus configured in order to allow a reduction in compressive stresses within the active region. | 11-26-2015 |
20150262941 | PERFORATED ELECTRONIC PACKAGE AND METHOD OF FABRICATION - An electronic package includes an integrated circuit chip mounted to a support plate and encapsulated by an encapsulating body. The package includes at least one weakening deep perforation. The perforation is formed in either the support plate or the encapsulating body, and functions to reduce a resistance of the package to bending stresses perpendicular to the support plate. | 09-17-2015 |
20150255540 | COMPONENT, FOR EXAMPLE NMOS TRANSISTOR, WITH ACTIVE REGION WITH RELAXED COMPRESSION STRESSES, AND FABRICATION METHOD - An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by a trench insulating region. The transistor, active region and trench insulating region are covered by an additional insulating region. A metal contact extends through the additional insulating region to make contact with the trench insulating region. The metal contact may penetrate into the trench insulating region. | 09-10-2015 |
20150249132 | INTEGRATED CIRCUIT COMPRISING COMPONENTS, FOR EXAMPLE NMOS TRANSISTORS, HAVING ACTIVE REGIONS WITH RELAXED COMPRESSIVE STRESSES - An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate. | 09-03-2015 |
20150137953 | POWER MANAGEMENT IN AN ELECTROMAGNETIC TRANSPONDER - An electromagnetic transponder includes an oscillatory circuit, a battery and a first rectifier bridge. Alternating current input terminals of the rectifier bridge are connected to the terminals of the oscillatory circuit, and at least two rectifier elements of the rectifier bridge are controllable on the basis of the voltage supplied by the battery. | 05-21-2015 |
20150048459 | DEVICE FOR DETECTING A LASER ATTACK IN AN INTEGRATED CIRCUIT CHIP - A device for detecting a laser attack made on an integrated circuit chip comprises a bipolar transistor of a first type formed in a semiconductor substrate, that bipolar transistor comprising a parasitic bipolar transistor of a second type. A buried region, forming the base of the parasitic bipolar transistor, operates as a detector of the variations in current flowing caused by impingement of laser light on the substrate. | 02-19-2015 |
20150046627 | COMMUNICATION ON AN I2C BUS - A communication system includes an I2C bus interconnecting at least one first device and one second device. At least one direct data link, other than the I2C bus, interconnects the first and second devices. The system is configurable to operate in: a first operating mode providing for data only transmission between the first and second devices over the I2C bus; and a second operating mode providing for simultaneous data transmission between the first and second devices over both the I2C bus and said data link. | 02-12-2015 |
20150043269 | ELECTRIC CHARGE FLOW CIRCUIT FOR A TIME MEASUREMENT - A charge flow circuit for a time measurement, including a plurality of elementary capacitive elements electrically in series, each elementary capacitive element leaking through its dielectric space. | 02-12-2015 |
20150037966 | METHOD FOR PRODUCING A PATTERN IN AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT - At least one projecting block is formed in an element. The projecting block is then covered with a first cover layer so as to form a concave ridge self-aligned with the projecting block and having its concavity face towards the projecting block. A first trench is then formed in the ridge in a manner that is self-aligned with both the ridge and the projecting block. The first trench extends to a depth which reaches the projecting block. The projecting block is etched using the ridge and first trench as an etching mask to form a second trench in the projecting block that is self-aligned with the first trench. A pattern is thus produced by the second trench and unetched parts of the projecting block which delimit the second trench. | 02-05-2015 |
20140372327 | MECHANISM FOR VERIFYING THE AUTHENTICITY OF A PRODUCT - The authenticity of a product associated with a host device is verified through a process. The product contains, in segments of a non-volatile memory, several different functions stored in ciphered fashion. The process involves, in a first phase, the sending by the host device of a control signal for executing a function, with the product functioning to decipher the function and store the unciphered function in the non-volatile memory. The process further involves, in a second phase, the sending by the host device of a control signal for causing execution of the deciphered function, with the product functioning to execute the function and send a result of this execution back to the host device. The host device evaluates the received result to verify product authenticity. | 12-18-2014 |
20140367784 | COMPONENT, FOR EXAMPLE NMOS TRANSISTOR, WITH ACTIVE REGION WITH RELAXED COMPRESSION STRESSES, AND FABRICATION METHOD - An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by an insulating region. The insulating region is formed to includes at least one area in which the insulating region has two insulating extents that are mutually separated from each other by a separation region formed by a part of the substrate. | 12-18-2014 |
20140367465 | METHOD FOR VERIFYING THE AUTHENTICITY OF A PRODUCT - In order to verify the authenticity of a product associated with a host device, the product contains, in segments of a non-volatile memory, several different functions stored in ciphered fashion. The host device sends a control signal for selecting and activating one of those ciphered functions. The product then deciphers and executes the function. The result of the function execution is then communicated back to host device when a decision on product authenticity is made. | 12-18-2014 |
20140362640 | METHOD FOR BLOCK-ERASING A PAGE-ERASABLE EEPROM-TYPE MEMORY - A method for erasing a page-erasable EEPROM-type memory includes: the memory receiving a command associated with a set of addresses of pages of the memory to be erased, each page comprising several memory cell groups each forming a word, for each address of the set of addresses, selecting a word line corresponding to a page of the memory, and triggering the simultaneous erasing of all the selected word lines. | 12-11-2014 |
20140360851 | Electrically Controllable Integrated Switch - An integrated circuit includes an interconnection part with several metallization levels. An electrically activatable switching device within the interconnection part has an assembly that includes a beam held by a structure. The beam and structure are located within the same metallization level. Locations of fixing of the structure on the beam are arranged so as to define for the beam a pivot point situated between these fixing locations. The structure is substantially symmetric with respect to the beam and to a plane perpendicular to the beam in the absence of a potential difference. The beam is able to pivot in a first direction in the presence of a first potential difference applied between a first part of the structure and to pivot in a second direction in the presence of a second potential difference applied between a second part of the structure. | 12-11-2014 |
20140355357 | METHOD FOR WRITING IN AN EEPROM-TYPE MEMORY INCLUDING A MEMORY CELL REFRESH - The present disclosure relates to a method for writing in an EEPROM memory, the method comprising steps of: storing the bits of a word to be written in first memory units, erasing a word to be modified, formed by first memory cells connected to a word line and first bit lines, reading bits stored in the memory cells of a word line WL, in a first read mode and storing the bits read in second memory units, reading in a second read mode the bits stored in the memory cells of the word line, and programming each memory cell of the word line connected to a memory unit storing a bit in the programmed state of the word to be written, of an erased word or of a word comprising a bit having different states in the first and second read modes. | 12-04-2014 |
20140347931 | WRITING INTO AN EEPROM ON AN I2C BUS - An EEPROM circuit includes a data reception register and a column decoder. A buffer memory having a size corresponding to the size of a data page is included between the data reception register and the column decoder. | 11-27-2014 |
20140319653 | Integrated Switchable Capacitive Device - An integrated circuit includes a substrate. A fixed main capacitor electrode is disposed in a metal layer overlying the substrate. A second main capacitor electrode is disposed in a metal layer and spaced from the fixed main capacitor electrode. A movable capacitor electrode is disposed adjacent the fixed main capacitor electrode. The movable capacitor electrode is switchable between a first configuration in which the movable capacitor electrode and fixed main capacitor electrode are mutually spaced out in such a manner as to form an auxiliary capacitor electrically connected to the main capacitor. In a second configuration, the movable capacitor electrode and the fixed main capacitor electrode are in electrical contact in such a manner as to give a second capacitive value. | 10-30-2014 |
20140291858 | METHOD FOR MAKING A PHOTOLITHOGRAPHY MASK INTENDED FOR THE FORMATION OF CONTACTS, MASK AND INTEGRATED CIRCUIT CORRESPONDING THERETO - A method for making a photolithography mask for formation of electrically conducting contact pads between tracks of a metallization level and electrically active zones of integrated circuits formed on a semiconductor wafer includes forming a first mask region including first opening zones intended for the formation of the contact pads. The first opening zone has a first degree of opening that is below a threshold. A second mask region including additional opening zones is formed, with the overall degree of opening of the mask being greater than or equal to the threshold. | 10-02-2014 |
20140273836 | ANTICOLLISION MECHANISM FOR AN NFC DEVICE - An anticollision method for an NFC device wherein, in reader mode, a variation of a piece of information representative of the amplitude of the signal in an antenna of the device is monitored, and if this piece of information exceeds a threshold, the device is switched to the card mode. | 09-18-2014 |
20140209141 | Method for Generation of Electrical Power within a Three-Dimensional Integrated Structure and Corresponding Link Device - Method for generation of electrical power within a three-dimensional integrated structure comprising several elements electrically interconnected by a link device, the method comprising the production of a temperature gradient in at least one region of the link device resulting from the operation of at least one of the said elements, and the production of electrical power using at least one thermo-electric generator comprising at least one assembly of thermocouples electrically connected in series and thermally connected in parallel and contained within the said region subjected to the said temperature gradient. | 07-31-2014 |
20140208190 | METHOD FOR PROCESSING TRANSMISSION ERRORS, IN PARTICULAR NOISE, DURING A CONTACTLESS COMMUNICATION BETWEEN A CARD AND A READER - A method is for processing transmission errors during contactless communication of information between a device and a reader. The information may be transmitted in the form of frames sent to a send/receive module of the reader in contactless coupling with the device and controlled by a control module coupled to the send/receive module. The information may be extracted from the frames within the send/receive module so as to be delivered to the control module. The method may include a detection of transmission errors that are to be ignored. | 07-24-2014 |
20140201815 | ACCESS CONTROL MECHANISM TO A SECURE ELEMENT COUPLED TO AN NFC ROUTER - The invention relates to a method of protecting a security module ( | 07-17-2014 |
20140192021 | CAPACITIVE TOUCH PAD CONFIGURED FOR PROXIMITY DETECTION - The present disclosure relates to a method for controlling a touch pad, comprising an object locate mode for locating an object on the touch pad comprising steps of: determining a measurement of capacitance of each of the pairs of electrodes of the touch pad, each pair comprising a row electrode and a column electrode transverse to the row electrode, comparing each measurement with a first detection threshold, and if the comparison of at least one measurement with the first threshold reveals the presence of an object on the touch pad, locating the object on the touch pad according to the capacitance measurements, the method comprising a proximity detection mode comprising steps of: determining a measurement representative of the capacitance between one or two electrodes and one or two other electrodes of the touch pad, and comparing a measurement obtained with a second detection threshold different from the first threshold. | 07-10-2014 |
20140192008 | TOUCH ACQUISITION IN A PROJECTED CAPACITIVE TOUCH SCREEN SYSTEM - A capacitive touch panel includes first electrodes extending in first direction and second electrodes extending in a second (intersecting) direction. The first electrodes include parallel extending transmit first electrodes and receive first electrodes that are interleaved with each other. The second electrodes include parallel extending transmit second electrodes and receive second electrodes that are interleaved with each other. Transmit circuitry is coupled to the transmit first electrodes and transmit second electrodes. Receive circuitry coupled to the receive first electrodes and receive second electrodes. Processing circuitry controls activation of the transmit and receive circuitry in a manner which supports the making of adjacent line capacitance measurements and intersecting line capacitance measurements. The capacitance measurements are processed to identify and determine location of touches made on or near the capacitive touch panel. | 07-10-2014 |
20140191578 | INTEGRATED CIRCUIT POWER SUPPLY REGULATOR - The current signature of an electronic function is masked by controlling a current source that supplies power for the electronic function is controlled in a dynamically-varying manner. Excess current is detected and compared to a threshold. If the detected excess current meets the threshold, the operation of the electronic function is modified, for example by controlling a clock. | 07-10-2014 |
20140191385 | Process for Producing a Metal Device Housed in a Closed Housing within an Integrated Circuit, and Corresponding Integrated Circuit - An integrated circuit includes a number of metallization levels separated by an insulating region disposed over a substrate. A housing includes walls formed from metal portions produced in various metallization levels. A metal device is housed in the housing. An aperture is produced in at least one wall of the housing. An external mechanism outside of the housing is configured so as to form an obstacle to diffusion of a fluid out of the housing through the at least one aperture. At least one through-metallization passes through the external mechanism and penetrates into the housing through the aperture in order to make contact with at least one element of the metal device. | 07-10-2014 |
20140191329 | METHOD FOR PRODUCING METAL CONTACTS WITHIN AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT - An integrated circuit includes a MOS transistor having a gate region and source and drain regions separated from the gate region by insulating spacers. At least two metal contact pads respectively contact with two metal silicide regions (for example, a cobalt silicide) which lie within the source and drain regions. The silicide regions are located at the level of lower parts of the two metal contact pads and are separate by a distance from the insulating spacers. | 07-10-2014 |
20140191179 | VERTICAL BIPOLAR TRANSISTOR - The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer. | 07-10-2014 |
20140191178 | METHOD OF FABRICATING A VERTICAL MOS TRANSISTOR - The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole. | 07-10-2014 |
20140167908 | Integrated Mechanical Device for Electrical Switching - An integrated circuit comprising a mechanical device for electrical switching comprising a first assembly being thermally deformable and having a beam held at at least two different locations by at least two arms, the beam and the arms being metal and disposed within the same metallization level, and further comprising at least one electrically conducting body. The first assembly has a first configuration at a first temperature and a second configuration at a second temperature different from the first temperature. The beam is out of contact with the electrically conducting body in one configuration in contact with the body in the other configuration. The beam establishes or breaks an electrical link passing through the said at least one electrically conducting body and through the said beam in the different configurations. | 06-19-2014 |
20140138814 | Method for Producing an Integrated Circuit Pointed Element, and Corresponding Integrated Circuit - A method for producing an integrated circuit pointed element is disclosed. An element has a projection with a concave part directing its concavity towards the element. The element includes a first etchable material. A zone is formed around the concave part of the element. The zone includes a second material that is less rapidly etchable than the first material for a particular etchant. The first material and the second material are etched with the particular etchant to form an open crater in the concave part and thus to form a pointed region of the element. | 05-22-2014 |
20140133517 | DEVICE FOR MONITORING THE TEMPERATURE OF AN ELEMENT - A device for monitoring the temperature surrounding a circuit, including: a charge storage element; a charge evacuation device; and a thermo-mechanical switch connecting the storage element to the evacuation element, the switch being capable of closing without the circuit being electrically powered, when the temperature exceeds a threshold. | 05-15-2014 |
20140127873 | MANUFACTURING PROCESS OF MEMORY CELLS - A method for fabricating at least one cell of a semiconducting component includes positioning a first conducting polysilicon-type layer on a substrate, above an insulating oxide-type layer. The production of at least one trench within the first conducting layer is included to form two electrically unlinked distinct conducting parts intended to form two transistor gates of respectively two distinct twin cells. | 05-08-2014 |
20140118115 | PROTECTION OF COMMUNICATION BETWEEN AN ELECTROMAGNETIC TRANSPONDER AND A TERMINAL - A method for protecting communication between an electromagnetic transponder and a terminal, wherein the transmission of a polling request by the terminal is only allowed when the transponder is in mechanical contact or in quasi-mechanical contact with the terminal. | 05-01-2014 |
20140113692 | TRANSPONDER POSITIONING AID - A method for assisting with positioning of an electromagnetic transponder by a user with respect to a terminal, wherein: a current value of a ratio of the current coupling factor between the transponder and the terminal to an optimum coupling factor with a first resistive load value is calculated and stored; the current value is compared with a previous value of this ratio, stored in a previous iteration; and data elements intended for the user are controlled according to the comparison. | 04-24-2014 |
20140113555 | PROTECTION OF COMMUNICATION BY AN ELECTROMAGNETIC TRANSPONDER - A method for protecting communication between an electromagnetic transponder and a terminal, wherein the transmission of an acknowledgement for a request received from a terminal by the transponder is only allowed when the transponder is in mechanical contact or in quasi-mechanical contact with the terminal. | 04-24-2014 |
20140113554 | ASSISTANCE FOR POSITIONING A TRANSPONDER - A method for assisting with positioning of an electromagnetic transponder by a user with respect to a terminal, wherein: a first value of the current in an oscillating circuit of the terminal is periodically measured; a second value of a ratio between a no-load value of this current, stored when no transponder is in the field of the terminal, and the first value, is calculated; and pieces of information intended for the user are controlled according to said second value. | 04-24-2014 |
20140111230 | SYSTEM FOR DETECTING A LASER ATTACK ON AN INTEGRATED CIRCUIT CHIP - A system for detecting a laser attack on an integrated circuit chip formed in a semiconductor substrate, including a detection device capable of detecting voltage variations of the substrate. | 04-24-2014 |
20140097481 | NON-VOLATILE MEMORY WITH VERTICAL SELECTION TRANSISTORS - The present disclosure relates to a method for manufacturing a non-volatile memory on a semiconductive substrate, comprising the steps of implanting in the depth of the substrate a first doped region forming a source region of selection transistors, forming in the substrate a buried gate comprising deep parts extending between an upper face of the substrate and the first doped region, implanting between two adjacent deep parts of the buried gate, a second doped region forming a common drain region of common selection transistors of a pair of memory cells, the selection transistors of the pair of memory cells thus having channel regions extending between the first doped region and the second doped region, along faces opposite the two buried gate adjacent deep parts, and implanting along opposite upper edges of the buried gate, third doped regions forming source regions of charge accumulation transistors. | 04-10-2014 |
20140095750 | Method for Managing the Operation of a Circuit Connected to a Two-Wire Bus - A method is provided for managing the operation of a circuit operating in a slave mode. The circuit is connected to a bus having at least two of wires and a priority logic level. The slave circuit imposes the priority logic level on a first wire of the bus. While imposing, the slave circuit detects a possible conflict on the first wire resulting from a forcing, external to the slave circuit, of the first wire to another logic level. Upon detecting a conflict, the slave circuit is placed in a state stopping the sending by the circuit of any data over the bus while leaving the circuit listening to the bus. | 04-03-2014 |
20140079214 | CRYPTOGRAPHIC COUNTERMEASURE METHOD BY DERIVING A SECRET DATA - A method of protecting a circuit from attacks aiming to discover secret data used during the execution of a cryptographic calculation by the circuit, by, executing a transformation calculation implementing a bijective transformation function, receiving as input a secret data, and supplying a transformed data, executing a cryptographic calculation receiving as input a data to process and the transformed data, and executing an inverse transformation calculation receiving as input the result of the cryptographic calculation, and supplying a result that the cryptographic calculation would have supplied if it had been applied to the data to process and directly to the secret data, the data to process belong to a stream of a multiplicity of data, the transformed data being supplied as input to the cryptographic calculation for all the data of the stream. | 03-20-2014 |
20140077869 | Method for Modulating the Impedance of an Antenna Circuit - An electromagnetic transponder includes an antenna circuit, a load, and a charge pump transistor having a current path coupled between the antenna circuit and the load. During operation, a retromodulated signal is transmitted at a first level by biasing the charge pump transistor during a first time period such that an impedance of the antenna circuit has a first impedance value and current flows from the antenna circuit to the load. A retromodulated signal at a second level is transmitted by biasing the charge pump transistor during a second time period such that the impedance of the antenna circuit has a second impedance value different than the first impedance value and current flows from the antenna circuit to the load. The retromodulated signals are transmitted at the first and second levels in a sequence determined to transmit information from the electromagnetic transponder. | 03-20-2014 |
20140070829 | DEVICE FOR DETECTING THE THINNING DOWN OF THE SUBSTRATE OF AN INTEGRATED CIRCUIT CHIP - A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge. | 03-13-2014 |
20140055119 | Power Supply of a Load at a Floating-Potential - A circuit includes a current source intended to be series-connected with a load between two terminals of application of a first D.C. voltage. An element limits the voltage across the load and a circuit controls the value of the current in the current source with the current flowing in the element. | 02-27-2014 |
20140040539 | METHOD FOR WEAR LEVELING IN A NONVOLATILE MEMORY - A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased. | 02-06-2014 |
20140029146 | Electronic Device for Protecting Against a Polarity Reversal of a DC Power Supply Voltage, and its Application to Motor Vehicles - Disclosed herein is a device comprising a protection circuit configured to protect against a polarity reversal of the input DC power supply voltage, the protection circuit comprising an N-channel main transistor having a source coupled to an input terminal and having a drain coupled to an output terminal, a command circuit configured to render the main transistor blocked in the event of a polarity reversal and conducting otherwise, and a control circuit configured to dynamically adjust the bias of substrate regions of respective components connected to the main transistor by connecting the substrate regions either to the source or to the drain of the main transistor according to the value of the voltages present at the source and the drain of the main transistor and the type of conductivity of the substrate regions. | 01-30-2014 |
20140027881 | ELECTRIC CHARGE FLOW ELEMENT - An electric charge flow element including, on an insulating support, a stack of a first electrode, of a dielectric layer having at least one portion capable of letting charges flow by tunnel effect, and of a second electrode, wherein at least one of the electrodes is made of undoped polysilicon. | 01-30-2014 |
20140026670 | METHOD OF COMPENSATING FOR EFFECTS OF MECHANICAL STRESSES IN A MICROCIRCUIT - A method for manufacturing an integrated circuit includes forming in a substrate a measuring circuit sensitive to mechanical stresses and configured to supply a measurement signal representative of mechanical stresses exerted on the measuring circuit. The measuring circuit is positioned such that the measurement signal is also representative of mechanical stresses exerted on a functional circuit of the integrated circuit. A method of using the integrated circuit includes determining from the measurement signal the value of a parameter of the functional circuit predicted to mitigate an impact of the variation in mechanical stresses on the operation of the functional circuit, and supplying the functional circuit with the determined value of the parameter. | 01-30-2014 |
20130315263 | METHOD FOR TRANSMITTING AND RECEIVING DIGITAL INFORMATION IN THE FORM OF FRAMES WITH POSSIBLY ENCRYPTED PARITY BITS, AND CORRESPONDING TRANSCEIVER DEVICE - The information bits and the parity bits are encrypted in a microcontroller and transmitted on a bus to a transceiver head which forms the frames to be transmitted on a channel from encrypted information bits and from encrypted parity bits received on the bus. | 11-28-2013 |
20130314150 | Method for Detecting Electrical Energy Produced from a Thermoelectric Material contained in an Integrated Circuit - An integrated circuit includes active circuitry disposed at a surface of a semiconductor body and an interconnect region disposed above the semiconductor body. A thermoelectric material is disposed in an upper portion of the interconnect region away from the semiconductor body. The thermoelectric material is configured to deliver electrical energy when exposed to a temperature gradient. This material can be used, for example, in a method for detecting the repackaging of the integrated circuit after it has been originally packaged. | 11-28-2013 |
20130311855 | METHOD FOR PROCESSING A NON-VOLATILE MEMORY, IN PARTICULAR A MEMORY OF THE EEPROM TYPE, FOR THE STORAGE THEN THE EXTRACTION OF INFORMATION, AND CORRESPONDING MEMORY DEVICE - Method for processing a non-volatile memory designed to store words containing data bits and control bits allowing an error correction with an error correction code, the method comprising the storage of information in the memory plane comprising an operation for writing in the memory plane at least one digital word modified with respect to at least one initial digital word not having any erroneous bit, said at least one modified digital word containing a bit having a modified value with respect to the value of this bit in said at least one initial digital word, the other bits of the modified digital word having values identical to those of these same bits in the initial digital word, the position of the modified bit in said at least one modified digital word defining the value of the digital information. | 11-21-2013 |
20130278330 | LOW PASS FILTER WITH AN INCREASED DELAY - A low pass filter comprises a filter input node configured to receive a first logic signal, a filter output node configured to supply a second logic signal, a resistive element comprising a first terminal coupled to the input node and a second terminal coupled to the output node, and a capacitive element comprising a first terminal coupled to the output node and a second terminal. The filter further comprises an inverting gate having a first terminal coupled to the input node and a second terminal coupled to the second terminal of the capacitive element. | 10-24-2013 |
20130275817 | REGISTER PROTECTED AGAINST FAULT ATTACKS - A circuit and method of detecting a fault attack in a circuit includes a plurality of registers each identified by an address. The method includes storing in a memory the address present on an address bus during a write operation to one of said registers. In response to a first alert signal indicating that the data stored by a first of said registers has been modified, comparing the address identifying said first register with said stored address. | 10-17-2013 |
20130268123 | METHOD FOR MANAGING THE DIALOGUE BETWEEN AN ITEM OF EQUIPMENT AND AT LEAST ONE MULTI-APPLICATION OBJECT - The subject comprises processing means configured for communicating with an item of equipment according to a contactless communication protocol containing an anticollision procedure; the processing means (MT) comprise several application modules (MA | 10-10-2013 |
20130257587 | AUTHENTICATION OF A TERMINAL BY AN ELECTROMAGNETIC TRANSPONDER - A method of authentication of a terminal generating a magnetic field by a transponder including an oscillating circuit from which a D.C. voltage is generated, wherein at least one quantity depending on the coupling between the transponder and the terminal is compared with at least one reference value. | 10-03-2013 |
20130257401 | REGULATOR WITH LOW DROPOUT VOLTAGE AND IMPROVED OUTPUT STAGE - The regulator with low dropout voltage comprises an error amplifier and an output stage comprising an output transistor and a buffer circuit comprising an input connected to the output node of the error amplifier, an output connected to the output transistor, a follower amplifier connected between the input and the output of the buffer circuit. The buffer circuit furthermore comprises a transistor active load connected to the output of the follower amplifier and a negative feedback amplifier arranged in common gate configuration and connected between the output of the follower amplifier and the gate of the transistor of the active load. | 10-03-2013 |
20130250700 | NONVOLATILE MEMORY COMPRISING MINI WELLS AT A FLOATING POTENTIAL - The disclosure relates to an integrated circuit comprising a nonvolatile memory on a semiconductor substrate. The integrated circuit comprises a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the isolation layer and forming gates of selection transistors of memory cells, isolation trenches perpendicular to the conductive trenches and reaching the isolation layer, and conductive lines parallel to the conductive trenches, extending on the substrate and forming control gates of charge accumulation transistors of memory cells. The isolation trenches and the isolated conductive trenches delimit a plurality of mini wells in the substrate, the mini wells electrically isolated from each other, each having a floating electrical potential and comprising two memory cells. | 09-26-2013 |
20130250531 | ELECTRICALLY ACTIVATABLE INTEGRATED MECHANICAL ANTI-ROLLBACK DEVICE WITH ONE OR MORE POSITIONS - A thermally deformable assembly is formed in an integrated-circuit metallization level. The physical behavior of the metal forming the assembly brings the assembly into contact with a stop-forming body when subjected to a temperature change caused by a current flow. A natural rollback to the initial configuration in which the assembly is a certain distance away from the body is prevented. The state or configuration of the assembly is determined by a capacitive reader. | 09-26-2013 |
20130242442 | INTEGRATED CIRCUIT PROVIDED WITH A PROTECTION AGAINST ELECTROSTATIC DISCHARGES - An integrated circuit protected against electrostatic discharges, having output pads coupled to amplification stages, each stage including, between first and second power supply rails, a P-channel MOS power transistor in series with an N-channel MOS power transistor, this integrated circuit further including protection circuitry for simultaneously turning on the two transistors when a positive overvoltage occurs between the first and second power supply rails. | 09-19-2013 |
20130241649 | Regulator with Low Dropout Voltage and Improved Stability - The regulator with a low dropout voltage comprises an error amplifier comprising a differential pair of input transistors and a circuit with folded cascode structure connected to the output of the said differential pair, an output stage connected to the output node of the error amplifier, and a Miller compensation capacitor connected between the output stage and the cascode node on the output side (XP) of the cascode circuit; the error amplifier furthermore comprises at least one inverting amplifier module in a feedback loop between the said cascode node and the gate of the cascode transistor of the cascode circuit connected between the said cascode node and the said output node. | 09-19-2013 |
20130229875 | METHOD OF READING AND WRITING NONVOLATILE MEMORY CELLS - The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state. | 09-05-2013 |
20130228846 | NONVOLATILE MEMORY CELLS WITH A VERTICAL SELECTION GATE OF VARIABLE DEPTH - The disclosure relates to an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, and a buried gate common to the selection transistors of the memory cells. The buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and at least a second section of a second depth greater than the first depth penetrating into a buried source line. The lower side of the buried gate is bordered by a doped region forming a source region of the selection transistors and reaching the buried source line at the level where the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line. | 09-05-2013 |
20130227827 | METHOD OF GENERATING ELECTRICAL ENERGY IN AN INTEGRATED CIRCUIT, CORRESPONDING INTEGRATED CIRCUIT AND METHOD OF FABRICATION - A method of generating electrical energy in an integrated circuit that may include setting into motion a (3D) three-dimensional enclosed space in the integrated circuit. The 3D enclosed space may include a piezoelectric element and a free moving object therein. The method may also include producing the electrical energy from impact between the free moving object and the piezoelectric element during the motion. | 09-05-2013 |
20130225076 | RECHARGE OF AN NFC DEVICE - A mobile device including: a battery; an element for charging the battery; a near-field communication circuit; and a connection between the near-field communication circuit and the battery charge element. | 08-29-2013 |
20130225074 | NON-VOLATILE MEMORY FOR NFC ROUTER - A plurality of circuits in a same package including a first integrated circuit having at least one NFC-type communication interface and at least one communication interface of another type, and a second integrated circuit having a security module with a non-volatile memory, the non-volatile memory being used by the NFC interface to store configuration data. | 08-29-2013 |
20130222954 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge protection circuit is coupled to a power supply rail and a ground supply rail of an integrated circuit and includes at least one shunt configured to couple the supply rails and a trigger configured to supply on an output a shunt control voltage to a control terminal of the shunt to set the shunt in a coupling state when an ESD event is sensed on one of the supply rails. The protection circuit further comprises a voltage booster arranged between the output of the trigger and the control terminal of the shunt to boost the shunt control voltage. | 08-29-2013 |
20130207720 | OPERATIONAL AMPLIFIER WITH ELIMINATION OF OFFSET VOLTAGE - An operational amplifier may include a differential stage comprising two transistors whose gates are respectively linked to the two inputs of the operational amplifier. The sources of the two transistors may be linked to a first current source whose delivered current depends negatively on temperature variations and to a second current source whose delivered current is proportional to absolute temperature. The sum of these two currents may be less dependent on temperature, in that this link of the sources of the two transistors with the two current sources is effected respectively by way of two resistors, and in that the current which passes through the two transistors is imposed of proportional with temperature type, so as to allow substantially temperature-independent elimination of the offset voltage of the operational amplifier while obtaining a temperature-independent constant gain-bandwidth product. | 08-15-2013 |
20130201347 | PRESENCE DETECTION DEVICE - A user presence detection device includes a camera module with a silicon-based image sensor adapted to capture an image and a processing device configured to process the image to detect the presence of a user. The camera module further includes a light filter having a lower cut-off wavelength of between 550 nm and 700 nm and a higher cut-off wavelength of between 900 nm and 1100 nm. | 08-08-2013 |
20130200371 | DEVICE FOR DETECTING A LASER ATTACK IN AN INTEGRATED CIRCUIT CHIP - A device for detecting a laser attack in an integrated circuit chip formed in the upper P-type portion of a semiconductor substrate incorporating an NPN bipolar transistor having an N-type buried layer, including a detector of the variations of the current flowing between the base of said NPN bipolar transistor and the substrate. | 08-08-2013 |
20130193437 | DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST BACK SIDE ATTACKS - An integrated circuit including: a semiconductor substrate of a first conductivity type having at least one well of a second conductivity type laterally delimited, on two opposite walls, by regions of the first conductivity type, defined at its surface; at least one region of the second conductivity type which extends in the semiconductor substrate under the well; and a system for detecting a variation of the substrate resistance between each association of two adjacent regions of the first conductivity type. | 08-01-2013 |
20130181294 | METHOD FOR FABRICATION OF AN INTEGRATED CIRCUIT IN A TECHNOLOGY REDUCED WITH RESPECT TO A NATIVE TECHNOLOGY, AND CORRESPONDING INTEGRATED CIRCUIT - The technological fabrication of the integrated circuit includes a fabrication of the integrated circuit in a reduced technological version of a native technology including at least a first dimensional compensation applied to the reduced channel length and to the reduced channel width of each transistor originating from a transistor, referred to as a “minimum transistor”, designed in the native technology and having in this native technology an initial channel length equal to a minimum length for the native technology and an initial channel width equal to a minimum width for the native technology. The fabrication obtains a transistor having a channel length equal, to a given precision, to the initial channel length and a channel width equal, to a given precision, to the initial channel width. | 07-18-2013 |
20130159791 | METHOD AND DEVICE FOR FAULT DETECTION - The disclosure concerns a method implemented by a processing device. The method includes performing a first execution by the processing device of a computing function based on one or more initial parameters stored in a first memory device. The execution of the computing function generates one or more modified values of at least one of the initial parameters, wherein during the first execution the one or more initial parameters are read from the first memory device and the one or more modified values are stored in a second memory device. The method also includes performing a second execution by the processing device of the computing function based on the one or more initial parameters stored in the first memory device. | 06-20-2013 |
20130147004 | Integrated Capacitive Device Having a Thermally Variable Capacitive Value - An integrated circuit, comprising a capacitive device having a thermally variable capacitive value and comprising a thermally deformable assembly disposed within an enclosure, and comprising an electrically-conducting fixed body and a beam held at at least two different locations by at least two arms rigidly attached to edges of the enclosure, the beam and the arms being metal and disposed within the first metallization level. A part of the said thermally deformable assembly may form a first electrode of the capacitive device and a part of the said fixed body may form a second electrode of the capacitive device. The thermally deformable assembly has a plurality of configurations corresponding respectively to various temperatures of the said assembly and resulting in a plurality of distances separating the two electrodes and various capacitive values in the capacitive device corresponding to the plurality of distances. | 06-13-2013 |
20130146873 | Integrated Mechanical Device for Electrical Switching - An integrated circuit comprising a mechanical device for electrical switching comprising a first assembly being thermally deformable and having a beam held at at least two different locations by at least two arms, the beam and the arms being metal and disposed within the same metallization level, and further comprising at least one electrically conducting body. The first assembly has a first configuration at a first temperature and a second configuration at a second temperature different from the first temperature. The beam is out of contact with the electrically conducting body in one configuration in contact with the body in the other configuration. The beam establishes or breaks an electrical link passing through the said at least one electrically conducting body and through the said beam in the different configurations. | 06-13-2013 |
20130127549 | CLOCK SIGNAL SYNCHRONIZATION AND DISTURBANCE DETECTOR - An electronic circuit including two ring oscillators, wherein the output of each ring oscillator is looped back on the input of this same oscillator as well on the input of the other oscillator. The application of such a circuit to the detection of a dynamic disturbance. | 05-23-2013 |
20130119134 | PROTECTION OF A RADIO FREQUENCY TRANSMIT-RECEIVE TERMINAL AGAINST ELECTROMAGNETIC DISTURBANCES - An antenna circuit for a device of transmission/reception by inductive coupling, including a first inductive element in parallel with a capacitive element and, between each node of the parallel association and two terminals of a switch, a second inductive element. | 05-16-2013 |
20130114340 | SECURE MEMORY WHICH REDUCES DEGRADATION OF DATA - A method for managing a non-volatile memory may include a first phase of writing data to a first bank of a memory plane of the non-volatile memory, and then a second phase of writing the same data to a second bank of the same memory plane of the non-volatile memory in the case of success of the first writing phase. | 05-09-2013 |
20130104950 | Method of Wireless Communication Between Two Devices, Especially within One and the Same Integrated Circuit, and Corresponding System | 05-02-2013 |
20130100825 | METHOD FOR MANAGING COMMUNICATION BETWEEN AN ELECTRONIC DEVICE, FOR EXAMPLE A CONTACTLESS CHIP CARD, AND A COMMUNICATION APPARATUS, FOR EXAMPLE A READER, AND CORRESPONDING ELECTRONIC DEVICE - The device is equipped with several protocol decoding means (DCDi) corresponding respectively to various communication protocols so as to be capable of dialoguing with the said communication apparatus during transactions selectively according to one of these communication protocols; the method comprises an automatic protocol detection comprising a) an activation ( | 04-25-2013 |
20130094306 | INTEGRATED CIRCUIT COMPRISING A NON-DEDICATED TERMINAL FOR RECEIVING AN ERASE PROGRAM HIGH VOLTAGE - The disclosure relates to an integrated circuit electrically powered by a supply voltage and comprising a memory electrically erasable and/or programmable by means of a second voltage greater than the supply voltage. The integrated circuit comprises means for receiving the second voltage by the intermediary of a reception terminal of the supply voltage or by the intermediary of a reception or emission terminal of a data or clock signal. Applicable in particular to electronic tags comprising a reduced number of interconnection terminals. | 04-18-2013 |
20130094305 | DEVICE FOR SUPPLYING A HIGH ERASE PROGRAM VOLTAGE TO AN INTEGRATED CIRCUIT - The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal received by the integrated circuit and detecting in the data signal a write command of the memory, and a voltage supplier for applying the high voltage to a terminal of the integrated circuit when a write command of the memory has been detected by the monitor. | 04-18-2013 |
20130092987 | MOS TRANSISTOR WITH NO HUMP EFFECT - A MOS transistor formed in an active area of a semiconductor substrate and having a polysilicon gate doped according to a first conductivity type, the gate including two lateral regions of the second conductivity type. | 04-18-2013 |
20130088263 | ELECTRIC CHARGE FLOW CIRCUIT FOR A TIME MEASUREMENT - A charge flow circuit for a time measurement, including a plurality of elementary capacitive elements electrically in series, each elementary capacitive element leaking through its dielectric space. | 04-11-2013 |
20130080810 | OPTIMIZATION OF THE PROCESSING SPEED OF AN ELECTROMAGNETIC TRANSPONDER - A method for setting the clock frequency of a processing unit of an electromagnetic transponder, wherein a ratio between data, representative of a voltage across an oscillating circuit of the transponder and obtained for two values of the resistive load, is compared with one to decide whether to increase or decrease the clock frequency of the processing unit. | 03-28-2013 |
20130075726 | PROTECTION METHOD FOR AN ELECTRONIC DEVICE AND CORRESPONDING DEVICE - The semiconductor wafer for a silicon-on-insulator integrated circuit comprises an insulating region located between a first semiconductor substrate intended to receive the integrated circuit and a second semiconductor substrate containing at least one buried layer comprising at least one metal silicide. | 03-28-2013 |
20130069623 | CURRENT DETECTOR ALLOWING A LARGE SUPPLY VOLTAGE RANGE - The disclosure relates to a method for detecting a current comprising: generating a bias current, transmitting the bias current to a feedback stage and a measurement stage connected to the measurement node receiving a current to be measured, slaving a voltage to the measurement node at a constant value by the measurement and feedback stages, transmitting to an output stage, a current circulating in the measurement stage, which depends on the bias current and the current to be measured, and converting a current circulating in the output stage into a voltage. | 03-21-2013 |
20130064021 | SENSE AMPLIFIER WITH FAST BITLINE PRECHARGE MEANS - The disclosure relates to a sense amplifier comprising a cascode transistor and means for biasing the cascode transistor, supplying a control voltage to a gate terminal of the cascode transistor. The means for biasing the cascode transistor comprise means for isolating the gate terminal of the cascode transistor from the output of the voltage generator during a first period of the precharge phase, so as to boost the bitline voltage, then for linking the gate terminal to the output of the voltage generator during a second period of the precharge phase. Application in particular to sense amplifiers for non-volatile memories. | 03-14-2013 |
20130064015 | METHOD OF BURN-IN TEST OF EEPROM OR FLASH MEMORIES - The disclosure relates to a method for testing an integrated circuit, comprising in a burn-in test mode, two steps during which gate oxides of conductive high voltage MOS transistors of the integrated circuit are subjected to a first test voltage, and blocked high voltage MOS transistors of the integrated circuit are subjected to a second test voltage, the first test voltage being set to a value higher than a high supply voltage supplied to the high voltage MOS transistors in a normal operating mode, to make the gate oxides of transistors considered as insufficiently robust break down, the second test voltage being set to a value lower than the first test voltage and which can be supported by the blocked transistors, the states of the transistors being changed between the two steps. | 03-14-2013 |
20130064014 | EEPROM MEMORY PROTECTED AGAINST BREAKDOWN OF CONTROL GATE TRANSISTORS - The disclosure relates to an electrically erasable and programmable memory comprising at least one word of memory cells with first and second control gate transistors in parallel to apply a control gate voltage to the memory cells of the word. The memory also comprises s first control circuit to supply a first control voltage to a control terminal of the first control gate transistor through a first current limiter, and a second control circuit to supply a second control voltage to a control terminal of the second control gate transistor through second current limiter. | 03-14-2013 |
20130063157 | METHOD AND DEVICE FOR CHARACTERIZING OR MEASURING A FLOATING CAPACITANCE - The disclosure comprises: linking a first terminal of the capacitance to the mid-point of a first voltage divider bridge, applying a first voltage to a second terminal of the capacitance, maintaining a voltage of a mid-point of the first divider bridge near a reference voltage, and discharging a mid-point of a second divider bridge with a constant current. When a voltage of the mid-point of the second bridge reaches a first voltage threshold, applying a second voltage to the second terminal of the capacitance, and measuring the time for the voltage to reach a second threshold. | 03-14-2013 |
20130057298 | METHOD AND DEVICE FOR CHARACTERIZING OR MEASURING A CAPACITANCE - The disclosure relates to a method for characterizing or measuring a capacitance, comprising: linking the capacitance to a first mid-point of a first capacitive divider bridge, applying to the divider bridge a bias voltage, maintaining the voltage of the first mid-point near a reference voltage, discharging a second mid-point of a second divider bridge in parallel with the first by means of a constant current, and measuring the time for a voltage of the second mid-point to become equal to the voltage of the first mid-point. The disclosure may be applied in particular to the control of a touch screen display. | 03-07-2013 |
20130051153 | FLOATING ADDRESSING OF AN EEPROM MEMORY PAGE - A method for electrically programming a non-volatile memory in which a programming cycle includes prior addressing of memory cells from an initial address corresponding to a first row and a column of a memory plane. The method may include addressing the memory cells in a second consecutive row when the end of the first row i is reached to store data on bits with consecutive and increasing addresses in two consecutive rows. | 02-28-2013 |
20130026597 | METHOD OF GENERATING ELECTRICAL ENERGY IN AN INTEGRATED CIRCUIT DURING THE OPERATION OF THE LATTER, CORRESPONDING INTEGRATED CIRCUIT AND METHOD OF FABRICATION - An integrated circuit may include a region containing a thermoelectric material and be configured to be subjected to a temperature gradient resulting from a flow of an electric current in a part of the integrated circuit during its operation, and an electrically conducting output coupled to the region for delivering the electrical energy produced by thermoelectric material. | 01-31-2013 |
20130021240 | METHOD AND DEVICE FOR CONTROLLING AN APPARATUS AS A FUNCTION OF DETECTING PERSONS IN THE VICINITY OF THE APPARATUS - A method for controlling an electronic apparatus, includes steps of: acquiring an image of the environment of the apparatus, detecting the presence of human faces in the image acquired, estimating a respective position of each face detected in relation to the apparatus, and sending a signal to the apparatus to enable a function of the apparatus if a condition is met relating to a number of faces detected in the image and/or the estimated position of each detected face. | 01-24-2013 |
20130021093 | DUAL-FUNCTION INTEGRATED CIRCUIT - An electronic circuit in a package, including two functions, the package orientation activating a single one of the two functions. | 01-24-2013 |
20130020628 | PROCESS FOR FABRICATING A TRANSISTOR COMPRISING NANOCRYSTALS - A process for fabricating a transistor may include forming source and drain regions in a substrate, and forming a floating gate having electrically conductive nanoparticles able to accumulate electrical charge. The process may include deoxidizing part of the floating gate located on the source side, and oxidizing the space resulting from the prior deoxidation so as to form an insulating layer on the source side. | 01-24-2013 |
20130020477 | ULTRAVIOLET RADIATION MEASUREMENT SENSOR - A method for measuring radiation of energy photons, such as ultraviolet radiation, on a surface, may include programming at least one transistor by at least transmitting an electric charge to it. The method may further include measuring an electrical quantity of the at least one transistor receiving radiation of energy photons and estimating, based on this electrical quantity, an amount of radiation received. | 01-24-2013 |
20130016828 | PROTECTION OF A MODULAR EXPONENTIATION CALCULATION BY MULTIPLICATION BY A RANDOM QUANTITYAANM Teglia; YannickAACI BelcodeneAACO FRAAGP Teglia; Yannick Belcodene FR - A method for protecting a calculation, by an electronic circuit, of a modular exponentiation of a digital quantity, wherein: a first variable is initialized with a random quantity; at least one second variable is initialized with a value which is a function of the digital quantity; at least for a bit at 1 of an exponent of the modular exponentiation, the first variable is updated by: a) the quotient of its content and a power of the random quantity; and b) the product of its content by that of the second variable; and once all the exponent bits have been processed, the content of the first variable is divided by the random quantity to provide the result of the modular exponentiation. | 01-17-2013 |
20130016827 | PROTECTION OF A CALCULATION ON AN ELLIPTIC CURVEAANM Teglia; YannickAACI BelcodeneAACO FRAAGP Teglia; Yannick Belcodene FR - A method for protecting a calculation on an elliptic curve, by an electronic circuit, wherein a point of an elliptic curve is multiplied by a digital quantity, comprising the steps of: initializing a first variable with a value which is a function of a random quantity; initializing at least a second variable with a value which is a function of the digital quantity; at least for a bit at 1 of the digital quantity, the first variable is updated by: a) subtracting a multiple of the random quantity; and b) adding the content of the second variable; and once all the bits of the digital quantity have been processed, subtracting from the first variable the product of the point to by the random quantity to provide the result. | 01-17-2013 |
20130016826 | PROTECTION OF A MODULAR EXPONENTIATION CALCULATION BY ADDITION OF A RANDOM QUANTITYAANM Teglia; YannickAACI BelcodeneAACO FRAAGP Teglia; Yannick Belcodene FR - A method for protecting a calculation, by an electronic circuit, of a modular exponentiation of a digital quantity, wherein: a first variable is initialized with a random quantity increased by once unit; a second variable is initialized with the product of the digital quantity by the random quantity; a third variable is initialized with the digital quantity; iteratively for all the bits at 1 of an exponent of the modular exponentiation, the first variable is updated by: a) multiplying its content by that of the third variable; and b) subtracting thereto the content of the second variable increased by the random quantity; and once all the bits of the exponent have been processed, the content of the first variable is decreased by the random quantity to provide the result of the modular exponentiation. | 01-17-2013 |
20130015900 | COUNTERMEASURE METHOD AND DEVICE FOR PROTECTING DATA CIRCULATING IN AN ELECTRONIC MICROCIRCUIT - The disclosure relates to a countermeasure method in an electronic microcircuit, comprising successive process phases executed by a circuit of the microcircuit, and adjusting a power supply voltage between power supply and ground terminals of the circuit, as a function of a random value generated for the process phase, at each process phase executed by the circuit. | 01-17-2013 |
20130015549 | Integrated Thermoelectric GeneratorAANM Fornara; PascalAACI PourrieresAACO FRAAGP Fornara; Pascal Pourrieres FRAANM Rivero; ChristianAACI RoussetAACO FRAAGP Rivero; Christian Rousset FR - An integrated thermoelectric generator includes a semiconductor. A set of thermocouples are electrically connected in series and thermally connected in parallel. The set of thermocouples include parallel semiconductor regions. Each semiconductor region has one type of conductivity from among two opposite types of conductivity. The semiconductor regions are electrically connected in series so as to form a chain of regions having, alternatingly, one and the other of the two types of conductivity. | 01-17-2013 |
20130013965 | MICROPROCESSOR PROTECTED AGAINST STACK OVERFLOW - A microprocessor includes a central processing unit, at least one call stack, a stack pointer, an address bus, and a data bus. The microprocessor further includes a hardware monitor configured to supply protection codes, insert the protection codes in the stack or let the central processing unit insert them, and then generate an error signal in response to an attempt to modify a protection code present in the stack. | 01-10-2013 |
20130013820 | METHOD FOR INITIALIZING REGISTERS OF PERIPHERALS IN A MICROCONTROLLER - Embodiments described in the present disclosure relate to a method for initializing registers of peripherals of a microcontroller, including acts of: accessing initialization data in a non-volatile memory connected by a main bus to a processing unit of the microcontroller and to the peripherals, activating a peripheral including registers to be initialized, and transferring the data read into the registers of the activated peripheral, the initialization data being accessed in the memory by an initialization circuit distinct from the processing unit, the initialization data accessed being sent to the peripherals by an initialization bus distinct from the main bus. | 01-10-2013 |
20130011944 | STORAGE OF AN IMAGE IN AN INTEGRATED CIRCUIT - An integrated circuit including a substrate of a semiconductor material and first metal portions of a first metallization level or of a first via level defining pixels of an image. The pixels are distributed in first pixels, for each of which the first metal portion is connected to the substrate, and in second pixels, for each of which the first metal portion is separated from the substrate by at least one insulating portion. | 01-10-2013 |
20130007565 | METHOD OF PROCESSING FAULTS IN A MICROCONTROLLER - Embodiments described in the present disclosure relate to a method of processing faults in a control unit, the method including: upon each request for reading a datum in a first memory, received by a first interface circuit for accessing the first memory, calculating by means of the first interface circuit, a check word based on the datum read, if the check word calculated is different from a check word read in the memory in association with the datum read, activating an error signal by means of the first interface circuit, and sending the error signal to an output circuit of the control unit, without using any circuits of the control unit, likely to send a request to access the first memory. | 01-03-2013 |
20130002302 | COUNTERMEASURE METHOD AND DEVICE FOR PROTECTING DATA CIRCULATING IN AN ELECTRONIC COMPONENT - A countermeasure in a logic circuit having a logic gate supplying a binary output signal, the method including supplying binary data having random values to inputs of logic circuit during a precharge phase; supplying data to process to inputs of the logic circuit during a data processing phase; supplying on input of the logic circuit a precharge command signal launching a precharge phase; and under the effect of the precharge command signal, adapting the functioning of a logic gate of the logic circuit, statistically unbalanced, so that the output signal of the logic gate is in a binary state with a same probability as the random binary data supplied on input of the logic circuit during the precharge phase. | 01-03-2013 |
20120320681 | REDUCING THE PROGRAMMING CURRENT FOR MEMORY MATRICES - A sector of an electrically programmable non-volatile memory includes memory cells connected to word lines and to bit lines, each cell including at least one transistor having a gate connected to a word line, a drain connected to a bit line and a source connected to a source line. The sector includes at least two distinct wells insulated from one another, each including a number of cells of the sector, being able to take different potentials, and in that the sector has at least one bit line electrically linked to the drain of at least two cells mounted on two distinct wells. | 12-20-2012 |
20120320480 | DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT CHIP AGAINST ATTACKS - An integrated circuit chip includes: a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type; in each well of the first type, a plurality of MOS transistors having a channel of the second conductivity type, and in each well of the second type, a plurality of MOS transistors having a channel of the first type, transistors of neighboring wells being inverted-connected; and a device of protection against attacks, including: a layer of the second type extending under said plurality of wells, from the lower surface of said wells; and regions of lateral insulation between the wells, said regions extending from the upper surface of the wells to said layer. | 12-20-2012 |
20120320477 | DEVICE FOR DETECTING AN ATTACK IN AN INTEGRATED CIRCUIT CHIP - An integrated circuit chip including a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type, and a device of protection against attacks including: between the wells, trenches with insulated walls filled with a conductive material, said trenches extending from the upper surface of the wells to the substrate; and a circuit capable of detecting a modification of the stray capacitance formed between said conductive material and a region of the chip. | 12-20-2012 |
20120313223 | METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITHOUT GROUND CONTACT PAD - The disclosure relates to a method of fabricating an integrated circuit of CMOS technology in a semiconductor wafer comprising scribe lines. According to the disclosure, a ground contact pad of the integrated circuit is made in a scribe line of the wafer and is destroyed during a step of individualizing the integrated circuit by singulation of the wafer. A ground contact of the integrated circuit is made on the back side of the integrated circuit when it is assembled in an interconnection package. | 12-13-2012 |
20120307563 | NONVOLATILE MEMORY WITH BITLINE CAPACITIVE COUPLING COMPENSATION - A method of programming memory cells in a nonvolatile memory, includes applying a programming voltage to a first bitline and setting a second bitline in a floating state. The method further includes applying a compensation voltage to a shield conductive line coupled to the bitline set in the floating state, and setting in the floating state a shield conductive line coupled to the bitline receiving the programming voltage. The method is applicable to the reduction of the parasitic programming phenomena of memory cells by capacitive coupling between bitlines. | 12-06-2012 |
20120293239 | Device for Generating a Reference Current Proportional to Absolute Temperature, with Low Power Supply Voltage and Large Power Supply Rejection Rate - The device for generating a reference current proportional to absolute temperature comprises processing means connected to the terminals of a core and designed to equalize the voltages across the terminals of the core, the core being designed to then be traversed by an internal current proportional to absolute temperature, and an output module designed to deliver to an output terminal the said reference current on the basis of the said internal current; the processing means comprise a self-biased amplifier possessing at least one first stage arranged according to a folded setup and comprising first PMOS transistors arranged in a setup of the common-gate type, and a feedback stage whose input is connected to the output of the amplifier and whose output is connected to the input of the first stage as well as to at least one terminal of the core. | 11-22-2012 |
20120293154 | GENERATION OF A TEMPERATURE-STABLE VOLTAGE REFERENCE - A circuit for generating a temperature-stable reference voltage, including, between two terminals of application of a D.C. voltage: a current source and at least two parallel branches, each comprising a resistive element and one or several transistors, the transistors being different form one another and the reference voltage being sampled between the terminals of said branches. | 11-22-2012 |
20120293149 | Device for Generating an Adjustable Bandgap Reference Voltage with Large Power Supply Rejection Rate - An adjustable bandgap reference voltage comprises means for generating current proportional to absolute temperature comprising first means connected to terminals of a core and designed to equalize voltages across the terminals, means for generating a current inversely proportional to absolute temperature connected to the core, and an output module designed to generate the reference voltage; the first processing means comprise a first amplifier possessing a stage, biased by the current inversely proportional to absolute temperature, arranged according to a folded setup and comprising first PMOS transistors arranged according to a common-gate setup, and a stage whose input is connected to the amplifier output and whose output is connected to the first stage input and to a terminal of the core, the second generating means comprise a follower amplifier setup connected to a terminal of the core and separated from the first amplifier, the output module is connected to the feedback stage. | 11-22-2012 |
20120293143 | Method and Device for Generating an Adjustable Bandgap Reference Voltage - Generating an adjustable bandgap reference voltage comprises generating a current proportional to absolute temperature comprising an equalization of the voltages across the terminals of a core designed to then be traversed by the said current proportional to absolute temperature, generating a current inversely proportional to absolute temperature, summing these two currents and generating said bandgap reference voltage on the basis of the said sum of currents; the said equalization comprises a connection across the terminals of the core of a first fed-back amplifier possessing at least one first stage arranged as a folded setup and comprising first PMOS transistors arranged according to a common-gate setup, and a biasing of the said first stage on the basis of the said current inversely proportional to absolute temperature, the said summation of the two currents being performed in the feedback stage of the first amplifier. | 11-22-2012 |
20120284808 | PROTECTION OF A NON-VOLATILE MEMORY BY CHANGE OF INSTRUCTIONS - A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes authorized or forbidden as a content of the areas is associated with each of these areas. | 11-08-2012 |
20120284796 | PROTECTION OF A VOLATILE MEMORY AGAINST VIRUSES BY MODIFICATION OF THE CONTENT OF AN INSTRUCTION - A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes for which the access to the areas is authorized or forbidden is associated with each of these areas. | 11-08-2012 |
20120256180 | METHOD OF EVALUATING A SEMICONDUCTOR WAFER DICING PROCESS - Embodiments of the disclosure relate to a method of evaluating a semiconductor wafer dicing process, comprising providing evaluation lines extending in at least one scribe line of the wafer, dicing the wafer in the scribe line, evaluating the length of the evaluation lines, providing an information about their length, and using the information to evaluate the dicing process. | 10-11-2012 |
20120250417 | HOT ELECTRON INJECTION NANOCRYSTALS MOS TRANSISTOR - The disclosure relates to a hot electron injection MOS transistor, comprising source and drain regions formed in a semiconductor substrate, a control gate, and a floating gate comprising electrically conductive nanoparticles. The control gate comprises a first portion arranged at a first distance from the substrate, a second portion arranged at a second distance less than the first distance from the substrate, and an intermediary portion linking the first and the second portions. | 10-04-2012 |
20120226834 | METHOD FOR ENABLING SEVERAL VIRTUAL PROCESSING UNITS TO DIRECTLY AND CONCURRENTLY ACCESS A PERIPHERAL UNIT - The present disclosure relates to a method for enabling a virtual processing unit to access a peripheral unit, the virtual processing unit being implemented by a physical processing unit connected to the peripheral unit, the method comprising a step of transmitting to the peripheral unit a request sent by the virtual processing unit to access a service provided by the peripheral unit, the access request comprising at least one parameter and an identifier of the virtual unit, the method comprising steps, executed by the peripheral unit after receiving an access request, of allocating a set of registers to the virtual unit identifier received, storing the parameter received in the register set allocated, and when the peripheral unit is available for processing a request, selecting one of the register sets, and triggering a process in the peripheral unit from the parameters stored in the selected register set. | 09-06-2012 |
20120200472 | METHOD OF CONNECTING ONE OR MORE CONTACTLESS COMPONENTS TO A SINGLE ANTENNA, AND CORRESPONDING SYSTEM - A first component (CMP | 08-09-2012 |
20120190332 | PROTECTION OF A SECURITY ELEMENT COUPLED TO AN NFC CIRCUIT - A method and a device for protecting a security module connected to a near-field communication router in a telecommunication device, wherein a transmission between the router and the security module is only allowed in the presence of a radio frequency communication flow detected by the router. | 07-26-2012 |
20120190305 | BATTERY LEVEL INDICATION BY PORTABLE TELEPHONE - Methods for indicating the state of charge of the battery of a portable object, comprising a step for contactless transmission from a portable object to a telephone of the state of charge of the battery of the portable object, and a step for indication, via a human-machine interface of the telephone, of the state of charge of the battery of the portable object. | 07-26-2012 |
20120189146 | CONTACTLESS RECHARGING OF THE BATTERY OF A PORTABLE OBJECT BY A TELEPHONE - A method for charging the battery of a portable object by a telephone, comprising a step for contactless transmission of power from a charging device of the telephone to the portable object, inducing the charging of the battery of the portable object. | 07-26-2012 |
20120174234 | COUNTERMEASURE METHOD AND DEVICE FOR PORTECTING DATA CIRCULATING IN AN ELECTRONIC COMPONENT - The disclosure relates to a countermeasure method in an electronic component, wherein binary data are transmitted between binary data storage units, binary data being transmitted in several transmission cycles comprising a first cycle comprising: randomly selecting bits of the data, transmitting the selected bits and transmitting bits, each having a randomly chosen value, instead of transmitting non-selected bits of the data. A last transmission cycle comprises transmitting bits of the data that have not been transmitted during a previous cycle. | 07-05-2012 |
20120159025 | Method and Device for Communication between a Master and a Number of Slaves According to a Serial Communication Protocol, in particular of the Open Drain Type - According to one implementation, the slave identifier bits are tested recursively in groups of p bits. For these p bits, each slave will recognize, in its p corresponding identifier bits, one combination out of the 2p possible combinations. The slaves respond simultaneously ( | 06-21-2012 |
20120153422 | Imaging Device with Filtering of the Infrared Radiation - An imaging device includes at least one photosite formed in a semiconducting substrate and fitted with a filtering device for filtering at least one undesired radiation. The filtering device is buried in the semiconducting substrate at a depth depending on the wavelength of the undesired radiation. | 06-21-2012 |
20120149443 | CONTACTLESS COMMUNICATION WITH AUTHORIZATION BY HUMAN CONTACT - A transponder comprising a resonant circuit, comprising an antenna and a capacitor, and at least one memory connected to the resonant circuit via an intermediate circuit, characterized in that the intermediate circuit comprises at least one contact zone for receiving a portion of human body, so that the positioning of a portion of human body on a contact zone modifies the intermediate circuit, capable of switching from a first state in which it does not allow the memory to be read and/or written to a second state in which it allows the memory to be read and/or written when the resonant circuit of the transponder is contactlessly powered by a reader. | 06-14-2012 |
20120149335 | CONTACTLESS COMMUNICATION WITH AUTHORIZATION BY HUMAN CONTACT AND VISUAL INDICATOR - Transponder comprising a resonant circuit, comprising an antenna and a capacitor, and at least one memory, wherein it comprises at least one contact zone for receiving a portion of human body, so that the positioning of a portion of human body on a contact zone modifies the electric circuit of the transponder, capable of switching from a first state in which it does not allow the memory to be read and/or written to a second state in which it allows the memory to be read and/or written when the resonant circuit of the transponder is contactlessly powered by a reader and in that it comprises an indicator which makes it possible to indicate that the positioning of a portion of human body on the contact zone of the transponder is or has been recognized. | 06-14-2012 |
20120139870 | CAPACITIVE TOUCH PAD CONFIGURED FOR PROXIMITY DETECTION - The present disclosure relates to a method for controlling a touch pad, comprising an object locate mode for locating an object on the touch pad comprising steps of: determining a measurement of capacitance of each of the pairs of electrodes of the touch pad, each pair comprising a row electrode and a column electrode transverse to the row electrode, comparing each measurement with a first detection threshold, and if the comparison of at least one measurement with the first threshold reveals the presence of an object on the touch pad, locating the object on the touch pad according to the capacitance measurements, the method comprising a proximity detection mode comprising steps of: determining a measurement representative of the capacitance between one or two electrodes and one or two other electrodes of the touch pad, and comparing a measurement obtained with a second detection threshold different from the first threshold. | 06-07-2012 |
20120139563 | METHOD FOR CONTROLLING A CAPACITIVE TOUCH PAD - The present disclosure relates to a method for measuring a capacitance of a pair of electrodes including charging the pair of electrodes and transferring the charge between the pair of electrodes and a sampling capacitor, and a measuring step representative of the capacitance of the pair of electrodes according to the voltage at the terminals of the sampling capacitor according to the number of cycles executed so that the voltage at the terminals of the sampling capacitor reaches a threshold voltage. According to the present disclosure, the method comprises an initial step of charging the sampling capacitor between a first voltage and a second intermediate voltage in between the first voltage and a third voltage greater than or equal to a ground voltage, the pair of electrodes being charged between the second voltage and the third voltage. The present disclosure applies in particular to the control of a touch pad. | 06-07-2012 |
20120139562 | DIRECTIONAL CAPACITIVE PROXIMITY SENSOR - The present disclosure relates to a method for detecting an object near an electronic system, comprising steps of: forming electrodes around a central area, on an electrically insulating medium, determining measurements representative of the capacitance of the electrodes, and comparing the measurements with a detection threshold, and deducing whether or not an object is near the central area in a detection, the electrically insulating medium on which the electrodes are formed being deposited on an electrically conductive medium forming a shield, the capacitance measurements being taken by simultaneously activating all the electrodes. | 06-07-2012 |
20120131533 | METHOD OF FABRICATING AN INTEGRATED CIRCUIT PROTECTED AGAINST REVERSE ENGINEERING - The disclosure relates to a method of fabricating an integrated circuit on a semiconductor chip, the method comprising: designing an architecture of the integrated circuit comprising at least first and second standard cells implementing a same basic function; designing for the standard cell at least first and second cell layouts presenting random differences; designing an integrated circuit layout corresponding to the integrated circuit architecture; fabricating the integrated circuit according to the integrated circuit layout; using the first cell layout to implement the first standard cell in the integrated circuit layout; and using the second cell layout to implement the second standard cell in the integrated circuit layout. The method can be used for protection of an integrated circuit against reverse engineering. | 05-24-2012 |
20120124258 | CONVERSION OF A SINGLE-WIRE BUS COMMUNICATION PROTOCOL - A method of transmission-reception over a serial bus placed, when idle, in a first state at a first voltage, including: a transmit circuit capable of coding a transmission according to a first protocol in which the respective states of the bits are conditioned by time periods of fixed levels, indifferently in the first state or in a second state at a second voltage smaller than the first one; a receive circuit capable of interpreting a communication according to the first protocol; and a protocol converter, interposed between the bus and the transmit and receive circuits, to convert the signals to be transmitted to a second protocol in which the respective states of the bits are conditioned by respective time periods of fixed levels in the first state, and to convert the received signals from the second protocol to the first protocol. | 05-17-2012 |
20120119822 | Method for Modulating the Impedance of an Antenna Circuit - An electromagnetic transponder includes an antenna circuit capable of providing signals to a charge pump. The pump includes a first transistor connected to a first capacitor. The transponder also includes means for applying a voltage alternating between first and second values between the gate and the conduction terminal on the side of the first capacitor of the first transistor. | 05-17-2012 |
20120108169 | METHOD AND DEVICE FOR MANAGING INFORMATION EXCHANGE BETWEEN FOR EXAMPLE A NFC CONTROLLER AND A SET OF AT LEAST TWO SECURE ELEMENTS - The device may include a contactless element and a set of least two auxiliary elements. Each auxiliary element may include a slave SWP interface connected to a same master SWP interface of the contactless element through a SWP link, and a management module configured for activating at once only one slave SWP interface on the SWP link. | 05-03-2012 |
20120106732 | CRYPTOGRAPHIC COUNTERMEASURE METHOD BY DERIVING A SECRET DATA - A method of protecting a circuit from attacks aiming to discover secret data used during the execution of a cryptographic calculation by the circuit, by, executing a transformation calculation implementing a bijective transformation function, receiving as input a secret data, and supplying a transformed data, executing a cryptographic calculation receiving as input a data to process and the transformed data, and executing an inverse transformation calculation receiving as input the result of the cryptographic calculation, and supplying a result that the cryptographic calculation would have supplied if it had been applied to the data to process and directly to the secret data, the data to process belong to a stream of a multiplicity of data, the transformed data being supplied as input to the cryptographic calculation for all the data of the stream. | 05-03-2012 |
20120105012 | POWER RECOVERY BY AN ELECTROMAGNETIC TRANSPONDER - A method of power recovery by an electromagnetic transponder in the field of a terminal, wherein: a ratio of the current coupling factor of the transponder with the terminal to an optimum coupling position with a resistive load value is evaluated; and a detuning of the oscillating circuit is caused if the ratio is greater than a first threshold greater than or equal to one. | 05-03-2012 |
20120104632 | PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING AN ANALOG BLOCK AND A DIGITAL BLOCK, AND CORRESPONDING INTEGRATED CIRCUIT - The integrated circuit comprises an analog block and a digital block in and/or on the same substrate. At least part of a first integrated-circuit portion (BA | 05-03-2012 |
20120102248 | MASTER-SLAVE COMMUNICATION OVER A SINGLE-WIRE BUS BETWEEN A MASTER CIRCUIT AND AT LEAST TWO SLAVE CIRCUITS - A method of transmission over a serial bus, between a master circuit and two slave circuits, wherein each slave circuit makes the transmission of a first one of two binary states depend on the absence of a transmission of the second binary state by the other slave circuit. | 04-26-2012 |
20120097838 | IMAGING DEVICE IN PARTICULAR OF THE CMOS TIME DELAY AND INTEGRATION TYPE - An imaging device may be formed in a semiconductor substrate including a matrix array of photosites extending in a first direction and a second direction. The imaging device may include a transfer module configured to transfer charge in the first direction and an extraction module configured to extract charge in the second direction. | 04-26-2012 |
20120092901 | POWER MANAGEMENT IN AN ELECTROMAGNETIC TRANSPONDER - A method for managing the power in an electromagnetic transponder in the field of a terminal, including the steps of: evaluating the power consumption of the transponder circuits; and if this power consumption is below a threshold, evaluating the current coupling factor between the transponder and the terminal and, according to the current coupling: causing an increase of the transponder power consumption or causing a detuning of an oscillating circuit of the transponder. | 04-19-2012 |
20120091553 | Method for Detecting the Repackaging of an Integrated Circuit after it has been Originally Packaged, and Corresponding Integrated Circuit - An integrated circuit includes active circuitry disposed at a surface of a semiconductor body and an interconnect region disposed above the semiconductor body. A thermoelectric material is disposed in an upper portion of the interconnect region away from the semiconductor body. The thermoelectric material is configured to deliver electrical energy when exposed to a temperature gradient. This material can be used, for example, in a method for detecting the repackaging of the integrated circuit after it has been originally packaged. | 04-19-2012 |
20120087228 | DATA MEDIUM OF THE COMPACT DISC TYPE, IN PARTICULAR FITTED WITH PROTECTION AGAINST COPYING, AND CORRESPONDING METHOD - A data medium of the compact disc type may include medium areas of different types configured to define digital content, and a controllable element having two different states corresponding respectively to the two different types of areas. The controllable element may be configured to take selectively one of its states in response to a command, so as to modify in a controllable manner the content of the data medium. | 04-12-2012 |
20120081092 | LOW ELECTROMAGNETIC EMISSION DRIVER - The disclosure concerns circuitry for controlling a power transistor of a drive circuit arranged to drive an electrical component, the circuitry comprising: a variable current source adapted to set the level of a current for charging a control terminal of said power transistor; and a control circuit adapted to control said variable current source in a continuous manner based on a feedback voltage. | 04-05-2012 |
20120080620 | METHOD AND DEVICE FOR DETECTING METALS IN A FLUID - A method detects metallic atoms in a fluid. The method includes: placing, in a zone sheltered from light, a photodiode comprising a photosensitive surface in contact with a fluid to analyze; heating the photosensitive surface of the photodiode to a temperature sufficient to allow metallic atoms deposited on the photosensitive surface to migrate through this surface; acquiring a signal relative to the lighting of the photodiode; and determining, from the acquired signal, a measurement representative of a contamination status by metallic atoms of the photodiode. | 04-05-2012 |
20120079151 | IDENTIFICATION, BY A MASTER CIRCUIT, OF TWO SLAVE CIRCUITS CONNECTED TO A SAME BUS - A method of communication between a master circuit and two slave circuits over a serial bus wherein: the two slave circuits simultaneously transmit their associated identifiers; the two slave circuits simultaneously transmit the inverse of these identifiers; and each slave circuit exploits the combinations present on the bus to determine an order of communication between the two circuits. | 03-29-2012 |
20120068689 | EEPROM CELL WITH CHARGE LOSS - An EEPROM memory cell that includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer, wherein the insulation layer includes a first portion and a second portion having lower insulation properties than the first one, the second portion being located at least partially above a channel area of the transistor. | 03-22-2012 |
20120066571 | KEY EXTRACTION IN AN INTEGRATED CIRCUIT - A method of extraction of a key from a physical unclonable function exploiting the states of cells of a volatile memory after a powering on, wherein: cells are read according to addresses stored in a non-volatile memory; an error-correction code corrects the read states; and, in case an error has been corrected, the address of the cell providing an erroneous state is replaced in the non-volatile memory with that of another cell providing the non-erroneous state. | 03-15-2012 |
20120035883 | METHOD OF DETECTING AN OBJECT WITH A PROXIMITY SENSOR - The disclosure relates to a method of detecting an object using a detection signal supplied by a proximity sensor. The method comprises the steps of generating a reference signal by filtering the value of the detection signal, defining a first detection threshold, and going from an object non-detecting state to an object detecting state when the value of the detection signal becomes greater than the first detection threshold. When the value of the detection signal becomes greater than the first detection threshold, the value of the reference signal is readjusted in a manner such that the value of the detection signal again becomes less than or respectively greater than, the first detection threshold. | 02-09-2012 |
20120030753 | MULTIPROTOCOL COMMUNICATION AUTHENTICATION - A method for authenticating a transmission between a first and a second circuit transiting through at least one third circuit, wherein: data are transmitted from the first to the third circuit, and from the third to the second circuit; a first signature of the data is calculated by the first circuit; at least a second signature of the data is calculated by the third circuit; at least one first portion of the first signature is transmitted by the first circuit to the third one; and the second signature is transmitted by the third circuit to the second one, a portion of this signature being distorted in case of a failure of authentication of the first portion of the first signature by the third circuit. | 02-02-2012 |
20120030443 | PROTECTION OF SECRET KEYS - A method for protecting at least first data of a non-volatile memory from which the extraction of this first data is triggered by the reading or the writing, by a processor from or into the memory, of second data independent from the first data, said first data being provided to a circuit which the processor cannot access. | 02-02-2012 |
20120030388 | CONVERSION OF A TWO-WIRE BUS INTO A SINGLE-WIRE BUS - A method of conversion by at least one interface circuit connected between a first bus including at least one data wire and one clock wire, and at least one second single-wire bus, of a transmission between a master circuit connected to the first bus and at least one slave circuit connected to the second bus, wherein a speculative read command is sent to the slave circuit before interpreting the state of a bit for controlling a reading or a writing, originating from the master circuit. | 02-02-2012 |
20120027104 | SINGLE-WIRE BUS COMMUNICATION PROTOCOL - A method for transmitting data over a single-wire bus wherein a first communication channel is defined by pulses of different durations according to the state of the transmitted bit and depending on a reference duration, and a second communication channel is defined by the reference duration. | 02-02-2012 |
20120023580 | METHOD FOR DETECTING AN ATTACK BY FAULT INJECTION INTO A MEMORY DEVICE, AND CORRESPONDING DETECTION SYSTEM - The method for detecting an attack by fault injection into memory positions includes a generation of an initial value of a reference indication including an application of a reversible mathematical operator to the values of the information stored in the memory positions. An updating of the value of this reference indication is performed on each write in at least one memory position by using the operator, the reverse operator and the values of the stored information before and after each write in the at least one memory position. And, in the presence of a request, a check is performed as to whether a criterion involving the values of the information stored in the memory positions at the time of the request and the operator or its reverse is or is not satisfied by the value of the reference indication at the time of the request. | 01-26-2012 |
20120014024 | Method of Testing a Structure Protected from Overvoltages and the Corresponding Structure - An electronic device includes an electronic component and a protection circuit configured to protect the component from overvoltages. A control circuit is configured to inhibit a part of the protection circuit in the presence of a test voltage across terminals of the component. | 01-19-2012 |
20120009774 | DEVICE FOR DETECTING AN ATTACK AGAINST AN INTEGRATED CIRCUIT - An integrated circuit including an intrusion attack detection device. The device includes a single-piece formed of a conductive material and surrounded with an insulating material and includes at least one stretched or compressed elongated conductive track, connected to a mobile element, at least one conductive portion distant from said piece and a circuit for detecting an electric connection between the piece and the conductive portion. A variation in the length of said track in an attack by removal of the insulating material, causes a displacement of the mobile element until it contacts the conductive portion. | 01-12-2012 |
20110309521 | CHIP STACK WITH CONDUCTIVE COLUMN THROUGH ELECTRICALLY INSULATED SEMICONDUCTOR REGION - A method for stacking and interconnecting integrated circuits includes providing at least two substrates; forming a trench in each substrate; filling the trench with an insulating material; forming, in each substrate, at least one conductive area; thinning each substrate until reaching at least the bottom of the trench, to obtain in each substrate at least one electrically insulated region within the closed perimeter delineated by the trench; bonding the substrates together; making at least one hole through the bonded substrates so that the hole passes at least partially through the conductive areas and passes through the insulated region of each substrate; and filling the hole with an electrically conductive material so as to obtain a conductive column that traverses the isolated region of each substrate and is in lateral electrical contact with the conductive areas. | 12-22-2011 |
20110302539 | METHOD FOR DESIGNING MASKS USED TO FORM ELECTRONIC COMPONENTS - A method for designing masks adapted to the forming of integrated circuits, including the steps of: (a) forming a first test file including a set of configurations of integrated circuit elements; (b) forming a second test file comprising the elements of the first test file, less the elements corresponding to configurations forbidden by design rule manuals; (c) trans-forming the second test file by means of a set of logical operations implemented by computing means to obtain a mask file; (d) testing the mask file and, if the test is negative, modifying the design rule manuals; and (e) repeating steps (a) to (d) until the test of step (d) is positive. | 12-08-2011 |
20110300800 | EVALUATION OF THE COUPLING FACTOR OF AN ELECTROMAGNETIC TRANSPONDER BY CAPACITIVE DETUNING - A method for evaluating the current coupling factor between an electromagnetic transponder and a terminal, and a transponder implementing this method, wherein a ratio between data representative of a voltage across an oscillating circuit of the transponder and obtained for two capacitance values of the oscillating circuit is compared with one or several thresholds. | 12-08-2011 |
20110267094 | CIRCUIT AND METHOD FOR DETECTING A FAULT ATTACK - A device for detecting a fault attack, including: a circuit for detecting an interruption of a power supply; a circuit for comparing the duration of said interruption with a first threshold; and a counter of the number of successive interruptions of the power supply having a duration which does not exceed the first threshold. | 11-03-2011 |
20110265178 | Method and Device for Authenticating a User With the Aid of Biometric Data - Authentication system comprising an input device comprising a plurality of input elements configured for inputting respectively characters in response to an input of a sequence of at least one character carried out by a user, the input device comprising at least one determination means coupled to at least one input element in order to determine a force exerted on the said at least one input element, the system comprising a recording means for recording a series of at least one force exerted on the said at least one input element, a memory configured for storing a series of at least one reference force, and comparison means configured for comparing the series of at least one exerted force with the series of at least one reference force. | 10-27-2011 |
20110255560 | TRANSMISSION OVER AN 12C BUS - A method and a system of multichannel transmission over a twin-wire bus including a data signal and a synchronization signal, data of a first channel being transmitted by a state coding of the data signal for a time period containing a first state of the synchronization signal, data of a second channel being transmitted by pulse coding outside of said period. | 10-20-2011 |
20110255064 | PHOTOLITHOGRAPHY METHOD AND DEVICE - A photolithography method includes projecting a light beam through a mask onto a photosensitive layer to form on the photosensitive layer an image of a mask pattern formed by the mask, and controlling a layer of active elements of the mask so that the light beam after having traversed the layer of active elements, reproduces the mask pattern onto the photosensitive layer. The active elements are distributed throughout the layer of active elements in conformance with a matrical organization of lines and columns, each active element being individually controllable to take a state transparent to the light of the light beam, or else a state opaque to or reflecting of the light of the light beam, as a function of a command signal supplied to the active element. | 10-20-2011 |
20110253174 | METHOD FOR DECONTAMINATING SEMICONDUCTOR WAFERS - A method for decontaminating at least one object contained in a chamber, the method including a succession of alternated steps of lowering and increasing the pressure in the chamber. | 10-20-2011 |
20110248720 | TESTING SYSTEM FOR INTEGRATED CIRCUITS - A system for testing an integrated circuit including components for receiving clock signals corresponding to different clock domains includes a pin of the integrated circuit to receive a test clock signal for components included in different clock domains, clock gating cells integrated in the integrated circuit to direct said test clock signal from the pin towards components included in respective clock domains and, coupled to each of the gating cells, a dedicated flip-flop for a respective clock domain, the dedicated flip-flop being also integrated in the integrated circuit to effect on the cell to which it is coupled a clock gating function during testing of the integrated circuit. | 10-13-2011 |
20110234307 | COUNTERMEASURE METHOD AND DEVICE AGAINST AN ATTACK BY FAULT INJECTION IN AN ELECTRONIC MICROCIRCUIT - The disclosure relates to a method for detecting an attack in an electronic microcircuit, comprising: forming the microcircuit in a substrate, forming in the substrate a first well electrically isolated from the substrate, by a second well and an embedded well, forming in the first and second wells a data processing circuit comprising a ground terminal formed in the first well and a power supply terminal formed in the second well, and activating a detection signal when a voltage at the ground or power supply terminal of the data processing circuit crosses a threshold voltage. | 09-29-2011 |
20110225432 | METHOD AND CIRCUITRY FOR DETECTING A FAULT ATTACK - A method of detecting a fault attack during a cryptographic operation using at least one look-up table including a plurality of sub-tables each having a same number of values of a fixed bit length, a fixed relation existing between values at same locations in each sub-table, the method including: performing a load operation to retrieve from the look-up table data values from a same location in each sub-table; verifying that the fixed relation exists between at least two of the data values; and generating an output signal based on the verification. | 09-15-2011 |
20110222684 | PROTECTION OF REGISTERS AGAINST UNILATERAL DISTURBANCES - A method for protecting a key intended to be used by an electronic circuit in an encryption or decryption algorithm, including the steps of: submitting the key to a first function taking a selection value into account; storing all or part of the result of this function in at least two registers; when the key is called by the algorithm, reading the contents of said registers and submitting them to a second function taking into account all or part of the bits of the registers; and providing the result of the combination as an input for the algorithm, the second function being such that the provided result corresponds to the key. | 09-15-2011 |
20110215862 | INTERNAL SUPPLY VOLTAGE CIRCUIT OF AN INTEGRATED CIRCUIT - The disclosure relates to a method for generating a setpoint voltage in an integrated circuit, comprising generating a substantially constant reference voltage, and generating from the reference voltage, a setpoint voltage comprising a component equal to the highest threshold voltage of all the CMOS transistors of a circuit of the integrated circuit and a component which may be equal to zero. The disclosure applies in particular to the provision of a power supply voltage of a circuit based on CMOS transistors. | 09-08-2011 |
20110202948 | METHOD FOR DETECTING POTENTIALLY SUSPICIOUS OPERATION OF AN ELECTRONIC DEVICE AND CORRESPONDING ELECTRONIC DEVICE - A method may be for detecting potentially suspicious operation of an electronic device configured to operate in the course of activity sessions. The method may include within the device, a metering, from an initial instant of the number of activity sessions having a duration below a first threshold, and a comparison of this number with a second threshold. | 08-18-2011 |
20110194219 | INTEGRATED CIRCUIT PROVIDED WITH A PROTECTION AGAINST ELECTROSATATIC DISCHARGES - An integrated circuit protected against electrostatic discharges, having output pads coupled to amplification stages, each stage including, between first and second power supply rails, a P-channel MOS power transistor in series with an N-channel MOS power transistor, this integrated circuit further including protection circuitry for simultaneously turning on the two transistors when a positive overvoltage occurs between the first and second power supply rails. | 08-11-2011 |
20110181991 | STRUCTURE OF PROTECTION OF AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES - An integrated circuit protected against electrostatic discharges, including input/output pads and first and second power supply rails, and: a thyristor forward-connected between each input/output pad and the second rail, each thyristor including, between its anode gate and its anode, a resistor; between each thyristor and the first rail, a diode having its anode connected to the anode gate of the thyristor and having its cathode connected to the first rail via a resistor for adjusting the triggering; and a triggering device capable of conducting a current between the first and second rails when a positive overvoltage occurs between these rails. | 07-28-2011 |
20110176674 | COUNTERMEASURE METHOD AND DEVICE FOR PROTECTING DATA CIRCULATING IN AN ELECTRONIC COMPONENT - The present disclosure relates to a countermeasure method in an integrated circuit comprising at least one first logic circuit and at least one first input register supplying the first logic circuit with a datum, the method comprising steps of introducing a random datum into each first input register of the first logic circuit and of the first logic circuit reading the random datum in each first input register, then of introducing a datum to be processed into each first input register, and of the first logic circuit processing the datum in each first input register. | 07-21-2011 |
20110170691 | PROTECTION OF A CIPHERING KEY AGAINST UNIDIRECTIONAL ATTACKS - A method for protecting a key implemented, by an electronic circuit, in a symmetrical algorithm for ciphering or deciphering a message, including the steps of: selecting in non-deterministic fashion a pair of different masks from a set of at least four different masks, the masks having the property of representing different bit combinations, at least by pairs of bits; executing the algorithm twice by applying, to the key or to the message, one of the masks of the selected pair at each execution; checking the consistency between the two executions. | 07-14-2011 |
20110156756 | COUNTERMEASURE METHOD AND DEVICE FOR PROTECTING DATA CIRCULATING IN AN ELECTRONIC COMPONENT - A countermeasure in a logic circuit having a logic gate supplying a binary output signal, the method including supplying binary data having random values to inputs of logic circuit during a precharge phase; supplying data to process to inputs of the logic circuit during a data processing phase; supplying on input of the logic circuit a precharge command signal launching a precharge phase; and under the effect of the precharge command signal, adapting the functioning of a logic gate of the logic circuit, statistically unbalanced, so that the output signal of the logic gate is in a binary state with a same probability as the random binary data supplied on input of the logic circuit during the precharge phase. | 06-30-2011 |
20110150065 | MULTIPLE-CHANNEL TRANSMISSION OVER A SINGLE-WIRE BUS - A method for transmitting at least a synchronization and a data signal on a single-wire bus between a master device and at least one slave device, wherein a first transmission channel from the master device to the slave device modulates the periodic pulse width between a first level and second level of a same sign voltage relative to a reference potential, and a second transmission channel amplitude modulates at least one of the voltage levels between the level and at least one third level different from the two others and from the reference potential. | 06-23-2011 |
20110140852 | POWER MANAGEMENT IN AN ELECTROMAGNETIC TRANSPONDER - A method of evaluation, by an electromagnetic transponder in the field of a terminal generating a magnetic field, of power that can be extracted from this field, including the steps of: evaluating the current coupling between the transponder and the terminal; and deducing therefrom information relative to the power available in this coupling position. | 06-16-2011 |
20110128070 | CHARGE PUMP STAGE, METHOD FOR CONTROLLING A CHARGE PUMP STAGE AND MEMORY HAVING A CHARGE PUMP STAGE - A charge pump having a supply terminal, for receiving a supply voltage, and an output terminal, for supplying an output voltage. The charge pump has a control block including a comparator having a first comparison input, for receiving the supply voltage, a second comparison input, for receiving the output voltage, and a comparison output, for generating a pump-switch-off signal depending upon a comparison between the input voltage and the output voltage; and a switch controlled in switching off by the pump-switch-off signal and configured for switching off the charge pump circuit. The control block has an activation input for receiving an activation signal that has a plurality of pulses and repeatedly activates the comparator-circuit block. | 06-02-2011 |
20110128030 | MONITORING OF THE ACTIVITY OF AN ELECTRONIC CIRCUIT - A method and a device for monitoring a digital signal, wherein a first P-channel MOS transistor is placed in degradation conditions of negative bias temperature instability type during periods when the signal to be monitored is in a first state; a first quantity representative of the saturation current of the first transistor is measured when the signal to be monitored switches to a second state; and a detection signal is switched when this first quantity exceeds a threshold. | 06-02-2011 |
20110126085 | METHOD OF SIGNATURE VERIFICATION - A method of detecting a fault including generating at least one blinded data value based on at least one input value and at least one blinding parameter selected from a plurality of blinding parameters generating a first signature based on said at least one blinded data value; selecting, from a memory storing a plurality of reference signatures, one or more reference signatures and comparing said first signature with said one or more reference signatures in order to detect a fault. | 05-26-2011 |
20110119762 | METHOD AND APPARATUS FOR DETECTION OF A FAULT ATTACK - The invention concerns a method of detecting a fault attack including providing a plurality of blinding values; generating a first set of data elements including a first group of data elements and at least one additional data element generated by performing the exclusive OR between at least one data element in the first group and at least one of the blinding values; generating a second set of data elements corresponding to the exclusive OR between each data element of the first set and a selected one of the plurality of blinding values; generating a first signature by performing a commutative operation between each of the data elements of the first set; generating a second signature by performing the commutative operation between each of the data elements of the second set; and comparing the first and second signatures to detect a fault attack. | 05-19-2011 |
20110119532 | METHOD OF DETECTING A FAULT ATTACK - A method of detecting a fault attack including generating a first signature of a first group of data values by performing a single commutative non-Boolean arithmetic operation between all the data values of the first group; generating a second set of data values by performing a permutation of the first set of data values; generating a second signature of the second group of data values by performing said single commutative non-Boolean arithmetic operation between all the data values of the second group; and comparing the first and second signatures to detect a fault attack. | 05-19-2011 |
20110113256 | Secure Method for Processing a Content Stored Within a Component, and Corresponding Component - The component comprises a first memory (MM) comprising a first portion (P | 05-12-2011 |
20110108902 | MEMORY WITH A READ-ONLY EEPROM-TYPE STRUCTURE - A non-volatile memory including at least first and second memory cells each including a storage MOS transistor with dual gates and an insulation layer provided between the two gates. The insulation layer of the storage transistor of the second memory cell includes at least one portion that is less insulating than the insulation layer of the storage transistor of the first memory cell. | 05-12-2011 |
20110103584 | PROTECTION OF A CIPHERING KEY - A method for protecting a key used, by an electronic circuit, in a symmetrical algorithm for ciphering or deciphering a message, including the steps of complementing to one the key and the message; executing the algorithm twice, respectively with the key and the message and with the key and the message complemented to one, the selection between that of the executions which processes the key and the message and that which processes the key and the message complemented to one being random; and checking the consistency between the two executions. | 05-05-2011 |
20110103146 | MEMORY DEVICE OF THE ELECTRICALLY ERASABLE AND PROGRAMMABLE TYPE, HAVING TWO CELLS PER BIT - The memory device includes a memory cell unit of the electrically erasable and programmable non-volatile type including two memory cells respectively connected to two bit lines via two bit line select transistors. The common terminal between the bit line select transistor and the floating-gate transistor of each memory cell of the memory cell unit is connected to the control gate of the floating-gate transistor of the other memory cell of the memory cell unit. | 05-05-2011 |
20110092000 | METHOD FOR MANUFACTURING AND TESTING AN INTEGRATED ELECTRONIC CIRCUIT - A method for manufacturing and for testing an integrated circuit, including the steps of forming, on the upper portion of the integrated circuit, a passivation layer including openings at the level of metal tracks of the last interconnect stack of the integrated circuit; forming, in the openings, first pads connected to second pads formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit; testing the integrated circuit by bringing test tips in contact with the second pads; and eliminating at least a portion of at least one of the conductive track sections. | 04-21-2011 |
20110091034 | Secure Method for Cryptographic Computation and Corresponding Electronic Component - The secure method for cryptographic computation comprises processing of an input datum (D) by a cryptographic computation tool involving at least one encryption key (K) and at least one generated item of secret information, so as to provide an output datum (DC). The generation of the said at least one item of secret information (ST) comprises processing of the said input datum by at least one operator (OPS) having at least one secret characteristic. | 04-21-2011 |
20110090748 | DEVICE FOR SUPPLYING A HIGH ERASE PROGRAM VOLTAGE TO AN INTEGRATED CIRCUIT - The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal received by the integrated circuit and detecting in the data signal a write command of the memory, and a voltage supplier for applying the high voltage to a terminal of the integrated circuit when a write command of the memory has been detected by the monitor. | 04-21-2011 |
20110090747 | INTEGRATED CIRCUIT COMPRISING A NON-DEDICATED TERMINAL FOR RECEIVING AN ERASE PROGRAM HIGH VOLTAGE - The disclosure relates to an integrated circuit electrically powered by a supply voltage and comprising a memory electrically erasable and/or programmable by means of a second voltage greater than the supply voltage. The integrated circuit comprises means for receiving the second voltage by the intermediary of a reception terminal of the supply voltage or by the intermediary of a reception or emission terminal of a data or clock signal. Applicable in particular to electronic tags comprising a reduced number of interconnection terminals. | 04-21-2011 |
20110090745 | SENSE AMPLIFIER WITH FAST BITLINE PRECHARGE MEANS - The disclosure relates to a sense amplifier comprising a cascode transistor and means for biasing the cascode transistor, supplying a control voltage to a gate terminal of the cascode transistor. The means for biasing the cascode transistor comprise means for isolating the gate terminal of the cascode transistor from the output of the voltage generator during a first period of the precharge phase, so as to boost the bitline voltage, then for linking the gate terminal to the output of the voltage generator during a second period of the precharge phase. Application in particular to sense amplifiers for non-volatile memories. | 04-21-2011 |
20110087856 | Memory Device with Serial Protocol and Corresponding Method of Addressing - The memory device comprises a physical memory plane (PMP) comprising m first physical lines (RGP | 04-14-2011 |
20110080933 | DEVICE FOR DETECTING TEMPERATURE VARIATIONS IN A CHIP - A device for detecting temperature variations of the substrate of an integrated circuit chip, including, in the substrate, implanted resistors connected as a Wheatstone bridge, wherein each of two first opposite resistors of the bridge is covered with an array of metal lines parallel to a first direction, the first direction being such that a variation in the substrate stress along this direction causes a variation of the unbalance value of the bridge. | 04-07-2011 |
20110080190 | METHOD FOR PROTECTING AN INTEGRATED CIRCUIT CHIP AGAINST LASER ATTACKS - A method for protecting, against laser attacks, an integrated circuit chip formed inside and on top of a semiconductor substrate and including in the upper portion of the substrate an active portion in which are formed components, this method including the steps of: forming in the substrate a gettering area extending under the active portion, the upper limit of the area being at a depth ranging between 5 and 50 μm from the upper surface of the substrate; and introducing diffusing metal impurities into the substrate. | 04-07-2011 |