DSM Solutions, Inc. Patent applications |
Patent application number | Title | Published |
20100133593 | Junction Field Effect Transistor Having a Double Gate Structure and Method of Making Same - A junction field effect transistor includes a channel region, a gate region coupled to the channel region, a well tap region coupled to the gate region and the channel region, and a well region coupled to the well tap region and the channel region. A double gate operation is achieved by this structure as a voltage applied to the gate region is also applied to the well region through the well tap region in order to open the channel from both the gate region and the well region. | 06-03-2010 |
20100019289 | Junction Field Effect Transistor Using Silicide Connection Regions and Method of Fabrication - A junction field effect transistor comprises a semiconductor substrate and a well region formed in the substrate. A source region of a first conductivity type is formed in the well region. A drain region of the first conductivity type is formed in the well region and spaced apart from the source region. A channel region of the first conductivity type is located between the source region and the drain region and formed in the well region. A gate region of a second conductivity type is formed in the well region. The transistor further includes first, second, and third connection regions. The first connection region is in ohmic contact with the source region and formed of silicide. The second connection region is in ohmic contact with the drain region and formed of silicide. The third connection region in ohmic contact with the gate region. | 01-28-2010 |
20090311837 | Integrated Circuit Using Complementary Junction Field Effect Transistor and MOS Transistor in Silicon and Silicon Alloys - This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices. | 12-17-2009 |
20090282382 | SYSTEM AND METHOD FOR ROUTING CONNECTIONS WITH IMPROVED INTERCONNECT THICKNESS - A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media. | 11-12-2009 |
20090278570 | Circuit Configurations Having Four Terminal JFET Devices - Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode. | 11-12-2009 |
20090184734 | Method of Producing and Operating a Low Power Junction Field Effect Transistor - A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter. | 07-23-2009 |
20090164963 | SYSTEM AND METHOD FOR ROUTING CONNECTIONS - A method for modeling a circuit includes receiving a netlist that defines a plurality of connections between a plurality of circuit elements and identifying a subset of the connections. The method also includes routing the identified connections with a first group of wires having a first wire width and routing at least a portion of the remaining connections with a second wire width. The second wire width is smaller than the first wire width. The method further includes replacing the first group of wires with a third group of wires having the second wire width. | 06-25-2009 |
20090142889 | Oxide Isolated Metal Silicon-Gate JFET - A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer. | 06-04-2009 |
20090137088 | JFET Having a Step Channel Doping Profile and Method of Fabrication - A junction field effect transistor comprises a semiconductor substrate, a source region formed in the substrate, a drain region formed in the substrate and spaced apart from the source region, and a gate region formed in the substrate. The transistor further comprises a first channel region formed in the substrate and spaced apart from the gate region, and a second channel region formed in the substrate and between the first channel region and the gate region. The second channel region has a higher concentration of doped impurities than the first channel region. | 05-28-2009 |
20090134475 | Transistor Providing Different Threshold Voltages and Method of Fabrication Thereof - A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of the second portion allows for an increased ON current. Despite the increase attained in the ON current, the higher threshold voltage of the first portion maintains or lowers a relatively low OFF current for the transistor. | 05-28-2009 |
20090075435 | JFET With Built In Back Gate in Either SOI or Bulk Silicon - A process for manufacturing a Junction Field-Effect Transistor, comprises doping a semiconductor material formed on an insulating substrate with impurities of a first conductivity type to form a well region. The process continues by implanting impurities of a second conductivity type into said well region to form a channel region, and by implanting impurities of the first conductivity type in said well region to form a back gate region. The process continues by forming a trench to expose at least one sidewall of said channel region, wherein the trench extends far enough along the sidewall to expose at least a portion of said back gate region. The process continues by depositing polysilicon to fill said trench along the at least one sidewall of said channel region and at least a portion of said back gate region, wherein at least a portion of the polysilicon will form a gate contact. The polysilicon is then doped with impurities of a first conductivity type. The process concludes by annealing the polysilicon to activate the doped impurities and to cause the doped impurities to diffuse along the at least one sidewall of said channel region so as to form a top gate region. The top gate region extends far enough to make electrical contact with said back gate region. | 03-19-2009 |
20090072278 | Method for Applying a Stress Layer to a Semiconductor Device and Device Formed Therefrom - A semiconductor device includes a substrate of semiconductor material. A source region, a drain region, and a conducting region of the semiconductor device are formed in the substrate and doped with a first type of impurities. The conducting region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state. A gate region is also formed in the substrate and doped with a second type of impurities. The gate region abuts a channel region of the conducting region. A stress layer is deposited on at least a portion of the conducting region. The stress layer applies a stress to the conducting region along a boundary of the conducting region that strains at least a portion of the conducting region. | 03-19-2009 |
20090057727 | Integrated Circuit Using Complementary Junction Field Effect Transistor and MOS Transistor in Silicon and Silicon Alloys - This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices. | 03-05-2009 |
20090017585 | Self Aligned Gate JFET Structure and Method - A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second polysilicon which has been polished back to be flush with a top surface of a dielectric layer covering the tops of the source and drain contacts. The dielectric layer preferably has a nitride cap to act as a polish stop. In some embodiments, nitride covers the entire dielectric layer covering the source and drain contacts as well as the field oxide region defining an active area for said JFET. An embodiment with an epitaxially grown channel region formed on the surface of the substrate is also disclosed. | 01-15-2009 |
20080272439 | SMALL GEOMETRY MOS TRANSISTOR WITH THIN POLYCRYSTALLINE SURFACE CONTACTS AND METHOD FOR MAKING - Process for fabrication of MOS semiconductor structures and transistors such as CMOS structures and transistors with thin gate oxide, polysilicon surface contacts having thickness on the order of 500 Angstroms or less and with photo-lithographically determined distances between the gate surface contact and the source and drain contacts. Semiconductor devices having polysilicon surface contacts wherein the ratio of the vertical height to the horizontal dimension is approximately unity. Small geometry Metal-Oxide-Semiconductor (MOS) transistor with thin polycrystalline surface contacts and method and process for making the MOS transistor. MOS and CMOS transistors and process for making. Process for making transistors using Silicon Nitride layer to achieve strained Silicon substrate. Strained Silicon devices and transistors wherein fabrication starts with strained Silicon substrate. Strained Silicon devices which use a Silicon Nitride film applied to the substrate at high temperature and which use differential thermal contraction rates during cooling to achieve strained Silicon. | 11-06-2008 |
20080272422 | Transistor Providing Different Threshold Voltages and Method of Fabrication Thereof - A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of the second portion allows for an increased ON current. Despite the increase attained in the ON current, the higher threshold voltage of the first portion maintains or lowers a relatively low OFF current for the transistor. | 11-06-2008 |
20080272408 | ACTIVE AREA JUNCTION ISOLATION STRUCTURE AND JUNCTION ISOLATED TRANSISTORS INCLUDING IGFET, JFET AND MOS TRANSISTORS AND METHOD FOR MAKING - Integrated active area isolation structure for transistor to replace larger and more expensive Shallow Trench Isolation or field oxide to isolate transistors. Multiple well implant is formed with PN junctions between wells and with surface contacts to substrate and wells so bias voltages applied to reverse bias PN junctions to isolate active areas. Insulating layer is formed on top surface of substrate and interconnect channels are etched in insulating layer which do not go down to the semiconductor substrate. Contact openings for surface contacts to wells and substrate are etched in insulating layer down to semiconductor layer. Doped silicon or metal is formed in contact openings for surface contacts and to form interconnects in channels. Silicide may be formed on top of polycrystalline silicon contacts and interconnect lines to lower resistivity. Any JFET or MOS transistor may be integrated into the resulting junction isolated active area. | 11-06-2008 |
20080272407 | SEMICONDUCTOR DEVICE HAVING A FIN STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor device includes a silicon on insulator (SOI) substrate, comprising an insulation layer formed on semiconductor material, and a fin structure. The fin structure is formed of semiconductor material and extends from the SOI substrate. Additionally, the fin structure includes a source region, a drain region, a channel region, and a gate region. The source region, drain region, and the channel region are doped with a first type of impurities, and the gate region is doped with a second type of impurities. The gate region abuts the channel region along at least one boundary, and the channel region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state. | 11-06-2008 |
20080272406 | DOUBLE GATE JFET WITH REDUCED AREA CONSUMPTION AND FABRICATION METHOD THEREFOR - Double gate JFET with reduced area consumption and fabrication method therefore. Double-gate semiconductor device including a substrate having a shallow trench isolator region comprising a first STI and a second STI, a channel region having a first and second channel edges, the channel region formed in the substrate and disposed between and in contact with the first STI and the second STI at the first and second channel edge. The first STI has a first cavity at the first channel edge, and the second STI has a second cavity at the second channel edge. The device further includes a gate electrode region comprising conductive material filling at least one of the first and second cavities. At least one of the first and second cavities is physically configured to provide electrical coupling of the gate electrode region to a back-gate P-N junction. | 11-06-2008 |
20080272404 | METHOD FOR APPLYING A STRESS LAYER TO A SEMICONDUCTOR DEVICE AND DEVICE FORMED THEREFROM - A semiconductor device includes a substrate of semiconductor material. A source region, a drain region, and a conducting region of the semiconductor device are formed in the substrate and doped with a first type of impurities. The conducting region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state. A gate region is also formed in the substrate and doped with a second type of impurities. The gate region abuts a channel region of the conducting region. A stress layer is deposited on at least a portion of the conducting region. The stress layer applies a stress to the conducting region along a boundary of the conducting region that strains at least a portion of the conducting region. | 11-06-2008 |
20080272401 | Inverted Junction Field Effect Transistor and Method of Forming Thereof - A junction field effect transistor includes a substrate and a well region on the substrate. A channel region lies in the well region. A source region lies in the channel region. A drain region lies in the channel region and apart from the source region. A gate region is isolated from the source, drain, and channel regions. The gate region is in contact with a portion of the well region. | 11-06-2008 |
20080272395 | ENHANCED HOLE MOBILITY P-TYPE JFET AND FABRICATION METHOD THEREFOR - Enhanced hole mobility p-type JFET and fabrication methods. A p-type junction field effect transistor including a substrate of n-type, a source region and a drain region formed in the substrate; wherein the source region and the drain region are p-type doped and at least one of the source region and the drain region is formed with silicon-germanium compound (Si | 11-06-2008 |
20080272393 | SEMICONDUCTOR DEVICE HAVING STRAIN-INDUCING SUBSTRATE AND FABRICATION METHODS THEREOF - A semiconductor device includes a semiconductor substrate that includes a substrate layer having a first composition of semiconductor material. A source region, drain region, and a channel region are formed in the substrate, with the drain region spaced apart from the source region and the gate region abutting the channel region. The channel region includes a channel layer having a second composition of semiconductor material. Additionally, the substrate layer abuts the channel layer and applies a stress to the channel region along a boundary between the substrate layer and the channel layer. | 11-06-2008 |
20080239779 | System and Method for Detecting Multiple Matches - A system for identifying asserted signals includes a plurality of input ports, a priority encoding module, and a match module. The plurality of input ports receive one of a plurality of input signals. The priority encoding module is coupled to the plurality of input ports and outputs a signal indicating a highest-priority input signal that is asserted. The match module is also coupled to the plurality of input ports and receives a plurality of match detect signals from the priority encoding module. Each match detect signal is associated with a particular input signal and indicates whether another input signal having a higher-priority than the associated input signal is asserted. The match module also generates a multiple match signal based on the input signals and the match detect signals. The multiple match signal indicates whether more than one of the input signals is asserted. | 10-02-2008 |