QIMONDA AG Patent applications |
Patent application number | Title | Published |
20140065787 | INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE - An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode. | 03-06-2014 |
20120198265 | CIRCUIT - An embodiment of a circuit comprises an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer. | 08-02-2012 |
20120126301 | MEMORY DEVICES INCLUDING SEMICONDUCTOR PILLARS - One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column trenches. The column trenches include a pair of parallel column trenches. A first trench of the pair includes two parallel bit lines coupled to pillars adjacent to the first trench. A second trench of the pair is free of bit lines. Other methods, devices, and systems are also disclosed. | 05-24-2012 |
20120110414 | Memory-Module Controller, Memory Controller and Corresponding Memory Arrangement, and Also Method for Error Correction - A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module. | 05-03-2012 |
20120034738 | SEMICONDUCTOR PACKAGE AND METHOD OF ATTACHING SEMICONDUCTOR DIES TO SUBSTRATES - A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 Kg, the heat has a temperature range from approximately 150 to 200° C. and the pressure is applied for a range of approximately 1 to 10 seconds. | 02-09-2012 |
20110205828 | SEMICONDUCTOR MEMORY WITH MEMORY CELL PORTIONS HAVING DIFFERENT ACCESS SPEEDS - A semiconductor memory including a plurality of memory banks disposed on an integrated circuit, each memory bank including an array of memory cells, wherein a first portion of memory cells of the plurality of memory banks has a first access speed and a second portion of memory cells of the plurality of memory banks has a second access speed, wherein the first access speed is different from the second access speed. | 08-25-2011 |
20110198557 | METHOD FOR FABRICATION OF CRYSTALLINE DIODES FOR RESISTIVE MEMORIES - The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si. | 08-18-2011 |
20110185257 | SEMICONDUCTOR MEMORY HAVING NON-STANDARD FORM FACTOR - A semiconductor memory chip including error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to error encode each data word to form a corresponding coded word comprising a non-binary number of data bits including the data bits of the data word and a plurality of error correction code bits. At least one memory cell array is configured to receive and store the coded word and partitioned based on the non-binary number of bits of the coded word so as to have a non-binary number of wordlines and provide the memory chip with an aspect ratio other than a 2:1 aspect ratio. | 07-28-2011 |
20110162204 | INTEGRATED DEVICE - An integrated device is disclosed. In one embodiment, the integrated device includes a carrier substrate with a through hole and a contact sleeve. A circuit chip is provided with a contact pad above the carrier substrate. A conductive material electrically connects the contact pad to the contact sleeve. | 07-07-2011 |
20110155297 | METHOD OF APPLYING AN ADHESIVE LAYER ON THINCUT SEMICONDUCTOR CHIPS OF A SEMICONDUCTOR WAFER - The invention relates to a method for making a semiconductor. In one embodiment the method includes applying an adhesive layer to ground-thin or thinned semiconductor chips of a semiconductor wafer. In this embodiment, the adhesive layer composed of curable adhesive is introduced relatively early into a method for the thinning by grinding, separation and singulation of a semiconductor wafer to form thinned semiconductor chips, and is used further in a semiconductor device into which the thinned semiconductor chip is to be incorporated. | 06-30-2011 |
20110090616 | INTEGRATED CIRCUIT AND METHOD INCLUDING STRUCTURING A MATERIAL - A method of making an integrated circuit including structuring a material. The method includes providing an arrangement of three-dimensional bodies. The material is arranged between the bodies and structured directed radiation. The projection pattern of the three-dimensional bodies is transferred into the material. The structured material connects at least two of the three-dimensional bodies. | 04-21-2011 |
20110089392 | MEMORY USING TUNNELING FIELD EFFECT TRANSISTORS - A memory includes a first tunneling field effect transistor including a first drain and a first source, the first drain coupled to a first resistive memory element. The memory includes a second tunneling field effect transistor including a second drain and sharing the first source, the second drain coupled to a second resistive memory element. The memory includes a first region coupled to the first source for providing a source node. | 04-21-2011 |
20110080796 | INTEGRATED CIRCUIT - An integrated circuit is disclosed. One embodiment provides a sense amplifier; a first bit line; a second bit line. A first switch is configured to connect/disconnect the first bit line to/from the sense amplifier. A second switch is configured to connect/disconnect the second bit line to/from the sense amplifier independently from the first switch. | 04-07-2011 |
20110057699 | INTEGRATED CIRCUIT AND PROGRAMMABLE DELAY - Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be delayed. The delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path including any of the delay cells arranged downstream of the starting point. The first output of the last delay cell in the chain forms an output of the programmable delay element. | 03-10-2011 |
20110034045 | Stacking Technique for Circuit Devices - Stackable circuit devices include mechanical and electrical connection elements that are optionally disengageable and disconnectable. The mechanical connection elements comprise pairs of complementary male and female plug-in engagement elements respectively arranged at opposite matching positions on top and bottom faces of each device package. The male and female plug-in engagement elements provide a mutual plug-in engagement. The electrical connection elements comprise a plurality of first and second complementary contact elements respectively arranged in opposite and matching positions on either the top or bottom face of each device package. When the circuit devices are stacked, the first contact elements are respectively configured to provide an electrical connection to a complementary matching second contact element of an adjacently plugged in circuit device. Some of the stackable circuit devices may accommodate an integrated memory die or chip and others of the stackable circuit devices may include line routing and distribution blocks. | 02-10-2011 |
20100293350 | METHOD OF OPERATING AN INTEGRATED CIRCUIT, INTEGRATED CIRCUIT AND MEMORY MODULE - According to one embodiment of the present invention, a method of operating an integrated circuit including a plurality of resistance changing memory cells grouped into physical memory units is provided. The method includes: Monitoring writing access numbers assigned to the physical memory units, each writing access number reflecting the number of writing accesses to the physical memory unit to which the writing access number is assigned; if the value of a writing access number assigned to a first physical memory unit exceeds a writing access threshold value, a data exchange process is carried out during which the data content stored within the first physical memory unit is exchanged with the data content of a second physical memory unit having a writing access number of a lower value. | 11-18-2010 |
20100123202 | INTEGRATED CIRCUIT WITH STACKED DEVICES - An integrated circuit with stacked devices. One embodiment provides a surface of a first semiconductor structure of a first crystalline semiconductor material including first and second portions. First structures are formed on the first portions. The second portions remain uncovered. Sacrificial structures of a second, different crystalline material are formed on the second portions. A second semiconductor structure of the first crystalline semiconductor material is formed over the sacrificial structures and over the first structures. | 05-20-2010 |
20100110753 | Ferroelectric Memory Cell Arrays and Method of Operating the Same - An integrated circuit includes a plurality of switching devices, wherein each device includes a gate dielectric capable of assuming at least a first and a second polarization state. The integrated circuit further includes an address circuit configured to control bit lines electrically coupled to first load regions of a load path of the switching devices and a word line electrically coupled to gate electrodes of the switching devices. The address circuit is configured to control a write cycle such that a first voltage is induced at the gate dielectrics of selected ones of the switching devices and a second voltage is induced at the gate dielectrics of non-selected ones of the switching devices. The first voltage suffices to switch the gate dielectrics of the selected devices from the first to the second polarization state and the second voltage does not suffice to switch the gate dielectrics of the non-selected devices. | 05-06-2010 |
20100097835 | 4 F2 MEMORY CELL ARRAY - An integrated circuit including a memory cell array comprises active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being arranged at a bitline pitch, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, the wordlines being arranged at a wordline pitch, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines, and the bitline pitch is different from the wordline pitch. | 04-22-2010 |
20100096669 | MEMORY CELL ARRAY COMPRISING WIGGLED BIT LINES - An integrated circuit including a memory cell array comprises transistors being arranged along parallel active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines. | 04-22-2010 |
20100090285 | Integrated Circuit with a Contact Structure Including a Portion Arranged in a Cavity of a Semiconductor Structure - An integrated circuit includes a contact structure with a buried first and a protruding second portion. The buried first portion is arranged in a cavity formed in a semiconductor structure and is in direct contact with the semiconductor structure. The protruding second portion is arranged above the main surface of the semiconductor structure and in direct contact with a conductive structure that is spaced apart from or separated from the main surface of the semiconductor structure. An insulator structure is arranged below and in direct contact with the contact structure. | 04-15-2010 |
20100090264 | INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES - One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed. | 04-15-2010 |
20100090263 | MEMORY DEVICES INCLUDING SEMICONDUCTOR PILLARS - One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column trenches. The column trenches include a pair of parallel column trenches. A first trench of the pair includes two parallel bit lines coupled to pillars adjacent to the first trench. A second trench of the pair is free of bit lines. Other methods, devices, and systems are also disclosed. | 04-15-2010 |
20100079246 | INTEGRATED CIRCUIT WITH A RECTIFIER ELEMENT - An integrated circuit with a rectifier element. One embodiment provides a signal source, an electronic circuit and a rectifier element with a copper layer and a cuprous oxide layer adjacent to and in direct contact with the copper layer. The signal source is configured to drive a signal on a signal output terminal that is electrically coupled to the copper layer. The electronic circuit is electrically coupled to the cuprous oxide layer. The rectifier element may be formed between wiring layers of an integrated circuit. | 04-01-2010 |
20100078711 | METHOD OF MANUFACTURING INTEGRATED CIRCUITS INCLUDING A FET WITH A GATE SPACER - A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides. | 04-01-2010 |
20100078681 | Integrated Circuit Including a Hetero-Interface and Self Adjusted Diffusion Method for Manufacturing the Same - An integrated circuit including a hetero-interface and a manufacturing method thereof is disclosed. One embodiment includes forming a hetero-structure including a hetero-interface at a junction between a first region and a second region, and, thereafter introducing a material into the first region and at least up to the hetero-interface, wherein a diffusion constant of the material is higher in the first region than in the second region. | 04-01-2010 |
20100064274 | PROXIMITY CORRECTION METHOD AND SYSTEM - A proximity correction method includes creating a first proximity correction model having a focus value and creating a second proximity correction model having a first defocus value. One of the first or second proximity correction models are associated with corresponding first and second layout areas of a semiconductor wafer. | 03-11-2010 |
20100061140 | INTEGRATED CIRCUIT INCLUDING DOPED SEMICONDUCTOR LINE HAVING CONDUCTIVE CLADDING - An integrated circuit includes an array of memory cells. Each memory cell includes a diode. The integrated circuit includes a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of diodes. The integrated circuit includes conductive cladding contacting the doped semiconductor line. | 03-11-2010 |
20100058018 | Memory Scheduler for Managing Internal Memory Operations - An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller. | 03-04-2010 |
20100057685 | INFORMATION STORAGE AND RETRIEVAL SYSTEM - An information storage and retrieval system includes a first data structure and a second data structure. The first data structure is configured to store documents. Each document includes a plurality of data portions. The second data structure is configured to store addresses to each document and data portion stored in the first data structure at addresses defined by an identity of each data portion. | 03-04-2010 |
20100054022 | Method and Apparatus for Reducing Charge Trapping in High-K Dielectric Material - In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state. | 03-04-2010 |
20100054021 | Memory Device with Multiple Capacitor Types - An integrated circuit includes a memory array portion and a support circuitry portion arranged on a semiconductor substrate. An insulative layer is formed on the semiconductor substrate. Data storage capacitors are located in the memory array portion and extending through the insulative layer. Non-data storage capacitors are located in the support circuitry portion and terminating above the insulative layer. | 03-04-2010 |
20100052191 | Metrology Mark with Elements Arranged in a Matrix, Method of Manufacturing Same and Alignment Method - A method of manufacturing an integrated circuit provides a metrology mark (e.g., alignment mark or overlay mark). The method includes forming a first plurality of first structures arranged in a matrix in a substrate. Portions of the matrix are covered with a mask such that first portions of the matrix are left exposed and second portions of the matrix are covered. Signal response properties of exposed ones of the first structures in the matrix are altered to form a metrology mark. The metrology mark includes first and second mark portions with different signal response properties and which are aligned to a virtual grid. The evaluation of precisely positioned metrology marks may be improved with low impact on process complexity. | 03-04-2010 |
20100051190 | METHOD FOR APPLYING AN ADHESIVE LAYER ON THIN CUT SEMICONDUCTOR CHIPS OF SEMICONDUCTOR WAFERS - The invention relates to a method for applying an adhesive layer to ground-thin or thinned semiconductor chips of a semiconductor wafer. In this case, the adhesive layer, with the aid of an adhesive film which is entirely composed of precurable adhesive, is introduced relatively early into a method for the thinning by grinding, separation and singulation of a semiconductor wafer to form thinned semiconductor chips, and is finally used further in the semiconductor device into which the thinned semiconductor chip is to be incorporated. | 03-04-2010 |
20100045351 | INTEGRATED CIRCUIT AND PROGRAMMABLE DELAY - Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be delayed. The delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path including any of the delay cells arranged downstream of the starting point. The first output of the last delay cell in the chain forms an output of the programmable delay element. | 02-25-2010 |
20100044669 | INTEGRATED CIRCUIT INCLUDING MEMORY CELL HAVING CUP-SHAPED ELECTRODE INTERFACE - An integrated circuit includes a first electrode and a cup-shaped electrode interface coupled to the first electrode. The integrated circuit includes a dielectric spacer at least partially laterally enclosed by the electrode interface and a resistance changing material laterally enclosed by the spacer and contacting the electrode interface. The integrated circuit includes a second electrode coupled to the resistance changing material. | 02-25-2010 |
20100040983 | Compensation of Process-Induced Displacement - A method of manufacturing integrated circuits includes determining a process-induced displacement (e.g., a stress-induced displacement) between primary structures on a substrate and providing a photomask with mask features assigned to the primary structures. The distances between the mask features are set such that the process-induced displacement is compensated. | 02-18-2010 |
20100032635 | ARRAY OF LOW RESISTIVE VERTICAL DIODES AND METHOD OF PRODUCTION - An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench. | 02-11-2010 |
20100027325 | INTEGRATED CIRCUIT INCLUDING AN ARRAY OF MEMORY CELLS AND METHOD - An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line. | 02-04-2010 |
20100027311 | INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT - An integrated circuit and a method of forming an integrated circuit. One embodiment includes a conductive line formed above a surface of a carrier. A slope of the sidewalls of the conductive line in a direction perpendicular to the surface of the carrier reveals a discontinuity and a width of the conductive line in an upper portion thereof is larger than the corresponding width in the lower portion. | 02-04-2010 |
20100025826 | Field Effect Transistors with Channels Oriented to Different Crystal Planes - An integrated circuit includes a first field effect transistor of a first carrier type and a second field effect transistor of a second, different carrier type. In a conductive state, a first channel of the first field effect transistor is oriented to one of a first set of equivalent crystal planes of a semiconductor substrate and a second channel of the second field effect transistor is oriented to at least one of a second, different set of equivalent crystal planes. The first set of equivalent crystal planes is parallel to a main surface of the semiconductor substrate and the second set of equivalent crystal planes is perpendicular to the main surface. | 02-04-2010 |
20100013005 | INTEGRATED CIRCUIT INCLUDING A VERTICAL TRANSISTOR AND METHOD - An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration. | 01-21-2010 |
20100009270 | METHOD FOR OPTIMIZING THE LAYOUT OF AT LEAST ONE TRANSFER DEVICE FOR PRODUCTION OF A DIRECT OR INDIRECT STRUCTURE - Embodiments of the invention include a method for generating a model layout for the manufacturing of a transfer device, the method including:
| 01-14-2010 |
20100006953 | INTEGRATED CIRCUIT INCLUDING A DIELECTRIC LAYER - An integrated circuit including a dielectric layer and a method for manufacturing. One embodiment provides a substrate having a first side and a second side and at least one dielectric layer. The dielectric layer includes a zirconium oxide and at least one dopant selected from the group consisting of hafnium and titanium and having a first side and a second side. The first side of the dielectric layer is arranged at least on a subarea of the first side of the semiconductor substrate. | 01-14-2010 |
20100002498 | INTEGRATED CIRCUIT FOR PROGRAMMING A MEMORY CELL - An integrated circuit includes an array of resistance changing memory cells. The array includes a first portion. The integrated circuit includes a circuit configured to apply a set pulse having a first pulse width to a first memory cell in the first portion to set the first memory cell. The first pulse width is based on a predetermined error percentage for the first portion. | 01-07-2010 |
20100001402 | Multiple Patterning Method - A self-aligned pitch fragmentation method for manufacturing an integrated circuit includes forming openings in a first layer, wherein the openings uncover first sections of a second layer arranged below the first layer. The first sections of the second layer are removed. The first layer is shrunk and the openings are expanded to form a first mask from the first layer, wherein the first mask exposes second sections and covers third sections of the second layer. The etch properties of the second sections are altered selectively to the third sections to facilitate the self-aligned pitch fragmentation method. | 01-07-2010 |
20090323411 | METHOD INCLUDING SELECTIVE TREATMENT OF STORAGE LAYER - Method including selective treatment of storage layer. One embodiment includes the formation of a material layer on a topology with protruding portions, which may be assigned to active areas, and with recessed portions, which may be assigned to isolation structures. A mask material is deposited that grows selectively above the protruding portions and that forms a mask which covers first portions of the material layer wrapping around at least portions of the protruding portions. Openings in the mask are formed above second portions of the material layer above the recessed portions. Then the material layer is treated in the second portions in a self-aligned manner. | 12-31-2009 |
20090322319 | MAGNETORESISTIVE SENSOR WITH TUNNEL BARRIER AND METHOD - Magnetoresistive sensors with tunnel barrier and method. One embodiment provides a magnetoresistive sensor having a magnetic tunnel junction is provided. The magnetic tunnel junction includes a barrier layer. The barrier layer includes carbon, pyrolytic carbon, or graphene, or graphite. | 12-31-2009 |
20090321860 | INTEGRATED CIRCUIT HAVING A MAGNETIC TUNNEL JUNCTION DEVICE AND METHOD - An integrated circuit having a magnetic tunnel junction and method. One embodiment provides an integrated circuit having a magnetic tunnel junction is provided. The magnetic tunnel junction includes a barrier layer. The barrier layer includes carbon, pyrolytic carbon, or graphene, or graphite. | 12-31-2009 |
20090321805 | INSULATOR MATERIAL OVER BURIED CONDUCTIVE LINE - One embodiment relates to an integrated circuit that includes a conductive line that is arranged in a groove in a semiconductor body. An insulating material is disposed over the conductive line. This insulating material includes a first insulating layer comprising a horizontal portion, and a second insulating layer that is disposed over the first insulating layer. Other methods, devices, and systems are also disclosed. | 12-31-2009 |
20090321706 | Resistive Memory Devices with Improved Resistive Changing Elements - An integrated circuit includes a memory cell with a resistance changing memory element. The resistance changing memory element includes a first electrode, a second electrode, and a resistivity changing material disposed between the first and second electrodes, where the resistivity changing material is configured to change resistive states in response to application of a voltage or current to the first and second electrodes. In addition, at least one of the first electrode and the second electrode comprises an insulator material including a self-assembled electrically conductive element formed within the insulator material. The self-assembled electrically conductive element formed within the insulator material remains stable throughout the operation of switching the resistivity changing material to different resistive states. | 12-31-2009 |
20090310401 | INTEGRATED CIRCUIT INCLUDING A MEMORY ELEMENT PROGRAMMED USING A SEED PULSE - An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element to a crystalline state from an amorphous state by applying a seed pulse to the memory element followed by a set pulse. | 12-17-2009 |
20090307417 | INTEGRATED BUFFER DEVICE - An integrated buffer device. One embodiment provides a receiving unit and a logic unit to control the operation of the buffer device based on a setting signal. | 12-10-2009 |
20090303780 | INTEGRATED CIRCUIT INCLUDING AN ARRAY OF DIODES COUPLED TO A LAYER OF RESISTANCE CHANGING MATERIAL - An integrated circuit includes an array of diodes and an electrode coupled to each diode. The integrated circuit includes a layer of resistance changing material coupled to the electrodes and bit lines coupled to the layer of resistance changing material. The layer of resistance changing material provides a resistance changing element at each intersection of each electrode and each bit line. | 12-10-2009 |
20090302392 | INTEGRATED CIRCUIT INCLUDING A BURIED WIRING LINE - Integrated circuits including a buried wiring lien. One embodiment provides a field effect transistor including a first active area and a gate electrode buried below a main surface of a semiconductor substrate. A gate wiring line may be buried below the main surface and a section of the gate wiring line may form the gate electrode. Above the gate wiring line, a buried contact structure is formed that is adjacent to and in direct contact with the first or a second active area. | 12-10-2009 |
20090302380 | Word Line to Bit Line Spacing Method and Apparatus - In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line. | 12-10-2009 |
20090296473 | Method of Forming an Integrated Circuit with NAND Flash Array Segments and Intra Array Multiplexers and Corresponding Integrated Circuit with NAND Flash Array Segments and Intra Array Multiplexers - The present invention provides an integrated circuit including N1 NAND flash array segments with N2 local bit lines, N1 intra array multiplexers and N2/2 global bit lines. Further, the present invention provides a method of producing an integrated circuit including N1 NAND flash array segments with N2 local bit lines, N1 intra array multiplexers and N2/2 global bit lines. | 12-03-2009 |
20090295443 | System and Method For Modifying Signal Characteristics - The present invention embodiments provide a system to modify signal characteristics to produce a desired signal. The system comprises a signal module to modify signal characteristics. The signal module includes at least one input to receive an input signal including a substantially rectangular signal and one or more control signals and an output to provide a substantially trapezoidal signal. A signal unit of the signal module adjusts characteristics of the substantially rectangular signal including leading and/or trailing edges of that signal in accordance with the one or more control signals to produce the substantially trapezoidal signal. The present invention embodiments further include a probe card and method to adjust signal characteristics as described above. | 12-03-2009 |
20090294895 | INTEGRATED CIRCUIT WITH CONDUCTIVE STRUCTURES - An integrated circuit includes an array of transistors and wordlines, where individual wordlines are coupled to a number of the transistors. Conductive structures that are insulated from the wordlines are disposed in a layer beneath the wordlines and are arranged between the transistors. | 12-03-2009 |
20090289288 | INTEGRATED CIRCUIT INCLUDING AN INSULATING STRUCTURE BELOW A SOURCE/DRAIN REGION AND METHOD - An integrated circuit including an insulating structure below a source/drain region and a method. One embodiment includes a memory cell with an access transistor and a storage element. A first source/drain region of the access transistor is electrically coupled to the storage element. A first insulating structure is disposed between the first source/drain region and a first portion of a semiconductor substrate, the first portion being arranged below the first source/drain region. A channel region of the access transistor is formed between the first and a second source/drain region of the access transistor in an active area being electrically coupled to the first portion of the semiconductor substrate. | 11-26-2009 |
20090285014 | INTEGRATED CIRCUIT AND METHOD FOR SWITCHING A RESISTIVELY SWITCHING MEMORY CELL - An integrated circuit and method for switching a resistively switching memory cell. One embodiment provides an initial pulse and at least one escalated pulse in case the memory cell did not switch. | 11-19-2009 |
20090273967 | METHOD AND INTEGRATED CIRCUIT FOR DETERMINING THE STATE OF A RESISTIVITY CHANGING MEMORY CELL - A method and an integrated circuit for determining the state of a resistivity changing memory cell. In one embodiment the method includes detecting a first resistance of the resistivity changing memory cell, determining whether the first resistance value is smaller than a predetermined threshold value thereby determining a first result value, initializing the resistivity changing memory cell into one of at least four resistivity changing memory states, detecting a second resistance value of the resistivity changing memory cell, determining whether the second resistance value is smaller than the predetermined threshold value determining a second result value, and determining the state of the resistivity changing memory cell state using the first and the second result values. | 11-05-2009 |
20090273773 | Measurement Method for Determining Dimensions of Features Resulting from Enhanced Patterning Methods - A method includes measuring spectral responses of at least first and second sections of a measurement mark. In the first section, individual ones of primary lines of a first width are arranged at a first pitch and in alternating order with secondary lines spaced from the primary lines at a first distance. In the second section, individual ones of further primary lines of a second, different width are arranged at the first pitch and in alternating order with further secondary lines that are spaced from the further primary lines at the first distance. From at least the first and second spectra, information on a difference between target and actual widths of the primary and secondary lines may be obtained. | 11-05-2009 |
20090268532 | Systems and Methods for Writing to a Memory - An integrated circuit includes memory segments, each having at least one memory cell configurable in first and second states to store data, and a controller that controls programming and erasing of the memory segments. The controller maps external memory addresses of write data to internal memory addresses of erased memory segments with no memory cells in the first state such that erased memory segments are programmed with write data. When a write access occurs for an external memory address previously mapped to an internal memory address of a programmed memory segment with at least one memory cell in the first state, the controller remaps the external memory address to another internal memory address of an erased memory segment. The controller identifies programmed memory segments to be erased and controls selective erasure of the identified programmed memory segments, such as programmed memory segments no longer mapped to an external memory address. | 10-29-2009 |
20090267678 | Integrated Circuit with Improved Data Rate - An integrated circuit includes: a terminal for outputting data, a driver for providing the data to the terminal, and a switch for selectively connecting/disconnecting the driver to the terminal. The disconnection of the driver reduces the capacitive load on the connection between the terminal and driver, thus reducing limitations on data rate from factors such as data reflections that reduce signal quality. Selective connection/disconnection allows the driver to be reconnected to the terminal only when needed. | 10-29-2009 |
20090267640 | SYSTEM INCLUDING PREEMPHASIS DRIVER CIRCUIT AND METHOD - A system including a preemphasis driver circuit and a method. One embodiment includes an output terminal, a main driver coupled between the input terminal and the output terminal and an auxiliary driver coupled to the output terminal, wherein at least one unclocked delay element is coupled between the input terminal and the auxiliary driver. | 10-29-2009 |
20090267084 | Integrated circuit with wireless connection - An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device. | 10-29-2009 |
20090261411 | INTEGRATED CIRCUIT INCLUDING A BODY TRANSISTOR AND METHOD - An integrated circuit including a floating body transistor and method. One embodiment provides a transistor including a body region formed in a first portion and a first and a second source/drain region formed in a second and a third portion. The body region is formed in a semiconductor substrate. The integrated circuit further includes a buried structure disposed at least below the body region and a first and a second insulating structure including an insulating material and being disposed at least between the body region and regions of the second and the third portion below the first and the second source drain region, wherein the first and the second insulating structure contact the buried structure. | 10-22-2009 |
20090261397 | Integrated Circuit with Floating-Gate Electrodes Including a Transition Metal and Corresponding Manufacturing Method - An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described. | 10-22-2009 |
20090261395 | Integrated Circuit Including a Ferroelectric Memory Cell and Method of Manufacturing the Same - A method for manufacturing an integrated circuit including a ferroelectric memory cell is disclosed. One embodiment of the method includes: forming a amorphous oxide layer over a carrier, the amorphous layer including: O and any of the group of: Hf, Zr and (Hf,Zr), forming a covering layer on the amorphous layer, and heating the amorphous layer up to a temperature above its crystallization temperature to at least partly alter its crystal state from amorphous to crystalline, resulting in a crystallized oxide layer. | 10-22-2009 |
20090261312 | INTEGRATED CIRCUIT INCLUDING AN ARRAY OF LOW RESISTIVE VERTICAL DIODES AND METHOD - An integrated circuit including an array of low resistive vertical diodes and method. One embodiment provides an array of diodes at least partially formed in a substrate for selecting one of a plurality of memory cells. A diode is coupled to a word line. The word line includes a straight-lined portion and protrusions. The diode includes an active area located between two adjacent protrusions. | 10-22-2009 |
20090251857 | SYSTEM INCLUDING AN ELECTRONIC MODULE WITH A HEAT SPREADER - A system including an electronic module with a heat spreader. One embodiment provides a plate including a thermally conductive material and a guiding member arranged along an edge of the plate. The plate and the guiding member of the heat spreader are configured to form, when attached to a first memory module, together with another heat spreader attached to a second memory module or together with a wall of another device, a duct channeling a flow of a coolant. | 10-08-2009 |
20090242955 | Integrated Circuit, Memory Device and Methods of Manufacturing the Same - An integrated circuit includes: a contact structure with a first stack of at least two conductive layers, and a gate electrode with a second stack of conductive layers, the second stack of layers having the same sequence of conductive layers as the first stack. | 10-01-2009 |
20090242952 | INTEGRATED CIRCUIT INCLUDING A CAPACITOR AND METHOD - An integrated circuit including a capacitor and a method of fabricating an integrated circuit. The capacitor has a first electrode. A plurality of conductive lines is separated from each other and is configured to be held at a potential being the same for all conductive lines. A second electrode encloses individual ones of the conductive lines at a top side and at least one lateral side and is separated from the first electrode by a dielectric layer. The second electrode includes a polycrystalline semiconductor material, a metal or a metal-semiconductor compound. | 10-01-2009 |
20090242865 | MEMORY ARRAY WITH DIODE DRIVER AND METHOD FOR FABRICATING THE SAME - A method of fabricating a memory array. The method begins with a structure, generally composed of dielectric fill material and having conductive lines formed at its lower portion, and a sacrificial layer formed on its upper surface. Diodes are formed in the fill material, each diode having a lightly-doped first layer of the same conductivity type as the conductive lines; a heavily doped second layer of opposite conductivity type; and a conductive cap. Self-aligned vias are formed over the diodes. Self-aligned, and self-centered spacers in the self-aligned vias define pores that expose the conductive cap. Memory material is deposited within the pores, the memory material making contact with the conductive cap. A top electrode is formed in contact with the memory material. | 10-01-2009 |
20090237983 | INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT DOPED WITH DIELECTRIC MATERIAL - An integrated circuit includes a first electrode, a second electrode, and a damascene structured memory element coupled to the first electrode and the second electrode. The memory element has a height and a width. The height is greater than or equal to the width. The memory element includes resistance changing material doped with dielectric material. | 09-24-2009 |
20090236658 | ARRAY OF VERTICAL TRIGATE TRANSISTORS AND METHOD OF PRODUCTION - An array of vertical trigate transistors and method of production are disclosed. One embodiment provides an array of selection transistors for selecting one of a plurality of memory cells. A selection transistor is a vertical trigate transistor. | 09-24-2009 |
20090222779 | METHODS AND APPARATUSES FOR GENERATING A RANDOM SEQUENCE OF COMMANDS FOR A SEMICONDUCTOR DEVICE - Methods and apparatuses for generating a random sequence of commands for a semiconductor device. The method generates random state transitions within a finite state machine model of the semiconductor device. A sequence of commands is determined which are associated to the generated random state transitions based on the finite state machine model of the semiconductor device. | 09-03-2009 |
20090219032 | SYSTEM AND METHOD FOR DETERMINING CIRCUIT FUNCTIONALITY UNDER VARYING EXTERNAL OPERATING CONDITIONS - A system and method for determining circuit functionality under varying external operating conditions. One embodiment provides a circuit for a given input signal. Internal signals are generated at internal nodes for the given input signal and the next set of external operating conditions. The internal signals are compared with internal reference signals to determine whether the integrated circuit is functional under the next set of external operating conditions. If the circuit is found functional under the next set of external operating conditions, then the internal reference signals are set equal to the internal signals, the initial set of external operating conditions are set equal to the next set of external operating conditions, and the above described method is repeated. | 09-03-2009 |
20090213830 | COMMUNICATION SYSTEM - A communication system is disclosed. In one embodiment, the communication system includes a communication device set up to execute a process, configured to put itself into an activated state or into a deactivated state at alternate times, receive time information in a first operating state of the activated state, take the received time information as a basis for ascertaining the later time at which useful information is transmitted to the communication device, receive the useful information at the later time in a second operating state of the activated state. Individual components of the communication device are able to be put into an activated state or into a deactivated state independently of one another. | 08-27-2009 |
20090206461 | INTEGRATED CIRCUIT AND METHOD - An integrated circuit and method of fabricating an integrated circuit. One embodiment includes a circuit chip, a contact pad, and a projecting top contact. A signal line couples the contact pad to the projecting top contact, the contact pad, the projecting top contact. The signal line is arranged on a top face of the circuit chip. A substrate and a lower contact pad, the lower contact pad is arranged on a bottom face of the substrate and the circuit chip is arranged on a top face of the substrate. A bottom face of the circuit chip is facing the top face of the substrate. A connection couples the contact pad on the circuit chip to the lower contact pad. | 08-20-2009 |
20090206316 | INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE - An integrated circuit includes a U-shaped access device and a first line coupled to a first side of the access device. The integrated circuit includes a contact coupled to a second side of the access device and self-aligned dielectric material isolating the first line from the contact. | 08-20-2009 |
20090206315 | INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE - An integrated circuit includes a first contact, a second contact, and a U-shaped access device coupled to the first contact and the second contact. The integrated circuit includes self-aligned dielectric material isolating the first contact from the second contact. | 08-20-2009 |
20090201740 | INTEGRATED CIRCUIT, METHOD TO PROGRAM A MEMORY CELL ARRAY OF AN INTEGRATED CIRCUIT, AND MEMORY MODULE - An integrated circuit having a memory cell arrangement with a plurality of memory cells and a memory cell arrangement controller is provided. The memory cell arrangement controller is configured such that during programming of at least one memory cell of the plurality of memory cells, at least one memory cell, which is arranged adjacent to the memory cell to be programmed, is driven to shield the memory cell to be programmed. | 08-13-2009 |
20090200534 | METHOD FOR FABRICATION OF POLYCRYSTALLINE DIODES FOR RESISTIVE MEMORIES - The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si. | 08-13-2009 |
20090196093 | STACKED DIE MEMORY - A memory includes a first die including a first array of phase change memory cells and a second die including a second array of phase change memory cells. The second die is stacked above the first die. The memory includes lines configured to access the first die and the second die. The first die and the second die are enclosed in a single package. | 08-06-2009 |
20090184429 | Integrated Circuit Comprising Conductive Lines and Contact Structures and Method of Manufacturing an Integrated Circuit - An integrated circuit comprises a first conductive lines and second lines as well as contact structures being in contact with the first and second conductive lines. The first conductive lines are arranged in a first metallization level, and second conductive lines are arranged in a second metallization level arranged above the first metallization level. The second conductive lines are arranged above the contact structures, and a pitch of neighboring contact structures is equal to a pitch of neighboring second conductive lines. The distance between neighboring contact structures is smaller than 100 nm. | 07-23-2009 |
20090184357 | SOI BASED INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING - A SOI based integrated circuit and method for manufacturing a SOI based integrated circuit is disclosed. One embodiment provides an integrated circuit having a silicon-on-insulator carrier including a substrate, a buried insulating layer on the substrate and a semiconductor layer on the buried insulating layer. A trench extends at least through the semiconductor layer and into the buried insulating layer. A conductive region is formed in the buried insulating layer, wherein the conductive region partly surrounds the trench and is configured to interconnect the semiconductor layer and the substrate. | 07-23-2009 |
20090183051 | Memory System with Cyclic Redundancy Check - A memory system, with a memory controller and a memory module, is configured to transfer error securing data and address signals within signal frames between the memory controller and the memory module. The memory system includes: an address register configured to pre-store an address signal associated with at least one block of data signals to be transferred, and at least one cyclic redundancy checksum calculator included in one of the memory controller and the memory module, the calculators being configured to calculate a cyclic redundancy checksum for the at least one data signal block, wherein the pre-stored address signal is used as an initial value for the calculation of the cyclic redundancy checksum and the at least one block of data and address signals are transferred together with the calculated cyclic redundancy checksum. | 07-16-2009 |
20090179262 | Floating Body Memory Cell with a Non-Overlapping Gate Electrode - An integrated circuit includes a memory cell with a transistor. The transistor includes first and second doped portions, and a third portion disposed between the first and second doped portions. The first and the second doped portions and the third portion are disposed in a semiconductor substrate. The transistor further includes a gate electrode adjacent to the third portion, the gate electrode being insulated from the third portion. The gate electrode does not overlap at least one of the first and second doped portions, and a line connecting the first and the second portions extends substantially perpendicular to a surface of the substrate. | 07-16-2009 |
20090175016 | CLIP FOR ATTACHING PANELS - Clip for attaching two outer panels to an intermediate panel, the clip comprising two arm portions each arm portion being configured to apply pressure to one of the outer panels in order to force the panel against a surface of the intermediate panel, and a bridge portion connecting the two arm portions, the bridge portion comprising a central section configured to provide mechanical coupling to the intermediate panel. | 07-09-2009 |
20090173984 | INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - The present invention provides an integrated circuit with a floating body transistor comprising two source/drain regions and a floating body region arranged between the two source/drain regions comprising: a back gate electrode separated from the floating body by a first dielectric layer; a control gate electrode, separated from the floating body by a second dielectric layer and overlying the back gate electrode; and a third dielectric layer arranged between the back gate electrode and the control gate electrode. The present invention provides also a method of manufacturing an integrated circuit and a method of operating an integrated circuit. | 07-09-2009 |
20090173138 | SYSTEM AND METHOD FOR CHECKING ELECTRICAL CONTACT POINTS OF SEMICONDUCTOR DEVICES - A system and method for checking electrical contact points of semiconductor devices. One embodiment includes a check system and a method in which, for the checking of electrical contact points of semiconductor devices, a system is provided by which a number of contact points are impacted with a mechanical load. | 07-09-2009 |
20090161460 | RETENTION TEST SYSTEM AND METHOD FOR RESISTIVELY SWITCHING MEMORY DEVICES - A retention test system and method for resistively switching memory devices is disclosed. One embodiment provides a plurality of memory cells configured to be changed over between a first state of high electrical resistance and a second state of low electrical resistance, wherein the system is configured to apply a bias voltage to at least one memory cell of the memory device to be tested. | 06-25-2009 |
20090161416 | OPTIMIZED PHASE CHANGE WRITE METHOD - A system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC), and a design structure including the IC embodied in a machine readable medium are disclosed. The system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM. A column line (bit line) is pre-charged to a single predetermined level prior to enabling current flow to a corresponding selected phase change element. A current flow in the phase change element with a row (word line) is initiated once the column (bit line) has been pre-charged, to write data to the PCRAM cell. The current flow is terminated in the phase change element by closing the column line (bit line) preferably by quenching. | 06-25-2009 |
20090161415 | INTEGRATED CIRCUIT FOR SETTING A MEMORY CELL BASED ON A RESET CURRENT DISTRIBUTION - An integrated circuit includes an array of resistance changing memory cells and a first circuit. The first circuit is configured to set a selected memory cell to a crystalline state by applying a decreasing stair step pulse to the selected memory cell. The pulse is based on a reset current distribution for the array of memory cells. | 06-25-2009 |
20090158999 | Manufacturing method for an integrated circuit comprising a multi-layer stack, corresponding integrated circuit and multi-layer mask - The present invention provides a manufacturing method for an integrated circuit comprising a multi-layer stack and a corresponding integrated circuit. In the method a first layer is deposited on a substrate in a plasma deposition process in a plasma chamber using a first reaction gas having at least one first gas component which is introduced at a first flow rate into the chamber. Thereafter a second layer is deposited in situ on the first layer in the plasma deposition process in the plasma chamber using a second reaction gas having at least one second gas component which is introduced at a second flow rate into the chamber. In a switching transition period from the first to the second flow rate a transition layer including a gradual composition transition from the first to the second layer is formed. | 06-25-2009 |
20090158010 | Command Protocol for Integrated Circuits - A method of operating an integrated circuit involves supplying an instruction portion of a command to the integrated circuit to specify an operation to be performed by the integrated circuit. At least some types of commands also include an attributes portion that provides additional information about the operation to be performed. The attributes portion of the command is supplied to the integrated circuit with a delay relative to the instruction portion of the command. The integrated circuit selectively enables circuitry for processing the attributes portion if the integrated circuit determines from the received instruction portion that the command also includes an attributes portion. The delay between the two portions of the command provides sufficient time for the integrated circuit to enable the attributes processing circuitry, which, in a default state, can be disabled during an active mode of the integrated circuit to save power. | 06-18-2009 |
20090150837 | CHECKING A CIRCUIT LAYOUT FOR A SEMICONDUCTOR APPARATUS - Method for checking a circuit layout for a semiconductor apparatus, including:
| 06-11-2009 |
20090144583 | Memory Circuit - The invention provides a memory circuit comprising a plurality of storage cells for storing data and redundant spare storage cells for replacing defective storage cells, and a memory access logic for accessing said storage cells connected to a replacement setting register which is writeable during operation of said memory circuit to store replacement settings. | 06-04-2009 |
20090142916 | APPARATUS AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - On aspect is a method to manufacture an integrated circuit including a reshaping process of the wafer edge region and an apparatus to perform the reshaping process. | 06-04-2009 |
20090141843 | Method and Apparatus for Determining a Skew - The invention provides a method and an apparatus for determining a skew of each data bit of an encoded data word received by a receiver via an interface from a transmitter comprising the steps of performing an error check and correction of the received and sampled encoded data word to calculate an error corrected encoded data word corresponding to the encoded data word transmitted by the transmitter, and correlating a sequence of error corrected encoded data words with the sampled encoded data words to determine a skew of each data bit of said received encoded data words. | 06-04-2009 |
20090129145 | Memory Cell Array Comprising Floating Body Memory Cells - A memory cell array includes a plurality of floating body memory cells, which are arranged in cell rows, and world lines, wherein each word line is configured to control memory cells associated with a pair of cell rows. The memory cell array also includes bitlines, wherein each bitline is electrically connected to an individual memory cell of each pair of the cell rows. | 05-21-2009 |
20090129029 | METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT - A method for manufacturing an integrated circuit is disclosed. One embodiment provides placing an elastic, anisotropically conductive material on top of a printed circuit board. An electronic component is placed over the elastic, anisotropically conductive material, fixing the electronic component on the printed circuit board. | 05-21-2009 |
20090127586 | INTEGRATED CIRCUIT HAVING MEMORY CELLS AND METHOD OF MANUFACTURE - An integrated circuit having memory cells and a method of manufacture is disclosed. One embodiment provides a switching active volume and a selection transistor coupled in series between a first electrode and a second electrode. The selection transistor is a vertical transistor for at least partially guiding a substantially vertical current flow. The second electrode includes a buried diffused ground plate formed in a substrate. A metal-containing region at least partially contacting the buried diffused ground plate is provided, the metal-containing region at least extending below the selection transistor. | 05-21-2009 |
20090125984 | SYSTEM AND METHOD FOR ESTABLISHING DATA CONNECTIONS BETWEEN ELECTRONIC DEVICES - A system and method is disclosed, including establishing of data connections between electronic devices. One embodiment provides a method for establishing a data connection between a first and a second electronic device, wherein establishing the data connection is authorized by executing at least one action with at least one physical tool. | 05-14-2009 |
20090122628 | DEVICE WITH PRECHARGE/HOMOGENIZE CIRCUIT - A device with a precharge/homogenize circuit. One embodiment provides at least one switching element is acting as a homogenizer, and at least one switching element is acting as a precharger. The diffusion region of the switching element acting as a homogenizer is separated from the diffusion region of the switching element acting as a precharger. | 05-14-2009 |
20090121286 | Integrated Circuit Comprising a Field Effect Transistor and Method of Fabricating the Same - An integrated circuit includes a field effect transistor including: a gate electrode disposed adjacent to a surface of semiconductor substrate and a source/drain region disposed in the semiconductor substrate and adjacent to the surface. A net dopant concentration of a first section of the source/drain region decreases towards the gate electrode along a direction perpendicular to the surface. | 05-14-2009 |
20090109774 | TEST METHOD AND SEMICONDUCTOR DEVICE - A test method and a semiconductor device is disclosed. One embodiment provides sending out a test signal by a semiconductor device. A reflected signal generated in reaction is compared to the test signal with a first threshold value. The reflected signal is compared with a second threshold value differing from the first threshold value. | 04-30-2009 |
20090108248 | INTEGRATED CIRCUIT INCLUDING DOPED SEMICONDUCTOR LINE HAVING CONDUCTIVE CLADDING - An integrated circuit includes an array of memory cells and a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of memory cells. The integrated circuit includes conductive cladding contacting the doped semiconductor line. | 04-30-2009 |
20090097348 | INTEGRATED CIRCUIT INCLUDING A MEMORY MODULE HAVING A PLURALITY OF MEMORY BANKS - An integrated circuit including a memory module having a plurality of memory banks is disclosed. One embodiment provides an even number of at least four memory banks. Each memory bank has a plurality of memory cells. Each two of the memory bank form a memory bank region and being alternately connected to an m-bit data bus. The memory banks are classified into two groups, each group including a memory bank of each memory bank region. The memory module further includes a selection device connected to the memory banks and being responsive to selection bits. The selection device selects one of the two groups of memory banks and a group of i memory cells within the memory banks of the selected group of memory banks to access the selected i memory cells per one stroke via the associated m-bit data buses of the memory groups including the selected memory banks, m being equal to an integer multiple of i. | 04-16-2009 |
20090097004 | Lithography Apparatus, Masks for Non-Telecentric Exposure and Methods of Manufacturing Integrated Circuits - A lithography apparatus includes a first optical system configured to irradiate a mask with a non-telecentric illumination and a second optical system configured to guide radiation reflected off or transmitted through the mask to a substrate. The mask includes an absorber structure arranged over a non-absorbing surface, wherein the absorber structure includes sidewalls extending in a first direction intersecting a main plane of incidence of the non-telecentric illumination. The sidewall angle of the sidewalls may be at most equal to 90° minus the angle of incidence of the non-telecentric illumination and at least equal to 90° minus the sum of the angle of incidence and a half acceptance angle of the second optical system. | 04-16-2009 |
20090097001 | Non-Telecentric Lithography Apparatus and Method of Manufacturing Integrated Circuits - A lithography apparatus includes a condenser system and a projection system. The condenser system is configured to irradiate a mask with non-telecentric incident radiation. The projection system is configured to collect and focus a radiation diffracted at an absorber pattern on the mask to a sample. The projection system is further configured to compensate, in the diffracted radiation, a phase and/or intensity variation resulting from the diffraction of the non-telecentric incident radiation, wherein the diffraction results from an absorber pattern provided on the mask. | 04-16-2009 |
20090096001 | Integrated Circuit and Method of Manufacturing the Same - A method of manufacturing an integrated circuit includes: forming a trench in a substrate, forming a high-k dielectric layer lining the trench, and removing a section of the high-k dielectric layer from the trench via an isotropic dry etch process. | 04-16-2009 |
20090087965 | STRUCTURE AND METHOD FOR MANUFACTURING PHASE CHANGE MEMORIES - A method for manufacturing at least one resistively switching memory cell including generating a first electrode; depositing a phase change material layer, the phase change material layer including a composition of formula Ga | 04-02-2009 |
20090085598 | INTEGRATED CIRCUIT TEST SYSTEM AND METHOD WITH TEST DRIVER SHARING - An integrated circuit test system and method for testing integrated circuits or chips is disclosed. One embodiment provides a test signal from a test driver via a primary test channel and distributed via parallel wiring paths to a plurality of contact pads of one or more integrated circuits or chips under test. At least one operational amplifier is arranged in the wiring path connected to the contact pads of the integrated circuits or chips. | 04-02-2009 |
20090085596 | SYSTEM AND METHOD FOR TESTING SEMICONDUCTOR DEVICES - A system for testing semiconductor devices is disclosed. In one embodiment, the test system being configured to be electrically connected via parallel wiring paths to a plurality of contact pins of a number of devices under test. The test system having at least one signal distribution matrix arranged in the wiring path to provide signals for testing and/or power supply to the devices. | 04-02-2009 |
20090085220 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURING - A semiconductor component and a method of manufacturing is disclosed. One embodiment provides a semiconductor chip with a chip pad and a support pad and a substrate with a substrate pad. The support pad is connected by wire bonding to the chip pad and the support pad. | 04-02-2009 |
20090085084 | Integrated Circuit and Methods of Manufacturing the Same - A method of manufacturing an integrated circuit includes forming landing pads in an array region of a substrate, individual ones of the landing pads being electrically coupled to individual ones of portions of devices formed in the substrate in the array region. The method also includes forming wiring lines within a peripheral region of the substrate. Forming the landing pads and forming the wiring lines includes a common lithographic process being effective in both the array and peripheral regions. The wiring lines and the landing pads of the integrated circuit are self-aligned. | 04-02-2009 |
20090080570 | INTEGRATED CIRCUIT AND METHOD OF GENERATING A BIAS SIGNAL FOR A DATA SIGNAL RECEIVER - An integrated circuit and method of generating a bias signal for a data signal receiver is disclosed. One embodiment provides a replica circuit configured to generate a feedback signal, wherein the replica circuit is a replica of at least a part of a data signal receiver, and wherein the feedback signal depends on a reference signal of the data signal receiver. A compensation circuit is configured to compensate an influence of the reference signal on the feedback signal. An amplifier circuit is configured to generate a bias signal based on the feedback signal, the bias signal being provided to the data signal receiver. | 03-26-2009 |
20090079450 | SEMICONDUCTOR TEST DEVICE - A semiconductor test device. In one embodiment, the test device includes a drill bit. The test device is configured to rotate the drill bit, at least after contacting the semiconductor device, for penetrating into the semiconductor device. | 03-26-2009 |
20090075178 | Mask with Registration Marks and Method of Fabricating Integrated Circuits - A photomask for a lithography apparatus includes a chip pattern configured to be transferred into a resist layer on a workpiece and at least one registration mark that is configured not to be transferred into the resist layer. Mask qualification may be improved without impacting wafer level processes. | 03-19-2009 |
20090073010 | DATA CONVERSION - A circuit includes a data conversion circuit including a first input configured to receive a first serial data stream, a second input configured to receive a second serial data stream, and a third input configured to receive a third serial data stream. A first sampling circuit is coupled to the first, second, and third inputs and is configured to sample the first to third data streams based on a plurality of clock signals and to generate a corresponding plurality of first sampled signals. A second sampling circuit is configured to sample the plurality of first sampled signals based on a further clock signal. The further clock signal has a clock frequency different from a clock frequency underlying the first to third serial data streams. | 03-19-2009 |
20090072398 | INTEGRATED CIRCUIT, CIRCUIT SYSTEM, AND METHOD OF MANUFACTURING - An integrated circuit, a circuit system and method of manufacturing such is disclosed. One embodiment provides a circuit chip including a first contact field on a chip surface; and an insulating layer on the chip surface. The insulating layer includes a flexible material. A contact pillar is coupled to the first contact field and extends from the chip surface through the insulating layer. The contact pillar includes a conductive material. | 03-19-2009 |
20090072274 | INTEGRATED CIRCUIT INCLUDING A FIRST GATE STACK AND A SECOND GATE STACK AND A METHOD OF MANUFACTURING - An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack and a gate dielectric on a first surface section of a main surface of a semiconductor substrate, and a second gate stack including a memory layer stack on a second surface section. A first pattern is transferred into the first gate stack and a second pattern into the second gate stack. | 03-19-2009 |
20090066345 | SENSOR HAVING ORGANIC FIELD EFFECT TRANSISTORS - A force sensor based on an organic field effect transistor applied on a substrate is disclosed. In one embodiment, a mechanical force acting on the transistor causes a change in its source-drain voltage or its source-drain current which corresponds to said force and which can in each case be detected as measurement quantity for the acting force, a diaphragm-based pressure sensor that uses a force sensor of this type, a one- or two-dimensional position sensor that uses a multiplicity of force sensors of this type, and a fingerprint sensor that uses a multiplicity of such force sensors. | 03-12-2009 |
20090057743 | Integrated Circuit Including Structures Arranged at Different Densities and Method of Forming the Same - A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the first structures, in a second portion. The first and second structures are defined by lithography processes using photomasks. At least one of the photomasks includes both openings in a first region for supporting the definition of the first structures and openings in a second region for supporting the definition of the second structures. | 03-05-2009 |
20090057737 | INTEGRATED CIRCUIT WITH DIELECTRIC LAYER - A method of fabricating an integrated circuit with a dielectric layer on a substrate is disclosed. One embodiment provides forming the dielectric layer in an amorphous state on the substrate, the dielectric layer having a crystallization temperature; a doping the dielectric layer; a forming of a covering layer on the dielectric layer at a temperature being equal to or below the crystallization temperature; and a heating of the dielectric layer to a temperature being equal to or greater than the crystallization temperature. | 03-05-2009 |
20090052232 | METHOD FOR FABRICATING AN INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT WITH SPATIALLY STABLE MATERIAL - A method for fabricating an integrated circuit, the method comprises forming a first electrode, depositing resistance changing material over the first electrode, the resistance changing material having an active zone for switching the resistance of the resistance changing material and an inactive zone, and forming a second electrode over the resistance changing material. The chemical composition of the resistance changing material in the active zone differs from the chemical composition of the resistance changing material in the inactive zone | 02-26-2009 |
20090051383 | Test Method and Production Method for a Semiconductor Circuit Composed of Subcircuits - Test method and production method for testing a semiconductor circuit comprising a plurality of subcircuits. The semiconductor circuit is produced according to specification stipulations comprising a design based on a hardware description language for a functional implementation, a logic synthesis for a structural implementation, a layout design for a topological implementation and processing a semiconductor substrates in accordance with the layout design. A test pattern having test signal sequences is coupled into the semiconductor circuit and functional results are coupled out. Test signal lengths and/or test signal levels are selected from a previously generated test parameter list, wherein the test parameter list is generated during the logic synthesis. | 02-26-2009 |
20090050873 | System Including Memory with Resistivity Changing Material and Method of Making the Same - A method of manufacturing a memory cell includes: forming a first electrode, depositing a first insulator material over the first electrode, forming a via in the first insulator material, depositing a resistivity changing material in the via without completely filling the via, and forming a second electrode contacting the resistivity changing material. | 02-26-2009 |
20090050870 | INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT WITH SPATIALLY STABLE MATERIAL - An integrated circuit includes a heater element serving as a first electrode, a second electrode, a memory element comprising resistance changing material coupled to the heater element and to the second electrode, and a diffusion compensation region coupled to the heater element and to the resistance changing material. The diffusion compensation region includes a surplus of at least one diffusible species present in the memory element and provides at least one diffusible species to the memory element. | 02-26-2009 |
20090046534 | Method of Operating a Memory Apparatus, Memory Device and Memory Apparatus - A method for operating a memory apparatus which comprises at least two memory devices, each memory device containing at least one bank, comprising: activation of at least one word line in at least one bank on the basis of a row activation command; storage of bank information, the bank information indicating which banks per memory device contain a word line activated by the row activation command; reading/writing of memory contents from/to banks with activated word lines on the basis of the bank information. | 02-19-2009 |
20090046499 | INTEGRATED CIRCUIT INCLUDING MEMORY HAVING LIMITED READ - An integrated circuit including a memory with an array of memory cells, each memory cell comprising a non-volatile memory element; and a limited read circuit communicatively coupled to the array of memory cells. | 02-19-2009 |
20090046498 | INTEGRATED CIRCUIT INCLUDING MEMORY HAVING REDUCED CROSS TALK - An integrated circuit includes a first electrode, a second, a first resistivity changing material contacting the first electrode at a first interface, and a second resistivity changing material contacting the second electrode at a second interface. A direct communication path between the first interface and the second interface is greater than the lateral distance. | 02-19-2009 |
20090045856 | CLOCK SIGNAL SYNCHRONIZING DEVICE WITH INHERENT DUTY-CYCLE CORRECTION CAPABILITY - One aspect relates to a clock signal synchronizing device, in particular to a delayed locked loop (DLL) with capability to correct static duty-cycle offset and to filter clock-jitter. One aspect relates to a clock signal synchronizing method with capability to correct static duty-cycle offset and to filter clock-jitter. In accordance one aspect, there is provided a clock signal synchronizing device including a delay circuit having a variable delay time and delaying an incoming clock signal or a signal generated therefrom to output a delayed clock signal. Also included is a negator for inverting the delayed clock signal to output an inverted delayed clock signal. Also included is a delay control circuit for controlling the delay circuit to adjust the phase relation between the incoming clock signal and the inverted delayed clock signal and a phase interpolator. The phase interpolator is activated when the incoming clock signal and the inverted delayed clock signal are substantially in phase and adds the incoming clock signal multiplied with a factor of substantially (1−p) to the inverted delayed clock signal multiplied with a factor of substantially p to output a compound signal to the delay circuit, p being a real number greater than or equal to 0 and smaller than or equal to 1. | 02-19-2009 |
20090045679 | Integrated Circuit and Method of Operating the Same - An integrated circuit includes a storage component, a voltage stabilizer circuit with an input configured to receive an input voltage and an output configured to provide an output voltage, and a load. The load is coupled to the output of the voltage stabilizer circuit. The integrated circuit is operable in a first and second operating state. In the first operating state, the storage component receives an input voltage and in the second operating state the input voltage is provided to the input of the voltage stabilizer circuit. | 02-19-2009 |
20090045385 | INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT WITH HIGH SPEED LOW CURRENT PHASE CHANGE MATERIAL - An integrated circuit includes a first electrode, a second electrode, and a memory element coupled to the first electrode and to the second electrode, the memory element includes fast-operation resistance changing material doped with dielectric material. | 02-19-2009 |
20090040861 | Method of Operating a Memory Apparatus, Memory Device and Memory Apparatus - A memory apparatus includes at least two memory devices, each memory device including at least one memory bank. A method of operating the memory apparatus includes receiving a row activation command generated by a memory controller, wherein the row activation command includes a bank address. The method also includes activating a word line in a bank of one of the memory devices based on the row activation command, wherein the bank address is used to select the memory device. | 02-12-2009 |
20090039910 | TEST APPARATUS FOR SEMICONDUCTOR MODULES - A test apparatus for semiconductor modules. One embodiment provides a test system. The test system includes a handler configured to receive at least one semiconductor module. The test system is equipped with a plurality of different pin cards. The handler has at least two independent groups of test receptacles. | 02-12-2009 |
20090039458 | INTEGRATED DEVICE - A method of fabricating an integrated device on a substrate with an exposed surface region is disclosed. One embodiment provides introducing a first component into the exposed surface region of the substrate. A material is provided on the exposed surface region. The material on the exposed surface region is cured and the first component release from the exposed surface region of the substrate. | 02-12-2009 |
20090037764 | MEMORY-MODULE CONTROLLER, MEMORY CONTROLLER AND CORRESPONDING MEMORY ARRANGEMENT, AND ALSO METHOD FOR ERROR CORRECTION - A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module. | 02-05-2009 |
20090034355 | INTEGRATED CIRCUIT INCLUDING MEMORY CELLS WITH TUNNEL FET AS SELECTION TRANSISTOR - An integrated circuit having an array of memory cells is disclosed. One embodiment provides selection transistors for selecting one of a plurality of memory cells. The selection transistor is a tunnel field effect transistor in order to reduce a leakage current when the transistor is in its non-conducting state. Furthermore an operation method and a method for production are described. | 02-05-2009 |
20090033364 | INTEGRATED CIRCUIT DEVICE FOR RECEIVING DIFFERENTIAL AND SINGLE-ENDED SIGNALS - An integrated circuit device includes a receiver that is capable of receiving and converting either differential input signals or two unrelated single-ended input signals. | 02-05-2009 |
20090019184 | INTERFACING MEMORY DEVICES - An integrated circuit includes a memory interface circuit. The memory interface circuit includes a first interface channel configured to couple to at least one memory device, a second interface channel configured to couple to at least one memory device, and a multiplexer configured to select between the first interface channel and the second interface channel. | 01-15-2009 |
20090006785 | APPARATUS, METHOD AND SYSTEM FOR COMPARING SAMPLE DATA WITH COMPARISON DATA - An apparatus, method and system for comparing sample data with comparison date is disclosed. One embodiment provides a plurality of storage locations, an interface coupled to a plurality of storage locations for an exchange of data between the plurality of storage locations and external circuitry coupled to the interface, and a data comparator for comparing comparison data stored in the plurality of storage locations and sample data. | 01-01-2009 |
20090002951 | SYSTEM HAVING A HEAT TRANSFER APPARATUS - A system including a heat transfer apparatus is disclosed. One embodiment provides for an electronic device and a heat transfer apparatus including a heat distribution plate with a first surface being at least in part in thermal communication with the electronic device. The thermal conductivity of the heat distribution plate is higher in a direction substantially parallel to the first surface than in a direction perpendicular to the first surface. | 01-01-2009 |
20080319693 | Method, Device And Computer Program For Evaluating A Signal Transmission - A method comprises the step of obtaining a first signal of the signal from a first position of a transmission channel, and a second signal of the signal from a second position of the transmission channel, determining a delay time between the first signal and the second signal by a first degree of alikeness of the first signal and the second signal trace, and determining a direction function vector of the signal by a second degree of alikeness of the first signal and the second signal trace. | 12-25-2008 |
20080318153 | PHOTOSENSITIVE LAYER STACK - A photosensitive layer stack and methods for multiple exposure lithography are disclosed having a bleachable layer with a first absorption switching from absorptive to transmissive upon irradiation and a photochromic layer having a second absorption switching from transmissive to absorptive upon irradiation. | 12-25-2008 |
20080317208 | Radiation Source and Method of Operating a Radiation Source in a Measurement Tool - A radiation source for a measurement tool includes an electron source configured to provide an electron beam, an anode configured to emit X-ray radiation under irradiation with the electron beam, and a deflection unit arranged between the electron source and the anode and operable to deflect the electron beam. | 12-25-2008 |
20080315430 | NANOWIRE VIAS - A method of fabricating an integrated circuit including arranging a nanowire with a first end portion thereof at a first contact surface of a first electrical contact and with a second end portion sticking up from the first contact surface, and embedding at least part of the nanowire in dielectric material. | 12-25-2008 |
20080315357 | INTEGRATED CIRCUIT AND METHOD INCLUDING STRUCTURING A MATERIAL - A method of making an integrated circuit including structuring a material. The method includes providing an arrangement of three-dimensional bodies. The material is arranged between the bodies and structured directed radiation. The projection pattern of the three-dimensional bodies is transferred into the material. The structured material connects at least two of the three-dimensional bodies. | 12-25-2008 |
20080311283 | Method of Inspecting and Manufacturing an Integrated Circuit - An auxiliary layer is provided over a main surface of a sample, wherein the sample may be a semiconductor substrate. The auxiliary layer may have an essentially plane surface and is transparent or semi-transparent to an inspection radiation with a wave length between, for example, 193 and 800 nm. The sample coated with the auxiliary layer is inspected for defects in the sample via an imaging method that may use coherent radiation. After inspection, the auxiliary layer is removed. Dependent on the defect count, a process of manufacturing integrated circuits may be continued or the sample may be reworked or discarded. | 12-18-2008 |
20080309927 | WAFER INSPECTION SYSTEM AND METHOD - A wafer inspection system and method is disclosed. On embodiment includes an edge defect detection unit, an optical inspection unit and a processor unit. The edge defect detection unit is configured to detect defects occurring in an edge area of the wafer and to record edge defect positions. The optical inspection unit is configured to capture images of functional devices in a functional area of the wafer surrounded by the edge area and to record device defect positions related to the functional devices. The processor unit is configured to output a data set relating the edge and device defect positions to the same coordinate system. | 12-18-2008 |
20080308870 | INTEGRATED CIRCUIT WITH A SPLIT FUNCTION GATE - An integrated circuit is disclosed. One embodiment provides a field-effect transistor including a gate electrode, a channel region and a first source/drain region. The gate electrode may include a main section determining a first flat band voltage between the gate electrode and the channel region and a first lateral section that is in contact with the main section and that determines a second flat band voltage between the gate electrode and the first source/drain region. The first and second flat band voltages differ by at least 0.1 eV. | 12-18-2008 |
20080304029 | Method and System for Adjusting an Optical Model - In a method of adjusting an optical parameter of an exposure apparatus, a photolithographic projection is performed using an exposure apparatus and using a layout pattern so as to provide measured layout data with different focus settings of the exposure apparatus. An optical model is provided including at least one optical parameter and a simulated image is created by using the optical model and the layout pattern. The optical model is optimized by modifying the optical parameter. | 12-11-2008 |
20080301370 | Memory Module - A memory module includes a module circuit board, an amplifier circuit disposed on the module circuit board for amplifying an input signal, and a memory component to store a data item, wherein the memory component is disposed on the module circuit board. The amplifier circuit includes an input to receive a data signal and an output to provide an amplified data signal. The memory component comprises an input to receive the amplified data signal, wherein the data item is stored in the memory component in dependence on a level of the received amplified data signal. | 12-04-2008 |
20080298149 | CURRENT REDUCTION WITH WORDLINE BIT LINE SHORT-CIRCUITS IN DRAMS AND DRAM DERIVATIVES - An integrated circuit memory device includes a memory array with associated word lines and bit lines. A switching arrangement is connected between a word line and a first voltage source that selectively connects the word line to the first voltage source, and also is responsive to a short-circuit between the word line and the bit line. | 12-04-2008 |
20080297765 | Apparatus and Method for Determining Trench Parameters - An apparatus includes an evaluating unit and a peak detection unit. The peak detection unit may be configured to determine at least one peak parameter of a peak in a Fourier transformed reflection spectrum of infrared radiation reflected off a sample that may comprise trench structures. The evaluation unit may be configured to determine from the at least one peak parameter and from a correction value containing information about an effective refractive index of the sample, a trench parameter of the trench structures. | 12-04-2008 |
20080296778 | Interconnection Structure and Integrated Circuit - A method of manufacturing an integrated circuit and an interconnection structure includes forming a conductive portion along a first direction and conductive lines along a second direction. | 12-04-2008 |
20080296680 | METHOD OF MAKING AN INTEGRATED CIRCUIT INCLUDING DOPING A FIN - A method of making an integrated circuit including doping a fin is disclosed. The method includes providing a substrate having at least one fin of a semiconductor material and carrying out a gas-phase doping of the at least one fin. | 12-04-2008 |
20080296674 | TRANSISTOR, INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT - A transistor, an integrated circuit and a method of forming an integrated circuit is disclosed. One embodiment includes a gate electrode. The gate electrode is disposed in a gate groove formed in a semiconductor substrate and includes a conductive carbon material. | 12-04-2008 |
20080290337 | Ultrathin Dielectrics and the Application Thereof in Organic Field Effect Transistors - An organic field effect transistor, having a substrate, a source electrode, a drain electrode and a gate electrode and an organic semiconductor material is disclosed. Arranged between the gate electrode and the organic semiconductor material is a dielectric layer (gate dielectric) obtained from a self-assembled monolayer of an organic compound having an anchor group, a linker group, a head group, and an aliphatic orientating group, the anchor group, the linker group, the head group, and the aliphatic orientating group being combined with one another in the order stated. | 11-27-2008 |
20080288835 | Test method, integrated circuit and test system - The test method, integrated circuit and test system embodiments disclosed herein relate to testing at least one integrated circuit which uses an internal operating clock and has a first number of address pins, a second number of command pins and an address generation circuit which receives at least one encoded address information item using a third number of the address pins, which is smaller than the first number, and provides the other address pins as a fourth number of free address pins, where at least one first command is transferred using the command pins and at least one second command is transferred using at least one portion of the fourth number of the address pins from a test apparatus to the integrated circuit using a test clock which has a lower rate than the internal operating clock. | 11-20-2008 |
20080283973 | INTEGRATED CIRCUIT INCLUDING A DIELECTRIC LAYER AND METHOD - An integrated circuit including a dielectric layer and a method for producing an integrated circuit. In one embodiment, a dielectric layer is deposited in a process atmosphere. The process atmosphere includes a first starting component at a first point in time, a second starting component at a second point in time and a third starting component at a third point in time. The third starting component includes a halogen. | 11-20-2008 |
20080283910 | INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT - An integrated circuit and method of forming an integrated circuit is disclosed. One embodiment includes a FinFET of a first type having a first gate electrode and a FinFET of a second type having a second gate electrode. The first gate electrode is formed in a gate groove that is defined in a semiconductor substrate and a bottom side of a portion of the second gate electrode is disposed above a main surface of the semiconductor substrate. | 11-20-2008 |
20080282535 | METHOD OF FABRICATING AN INTEGRATED CIRCUIT - A method of fabricating an integrated circuit, including a functional layer on a substrate is disclosed. One embodiment includes providing a substrate in a process atmosphere. A first precursor and a second precursor are provided in the process atmosphere. The first precursor is removed from the process atmosphere. A third precursor is provided in the process atmosphere. | 11-20-2008 |
20080280446 | METHOD OF PRODUCING A MICROSCOPIC HOLE IN A LAYER AND INTEGRATED DEVICE WITH A MICROSCOPIC HOLE IN A LAYER - A microscopic hole is produced in a dielectric layer having a dielectric first material, a first surface and a second surface. In one embodiment, the tapered through-hole is etched from the second surface of the layer to the first surface of the layer. The tapered hole provides a first cross section near the first surface of the dielectric layer and a second cross section near the second surface of dielectric layer. A cladding is deposited at the inner surface of the through-hole. The cladding includes a second material and provides a thickness decreasing from the second surface to the first surface. | 11-13-2008 |
20080277760 | INTEGRATED CIRCUIT DEVICE HAVING OPENINGS IN A LAYERED STRUCTURE - An integrated circuit device includes a substrate with a first layer situated on the substrate. The first layer defines a first opening with a cover layer deposited on the first layer and coating a sidewall portion of the first opening. A second layer is situated on the cover layer. The second layer defines a second opening extending through the second layer and through the cover layer to connect the first and second openings. | 11-13-2008 |
20080277717 | MINORITY CARRIER SINK FOR A MEMORY CELL ARRAY COMPRISING NONVOLATILE SEMICONDUCTOR MEMORY CELLS - A memory cell array of nonvolatile semiconductor memory cells is specified in which a minority carrier sink is formed within a semiconductor body in the region of the memory cell array, the minority carrier sink being arranged outside a space charge zone structure that forms in the semiconductor body during operation of the semiconductor memory cells, and the minority carrier sink having a shorter minority carrier lifetime in comparison with a semiconductor zone reaching as far as a surface of the semiconductor body. | 11-13-2008 |
20080275273 | Method for Synthesizing Long-Chain Phosphonic Acid Derivatives and Thiol Derivatives - A process for synthesizing long-chain phosphonic acid derivatives and thiol derivative is disclosed. One embodiment provides organic compounds which can form a self-assembled monolayer and are obtained by reaction of an olefin with a thiocarboxylic acid and subsequent hydrogenation to give the thiol, or with a phosphite and subsequent hydrolysis to give the phosphonic acid. | 11-06-2008 |
20080268638 | Substrate with Feedthrough and Method for Producing the Same - A substrate with first and second main surfaces includes at least one channel extending from the first main surface to the second main surface. The at least one channel includes a first cross-sectional area at a first location and a second cross-sectional area at a second location. An electrically conductive first material is disposed in the at least one channel. | 10-30-2008 |
20080258206 | Self-Aligned Gate Structure, Memory Cell Array, and Methods of Making the Same - A self-aligned gate structure includes a first gate region and a second gate region. The first gate region extends in semiconductor substrate portions to a lesser depth than in isolation trenches that are adjacent to the semiconductor substrate portions. The first gate region comprises a first conductive material. The second gate region is adjacent to the first gate region and extends above a surface of the semiconductor substrate. The second gate region includes a second conductive material. | 10-23-2008 |
20080253179 | SEMICONDUCTOR DEVICE, AN ELECTRONIC DEVICE AND A METHOD FOR OPERATING THE SAME - A semiconductor memory device includes circuitry coupled to a plurality of memory cells with transistors. The circuitry is configured to change a potential of a body of the transistor to a degree depending on a charging state of the body. A gate electrode of the transistor is maintained in a non-addressed state. | 10-16-2008 |
20080253160 | INTEGRATED CIRCUIT HAVING A MEMORY CELL ARRAY AND METHOD OF FORMING AN INTEGRATED CIRCUIT - An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75. | 10-16-2008 |
20080252346 | CIRCUIT HAVING A CLOCK SIGNAL SYNCHRONIZING DEVICE WITH CAPABILITY TO FILTER CLOCK-JITTER - A circuit having a clock signal synchronizing device with capability to filter clock-jitters is disclosed. One embodiment provides a delayed locked loop with capability to filter clock-jitter. Further, the invention relates to a clock signal synchronizing method with capability to filter clock-jitter. | 10-16-2008 |
20080250292 | Memory Module with Ranks of Memory Chips - A memory module includes a plurality of memory devices and a stacked error correction code memory device. The plurality of memory devices includes one or more memory chips arranged in a plurality of ranks. The stacked error correction code memory device includes a plurality of error correction code memory chips. The number of error correction code memory chips is at least one more than the number of the one or more memory chips. Each of the error correction code memory chips are arranged together with the memory chips of one of the ranks. | 10-09-2008 |
20080247252 | Semiconductor Memory Device with Temperature Control - A memory device in a semiconductor substrate includes at least one temperature sensor to provide a temperature dependent signal and at least one circuit to dissipate heat in response to a control signal. A control circuit is coupled to the at least one circuit and is operable to generate the control signal in response to the temperature dependent signal. | 10-09-2008 |
20080246505 | SEMICONDUCTOR DEVICE TEST SYSTEM AND METHOD - A semiconductor device test method and system. One embodiment provides a method for testing semiconductor devices forming a group of semiconductor devices to be tested. For addressing or selection of one of the semiconductor devices of the group, at least two different signals are supplied to the respective semiconductor device to be addressed or selected via at least two different semiconductor device connections. | 10-09-2008 |
20080246499 | SYSTEM AND METHOD FOR THE ELECTRICAL CONTACTING OF SEMICONDUCTOR DEVICES - A device and a method for the electrical contacting of semiconductor devices. One embodiment provides for testing semiconductor devices by using a contacting device for the electrical contacting of a number of semiconductor devices to be tested and for the electrical connection with a test system. The contacting device includes a fluid container for accommodating a fluid adapted to be tempered. | 10-09-2008 |
20080240290 | METHOD AND DEVICE FOR TRANSMITTING OUTGOING USEFUL SIGNALS AND AN OUTGOING CLOCK SIGNAL - Method and device for transmitting outgoing useful signals and an outgoing clock signal. Useful signals and a clock signal are transmitted from a transmitter via a first line pair and a second line pair to a receiver. A first useful signal is transmitted in the form of a modulated difference between the electrical potentials of the first line pair. A second useful signal is transmitted in the form of a modulated difference between the electrical potentials of the second line pair. The clock signal is transmitted in the form of a modulated difference between the average value of the potentials of the first line pair and the average value of the potentials of the second line pair. | 10-02-2008 |
20080239788 | INTEGRATED CIRCUIT HAVING A RESISTIVELY SWITCHING MEMORY AND METHOD - An integrated circuit having a resistance-based or resistively switching memory cell, and a method for operating a resistively switching memory cell is disclosed. One embodiment is adapted to be put in a low-resistance state by applying a first threshold voltage and in a high-resistance state by applying a second threshold voltage, wherein reading out of the data content from the memory cell is performed by applying a voltage to the memory cell in the range of the first or second threshold voltage or a higher voltage. | 10-02-2008 |
20080238468 | Integrated circuit chip and method for testing an integrated circuit chip - In a method or apparatus such as an integrated circuit (IC) chip including a plurality of circuits for executing a plurality of testmodes, a testmode entry code specifying one of the plurality of testmodes and one of an unrestricted private testmode category and a restricted public testmode category is received. Execution of only a public testmode of the plurality of testmodes is enabled when the testmode entry code specifies the restricted public testmode category. Execution of all of the plurality of testmodes is enabled when the testmode entry code specifies the unrestricted private testmode category. | 10-02-2008 |
20080238462 | TEST DEVICE FOR SEMICONDUCTOR DEVICES - A test device for semiconductor devices is disclosed. One embodiment provides a probe card, having at least one contact test body for contacting a semiconductor device. The probe card includes self-alignment devices and/or a penetration restriction device, or parts thereof. A semiconductor device is provided having at least one contact field adapted to be contacted by contact test bodies of a test device. The semiconductor device includes self-alignment devices and/or a penetration restriction device, or parts thereof, for the contact test body in the region of the contact field. | 10-02-2008 |
20080237891 | SEMICONDUCTOR DEVICE - A semiconductor device having a stacked arrangement of a substrate and a first chip and a second chip is disclosed. In one embodiment, the first chip is arranged with a lower face on an upper face of the substrate; the second chip with a lower face on an upper face of the first chip, whereby a partial area of the upper face of the first chip that is adjacent to an edge of the first chip is uncovered by the second chip; a fifth wire contact pad is arranged on the uncovered area of the upper face of the first chip; a first bonding wire is arranged that is connected with a first wire contact pad of the substrate and the fifth wire contact pad of the first chip. | 10-02-2008 |
20080232170 | MEMORY DEVICE, A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FORMING A MEMORY DEVICE - A memory device having an array portion including memory cells, and a peripheral portion including conductive lines is disclosed. In one embodiment, portions of the conductive lines adjoin a surface of a semiconductor carrier. | 09-25-2008 |
20080231360 | ARRANGEMENT OF SIGNAL LINE PAIRS AND AMPLIFIERS - An arrangement of signal line pairs and amplifiers is disclosed. One embodiment provides each signal line pair of a group of signal line pairs that are directly adjacent and run parallel to one another is respectively assigned an amplifier from a group of amplifiers arranged successively in a signal line direction. Each signal line pair includes a first and a second signal line, between which the amplifier assigned to the respective signal line pair is arranged. The position of an amplifier is assigned to a specific signal line pair in the amplifier group along the signal line direction is chosen in such a way that a first coupling section which forms the first signal line assigned to the respective amplifier together with its adjacent lines along the amplifier group, and a second coupling section, which forms the second signal line assigned to the respective amplifier together with its adjacent lines along the amplifier group, substantially have the same coupling properties. | 09-25-2008 |
20080231303 | SEMICONDUCTOR DEVICE FOR ELECTRICAL CONTACTING SEMICONDUCTOR DEVICES - A semiconductor device with a number of contact pads for the electrical contacting of the semiconductor device is disclosed. A padding layer, which is manufactured of a hard material, is provided at least partially below an upper layer of the contact pads. | 09-25-2008 |
20080231295 | DEVICE AND METHOD FOR ELECTRICAL CONTACTING SEMICONDUCTOR DEVICES FOR TESTING - A device and method are disclosed for electrical contacting of semiconductor devices for testing. One embodiment provides for testing semiconductor devices or integrated circuits, including a probe card with contact tips for the electrical contacting of the semiconductor devices. The electrical connection of at least one contact tip to the test system is adapted to be switched via a resistively switching memory cell. A resistively switching memory cell in the form of a nano switch is integrated in the electrical connection of the contact tip. | 09-25-2008 |
20080231293 | DEVICE AND METHOD FOR ELECTRICAL CONTACTING FOR TESTING SEMICONDUCTOR DEVICES - A device and method for electrical contacting for the testing of semiconductor devices is disclosed. One embodiment provides for the electrical connection of the semiconductor device with a test system, including devices for the contacting of connection pins or contact pads of the semiconductor device to be tested. The devices for the contacting of the connection pins or the contact pads of the semiconductor device to be tested include contact holders with at least one exchangeable contact tip. | 09-25-2008 |
20080230722 | INTEGRATED CIRCUIT AND METHOD INCLUDING A PATTERNING METHOD - A method of making an integrated circuit including a patterning method using chemically amplified photoresists and exposure apparatus is disclosed. One embodiment provides a photoresist layer exposed using a screened particle beam or a projection exposure with a projection wavelength of less than a limit wavelength below which secondary electrons are initiated by the exposure in the photoresist layer. The photoresist layer is irradiated, at least in a section subjected to the exposing, with UV light having a spectrum below a limit frequency corresponding to the limit wavelength. | 09-25-2008 |
20080229033 | Method For Processing Data in a Memory Arrangement, Memory Arrangement and Computer System - A method processes data in a memory arrangement. The method includes receiving and transmitting the data from the memory arrangement in the form of data packets according to a predefined protocol. The method includes distributing each received data packet to at least two separate data packet processing units. Each data packet processing unit is coupled to a portion of memory cells of the memory arrangement. The method includes processing, at each data packet processing unit, parts of the received data packets that relate to the portion of the memory cells the data packet processing unit is coupled to. The method includes generating a data packet to be transmitted including setting up, with each data packet processing unit, a part of the data packet to be transmitted. | 09-18-2008 |
20080228988 | METHOD FOR TRANSMITTING CONFIGURATION DATA VIA A CONFIGURATION DATA BUS IN A MEMORY ARRANGEMENT, CONFIGURATION DATA BUS STRUCTURE, MEMORY ARRANGEMENT, AND COMPUTER SYSTEM - A method transmits configuration data in a memory arrangement. The method includes controlling, with a control unit of the memory arrangement, data transmissions via a configuration data bus in the memory arrangement, the controlling including controlling transmitting configuration data of the memory arrangement for storing in at least two register units of the memory arrangement via the configuration data bus from the control unit to each of the at least two register units. The method includes storing, in the at least two register units, the configuration data. The at least two register units have a same bus address identifying the at least two register units on the configuration data bus. The method includes requesting, with the control unit, configuration data stored in the at least two register units. The method includes transmitting, under control of the control unit, the stored configuration data via the configuration data bus from only one of the at least two register units to the control unit. | 09-18-2008 |
20080225503 | ELECTRONIC SYSTEM WITH INTEGRATED CIRCUIT DEVICE AND PASSIVE COMPONENT - An electronic system with integrated circuit device and passive component is disclosed. One embodiment provides a printed circuit board, a method for fabricating an electronic system, and an electronic system, including at least one integrated circuit device and at least one passive component, wherein the passive component is arranged at least partially underneath the integrated circuit device. | 09-18-2008 |
20080222443 | Controller - The invention relates to a controller for generating control signals (evload_o, odload_o, st_chgclk_o, clk_o , clkorfiford_i) synchronous with a continuous clock signal (clk_hr_i) input to it for a device ( | 09-11-2008 |
20080219060 | DEVICE AND METHOD FOR INTERNAL VOLTAGE MONITORING - A memory device and method for internal voltage monitoring is disclosed. One embodiment includes at least one error register configured to store a particular error flag during the stress test. This error flag is generated if the supply voltage applied at the memory device during the test method in the memory device or an internally generated voltage of the memory device lies below a predetermined threshold value. | 09-11-2008 |
20080217672 | INTEGRATED CIRCUIT HAVING A MEMORY - An integrated circuit having a memory arrangement including capacitor elements and further capacitor elements is disclosed. One embodiment provides a substrate layer with contact pads and further contact pads; the capacitor elements being disposed in a first level on the substrate layer and connected with the contact pads; the further capacitor elements being disposed in a second level above the first level; contact elements being disposed between the capacitor elements and connected with the further contact pads; the further capacitor elements being disposed above the contact elements and being connected with the contact elements. | 09-11-2008 |
20080217655 | INTEGRATED CIRCUIT WITH BURIED CONTROL LINE STRUCTURES - An integrated circuit with buried control line structures. In one embodiment, the control lines are subdivided into sections, wherein regions free of switching transistors are provided at intervals along the control lines. Connections for feeding the control potentials into the sections of the control lines are provided at least in a subset of the regions free of switching transistors. The isolations lines are connected to one another by an interconnect running transversely with respect to the control lines. | 09-11-2008 |
20080205179 | INTEGRATED CIRCUIT HAVING A MEMORY ARRAY - An integrated circuit having a memory array and a method for reducing sneak current in a memory array is disclosed. | 08-28-2008 |
20080205118 | INTEGRATED CIRCUIT HAVING A RESISTIVE SWITCHING DEVICE - An integrated circuit, a memory cell, memory device and method of operating the memory device is disclosed. In one embodiment, an integrated circuit having a resistively switching memory cell includes a bitline electrode and a second electrode having a lower voltage potential than the bitline electrode; a switching active volume and a selection transistor connected in series between the bitline electrode and the second electrode. The second electrode is connected, via a connection transistor, to a third electrode having the same or a lower voltage potential than the second electrode; wherein the second electrode includes a buried electrode at least partially positioned below the bitline electrode and the third electrode. | 08-28-2008 |