UNITED MICROELECTRONICS CORP. Patent applications |
Patent application number | Title | Published |
20150348892 | INTERPOSER FABRICATING PROCESS AND WAFER PACKAGING STRUCTURE - An interposer fabricating process includes the following steps. A substrate, an oxide layer, and a dielectric layer are stacked from bottom to top, and an interconnect in the dielectric layer is provided, wherein the dielectric layer includes a stop layer contacting the oxide layer and the interconnect includes a metal structure having a barrier layer protruding from the stop layer. The substrate and the oxide layer are removed until exposing the stop layer and the barrier layer by a removing selectivity between the oxide layer and the stop layer. A wafer packaging structure formed by said interposer is also provided. | 12-03-2015 |
20150348850 | MASK SET AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE BY USING THE SAME - A mask set includes a first mask and a second mask. The first mask includes geometric patterns. The second mask includes at least a strip-shaped pattern with a first edge and a second edge opposite to the first edge. The strip-shaped pattern has a centerline along a long axis of the strip-shaped pattern. The first edge includes inwardly displaced segments shifting towards the centerline and each of the inwardly displaced segments overlaps each of the geometric patterns. | 12-03-2015 |
20150348789 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer. | 12-03-2015 |
20150333130 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of first providing a substrate, in which the substrate includes a SONOS region and a EEPROM region. Next, a first gate layer is formed in the SONOS region and the EEPROM region, the first gate layer is patterned by removing the first gate layer from the SONOS region and forming a floating gate pattern in the EEPROM region, an ONO layer is formed in the SONOS region and the EEPROM region, a second gate layer is formed on the ONO layer of the SONOS region and the EEPROM region, the second gate layer and the first gate layer are patterned to form a floating gate and a control gate in the EEPROM region, and the second gate layer is patterned to form a first gate in the SONOS region. | 11-19-2015 |
20150332996 | INTERPOSER AND METHOD OF FABRICATING THE SAME - The present invention provides an interposer including multiple circuit designs and an uppermost circuit design disposed on the circuit designs. A maximum exposure region is defined as a maximum size which can be defined by a single shot of a lithographic scanner. The sizes of the circuit designs below the uppermost circuit design are smaller than the size of the maximum exposure region. Therefore, the circuit designs are respectively formed by only a single shot of the lithographic scanner. The uppermost circuit design has a length greater than the length of the maximum exposure region, so that the circuit design is formed by stitching two photomasks lithographically. | 11-19-2015 |
20150332926 | Method of Forming High-K Gates Dielectrics - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; injecting a first precursor and forming an interfacial layer on the substrate; and injecting a second precursor and performing a thermal treatment for forming an interface layer on the interfacial layer. | 11-19-2015 |
20150325639 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device and an operating method of the same are disclosed. The semiconductor device includes a substrate, a source region, a drain region, a gate structure, a first lightly-doped region, and a first isolation region. The source region and the drain region are formed in the substrate. The gate structure is formed on the substrate and between the source region and the drain region. The first lightly-doped region is formed below the source region. The first isolation region is formed in the substrate and surrounding the source region, the drain region, and the first lightly-doped region. The source region and the drain region have a first-polarity, and the first lightly-doped region and the first isolation region have a second-polarity. | 11-12-2015 |
20150325574 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND DEVICE MANUFACTURED BY THE SAME - A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating deposition are substantially aligned with the top surface of the insulation. | 11-12-2015 |
20150325453 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is provided. A material layer, a first flowing material layer and a first mask layer are sequentially formed on a substrate. A first etching process is performed by using the first mask layer as a mask, so as to form a first opening in the material layer. The first mask layer and the first flowing material layer are removed. A filler layer is formed in the first opening. A second flowing material layer is formed on the material layer and the filler layer. A second mask layer is formed on the second flowing material layer. A second etching process is performed by using the second mask layer as a mask, so as to form a second opening in the material layer. | 11-12-2015 |
20150303283 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the following steps. A substrate including at least a fin layer and a plurality of gate electrodes is provided. A tilt and twist ion implantation is performed to form a plurality of doped regions in the fin layer. An etching process is performed to remove the doped regions to form a plurality of recesses in the fin layer. | 10-22-2015 |
20150303120 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor package structure is disclosed. The method includes: providing a wafer having a front side and a backside; forming a plurality of through-silicon vias (TSVs) in the wafer and a plurality of metal interconnections on the TSVs, in which the metal interconnections are exposed from the front side of the wafer; performing a monitoring step to screen for TSV failures from the backside of the wafer; and bonding the wafer to a substrate. | 10-22-2015 |
20150294058 | MARK SEGMENTATION METHOD AND METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE APPLYING THE SAME - In this disclosure, a mark segmentation method and a method for manufacturing a semiconductor structure applying the same are provided. The mark segmentation method comprises the following steps. First, a plurality of segments having a width W | 10-15-2015 |
20150293461 | OVERLAP MARK SET AND METHOD FOR SELECTING RECIPE OF MEASURING OVERLAP ERROR - An overlap mark set is provided to have at least a first and a second overlap marks both of which are located at the same pattern layer. The first overlap mark includes at least two sets of X-directional linear patterns, having a preset offset a | 10-15-2015 |
20150287823 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a lightly doped drain in the substrate; and performing a first implantation process for implanting fluorine ions at a tiled angle into the substrate and part of the gate structure. | 10-08-2015 |
20150287797 | HIGH-VOLTAGE METAL-OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD OF FABRICATING THE SAME - The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate. | 10-08-2015 |
20150279957 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure. | 10-01-2015 |
20150279829 | WAFER PACKAGE PROCESS - A wafer package process includes the following steps. A wafer with a plurality of first dies is provided. A plurality of second dies are bonded on the first dies by using flip chip technology, wherein the size of the first die is larger than that of the second die. A molding material is formed to entirely cover the second dies and the wafer. A through via is formed in the molding material. A conductive material is formed to fill the through via onto the molding material. | 10-01-2015 |
20150276382 | MEASUREMENT MARK STRUCTURE - A measurement mark structure includes a mark pattern and a pair of assistant bars positioned at two opposite sides of the mark pattern. The mark pattern includes a plurality of segments. The segments of the mark pattern are arranged along a first direction and the pair of the assistant bars are expend along the first direction. | 10-01-2015 |
20150270277 | Memory Cell and Manufacturing Method Thereof - The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof. | 09-24-2015 |
20150270228 | CRACK-STOPPING STRUCTURE AND METHOD FOR FORMING THE SAME - A crack-stopping structure includes a semiconductor wafer comprising a plurality of dies defined by a plurality of scribe line regions, a plurality of metal patterns formed in the scribe line regions, and a plurality of groups of through silicon holes (TSHs) formed in the scribe line regions. The wafer further includes a front side and a back side, and the TSHs respectively include at least a bottom opening formed in the bottom side of the wafer. The groups of TSHs are formed between the metal patterns and the dies. | 09-24-2015 |
20150264813 | CHIP-STACK INTERPOSER STRUCTURE INCLUDING PASSIVE DEVICE AND METHOD FOR FABRICATING THE SAME - A chip-stack interposer structure including a passive device is described, including an interposing layer, a capacitor, a first contact and a second contact. The capacitor is embedded in or disposed on the interposing layer, including a first electrode, a second electrode and a dielectric layer between the first and the second electrodes. The first contact is connected with the first electrode. The second contact is connected with the second electrode. The first electrode and the second electrode are disposed at the same side of the interposing layer or at different sides of the interposing layer. | 09-17-2015 |
20150262621 | Non-Volatile Memory Which Can Increase the Operation Window - A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of memory cells, a plurality of word lines each coupled to a corresponding row of memory cells, and a decoder coupled to the plurality of word lines for enabling at least one row of memory cells of the plurality of rows of memory cells. | 09-17-2015 |
20150256146 | RESONATOR FILTER - A resonator filter includes a substrate, a bottom electrode formed on the substrate, a multi-layered coupling structure formed on the bottom electrode, a top electrode formed on the multi-layered coupling structure, a first piezoelectric layer sandwiched in between the bottom electrode and the multi-layered coupling structure, and a second piezoelectric layer sandwiched in between the multi-layered coupling structure and the top electrode. The multi-layered coupling structure includes at least an insulating material. | 09-10-2015 |
20150255576 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device is described. A spacer is formed on a sidewall of a fin structure. A portion of the fin structure is removed to form a cavity exposing at least a portion of the inner sidewall of the spacer. An epitaxy process is performed based on the remaining fin structure to form a semiconductor layer that has a shovel-shaped cross section including: a stem portion in the cavity, and a shovel plane portion contiguous with the stem portion. A semiconductor device is also described, which includes the spacer, the remaining fin structure and the semiconductor layer that are mentioned above. | 09-10-2015 |
20150255563 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING MULTI-LAYER HARD MASK - A method for manufacturing a semiconductor device is provided, comprising steps of providing a substrate with an underlying layer formed thereon; forming a gate layer overlying the underlying layer; and forming a multi-layer hard mask layer on the gate layer, and the multi-layer hard mask layer comprising a plurality of material layers and a top hard mask formed on the material layers, wherein the gate layer and the top hard mask contain the same element, such as silicon. | 09-10-2015 |
20150255430 | PACKAGE STRUCTURE - A package structure is disclosed. The package structure includes a first die, a second die on the first die, and a substrate disposed corresponding to the first die. The first die includes a first die identification (ID) region defined thereon and a plurality of first through silicon vias (TSVs) in the first die ID region. The second die includes another first die identification (ID) region and a second die ID region defined thereon and a plurality of second TSVs in the another first die ID region and a plurality of third TSVs in the second die ID region, in which the second TSVs are electrically connected to the first TSVs in the first die. | 09-10-2015 |
20150249158 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a first gate structure, a second gate electrode, a third gate electrode and a protective layer. The first gate structure comprises a first gate electrode disposed on the substrate and a first gate dielectric covering the first gate electrode. The second gate electrode is disposed on and electrically isolated from the first gate electrode. The first gate structure has an extending portion relative to the second gate electrode. The third gate electrode is disposed adjacent to and electrically isolated from the first gate electrode and the second gate electrode. The third gate has an extending portion between a lower surface of the protective layer and an upper surface of the extending portion of the first gate structure. | 09-03-2015 |
20150243776 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR AND FIELD DRIFT METAL OXIDE SEMICONDUCTOR - A laterally diffused metal oxide semiconductor (LDMOS) is provided. A substrate has a deep well with a second conductive type therein. A gate is disposed on the substrate. A first doped region of a second conductive type and a second doped region of a first conductive type are located in the deep well and at the corresponding two sides of the gate. A drain region of a second conductive type is located in the first doped region. A drain contact is disposed on the drain region. A doped region of a first conductive type is located in the first doped region and under the drain region but not directly below the drain contact. A source region is located in the second doped region. A field drift metal oxide semiconductor (FDMOS) which is similar to the laterally diffused metal oxide semiconductor (LDMOS) is also provided. | 08-27-2015 |
20150243754 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal. | 08-27-2015 |
20150243663 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND DEVICE MANUFACTURED USING THE SAME - A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a dual silicide approach of the embodiment, a substrate having a first area with plural first metal gates and a second area with plural second metal gates is provided, wherein the adjacent first metal gates and the adjacent second metal gates are separated by an insulation. A dielectric layer is formed on the first and second metal gates and the insulation. The dielectric layer and the insulation at the first area are patterned by a first mask to form a plurality of first openings. Then, a first silicide is formed at the first openings. The dielectric layer and the insulation at the second area are patterned by a second mask to form a plurality of second openings. Then, a second silicide is formed at the second openings. | 08-27-2015 |
20150236158 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE MADE THEREBY - A method for fabricating a semiconductor device, and a semiconductor device made with the method are described. In the method, a cavity is formed in a substrate, a first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity, and a second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity. In the semiconductor device, the ratio (S/Y) of the thickness S of the buffer layer on a lower sidewall of the cavity to the thickness Y of the buffer layer at the bottom of the cavity ranges from 0.6 to 0.8. | 08-20-2015 |
20150236150 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided. | 08-20-2015 |
20150236010 | ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE CAPABLE OF PREVENTING LATCH-UP ISSUE CAUSED BY UNEXPECTED NOISE - The electrostatic discharge protection structure includes an N-well disposed on a substrate, a P-well disposed on the substrate and adjacent to the N-well, a first doped region of N-type conductivity disposed in the N-well, a second doped region of N-type conductivity disposed in the N-well, a third doped region of P-type conductivity disposed in the N-well, a fifth doped region of P-type conductivity disposed in the P-well, a fourth doped region of N-type conductivity disposed between the third doped region and the fifth doped region in the P-well, an anode electrically connected to the first doped region and the second doped region, and a cathode electrically connected to the fourth doped region and the fifth doped region. | 08-20-2015 |
20150228808 | SCHOTTKY DIODE AND METHOD FOR FABRICATING THE SAME - A Schottky diode is disclosed. The Schottky diode includes: a substrate, a first-type buried layer in the substrate, a cathode region, an anode region surrounding the cathode region, and a first-type guard ring surrounding the anode region and connected to the first-type buried layer. The cathode region preferably includes a high-voltage second-type lightly doped drain in the substrate, a first-type well surrounding the high-voltage second-type lightly doped drain, and a first-type doping region in the first-type well and surrounding the high-voltage second-type lightly doped drain. | 08-13-2015 |
20150228788 | STRESS MEMORIZATION PROCESS AND SEMICONDUCTOR STRUCTURE INCLUDING CONTACT ETCH STOP LAYER - A stress memorization process including the following step is provided. A gate is formed on a substrate. A low-k dielectric layer with a dielectric constant lower than 3 is formed to entirely cover the gate and the substrate. A stress layer is formed to entirely cover the low-k dielectric layer. The stress layer and the low-k dielectric layer are removed. Moreover, a semiconductor structure including a contact etch stop layer is provided. A gate is disposed on a substrate. A porous layer entirely covers the gate and the substrate. A contact etch stop layer entirely covers the porous layer, wherein the thickness of the porous layer is thinner than the thickness of the contact etch stop layer. | 08-13-2015 |
20150228771 | ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE CAPABLE OF PREVENTING LATCH-UP ISSUE CAUSED BY UNEXPECTED NOISE - An electrostatic discharge protection structure includes a first well, a second well disposed in the first well, a first and a second doped region disposed in the first well, a third and a fourth doped region disposed in the second well, a first electrode electrically connected to the first doped region and the second doped region, and a second electrode electrically connected to the fourth doped region. | 08-13-2015 |
20150228547 | SEMICONDUCTOR STRUCTURE WITH THROUGH SILICON VIA AND METHOD FOR FABRICATING AND TESTING THE SAME - A semiconductor structure with a through silicon via includes a substrate having a front side and a back side. The through silicon via penetrates the substrate. A device is disposed on the front side of the substrate. Numerous dielectric layers cover the front side. A first test pad for testing the device is disposed on the front side of the substrate. A second test pad for testing the through silicon via is disposed on the back side of the substrate. A method of fabricating and testing the semiconductor structure is also provided. | 08-13-2015 |
20150228546 | SEMICONDUCTOR DEVICE AND METHOD OF REMOVING SPACERS ON SEMICONDUCTOR DEVICE - A manufacturing method for a semiconductor device includes: providing a substrate including a first gate structure disposed thereon, wherein the first gate structure includes a first gate electrode and a first hard mask covers the first gate electrode. A first oxide spacer and a silicon carbon nitride spacer are formed in sequence to surround the first gate electrode. A thermal treatment is performed to form a silicon oxycarbonitride layer between the first oxide spacer and the silicon carbon nitride spacer. Then, a second oxide spacer, a third oxide spacer, and a first silicon nitride spacer are formed on the silicon carbon nitride spacer in sequence. The first hard mask and the first silicon nitride spacer are removed. Finally, the third oxide spacer, the second oxide spacer, and silicon carbon nitride spacer are removed entirely to expose the silicon oxycarbonitride layer. | 08-13-2015 |
20150214293 | CAPACITOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A capacitor structure includes a substrate with a plurality of dielectric layers sequentially formed thereon, a trench formed in the dielectric layers, wherein the trench is composed of at least two interconnected dual damascene recesses, each dual damascene recess formed in one dielectric layer; and a capacitor multilayer disposed on the sidewall of the trench. | 07-30-2015 |
20150214125 | SCRIBE LINE STRUCTURE - A scribe line structure including a semiconductor substrate, a pad and a first patterned metal layer is provided. The semiconductor substrate has a die region, a die sealing region located outside the die region and a dicing region located outside the die sealing region. The pad is disposed in the dicing region. The first patterned metal layer is disposed in the dicing region, right below and connected to the pad, wherein the first patterned metal layer has a plurality of first patterns directly connected to each other. | 07-30-2015 |
20150214114 | MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE - A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps. A substrate with a plurality of dummy gate structures formed thereon and a first dielectric layer covering the dummy gate structures is provided, the dummy gate structures comprising a plurality of dummy gates and a plurality of insulating layers formed on the dummy gates, wherein at least two of the dummy gate structures have different heights. A first planarization process is performed to expose at least one of the dummy gate structures having the highest height. A first etching process is performed to expose the insulating layers. A chemical mechanical polishing (CMP) process with a non-selectivity slurry is performed to planarize the dummy gate structures. The planarized dummy gate structures are removed to form a plurality of gate trenches. | 07-30-2015 |
20150214068 | METHOD OF PERFORMING ETCHING PROCESS - A method of performing an etching process is provided. A substrate is provided, wherein a first region and a second region are defined on the substrate, and an overlapping region of the first region and the second region is defined as a third region. A tri-layer structure comprising an organic layer, a bottom anti-reflection coating (BARC), and a photoresist layer is formed on the substrate. The photoresist layer and the BARC in the second region are removed. An etching process is performed to remove the organic layer in the second region by using the BARC and/or the photoresist layer as a mask, wherein the etching process uses an etchant comprises CO | 07-30-2015 |
20150206894 | SEMICONDUCTOR STRUCTURE AND LAYOUT STRUCTURE FOR MEMORY DEVICES - A layout structure for memory devices includes a plurality of first gate patterns, a plurality of first landing pad patterns, a plurality of dummy patterns, a plurality of second landing pad patterns, and a plurality of second gate patterns. The first landing pad patterns are parallel with each other and electrically connected to the first gate patterns. The dummy patterns and the first landing pad patterns are alternately arranged, and the second landing pad patterns are respectively positioned in between one first landing pad pattern and one dummy pattern. The second gate patterns are electrically connected to the second landing pad patterns. | 07-23-2015 |
20150206810 | STACKED SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - A stacked semiconductor structure and a manufacturing method for the same are provided. The stacked semiconductor structure is provided, which comprises a first semiconductor substrate, a second semiconductor substrate, a dielectric layer, a trench, a via, and a conductive structure. The first semiconductor substrate comprises a first substrate portion and a first conductive layer on an active surface of the first substrate portion. The second semiconductor substrate comprises a second substrate portion and a second conductive layer on an active surface of the second substrate portion. The trench passes through the second substrate portion and exposing the second conductive layer. The via passes through the dielectric layer and exposes the first conductive layer. The conductive structure has an upper portion filling the trench and a lower portion filling the via. Opposing side surfaces of the upper portion are beyond opposing side surfaces of the lower portion. | 07-23-2015 |
20150206803 | METHOD OF FORMING INTER-LEVEL DIELECTRIC LAYER - A method of forming an inter-level dielectric layer including the following step is provided. Two gate structures are formed on a substrate. A first oxide layer is formed to conformally cover the two gate structures and the substrate. The first oxide layer is etched ex-situ by a high density plasma (HDP) etching process. A second oxide layer is formed in-situ on the first oxide layer and fills a gap between the two gate structures by a high density plasma (HDP) depositing process. | 07-23-2015 |
20150206759 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is disposed between two sub-fin structures, and a top surface of each sub-fin structure is lower than a top surface of the fin group; and a shallow trench isolation (STI) disposed in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation. | 07-23-2015 |
20150200626 | VCO RESTART UP CIRCUIT AND METHOD THEREOF - A circuit and a method for restarting up a VCO of a PLL are introduced herein. The VCO restart up circuit receives a power down signal, an external signal, a clock output from the VCO and generates a trigger signal to the VCO to trigger the VCO clock to leave a stable mode. In other words, if the VCO clock is in the stable mode, the VCO restart up circuit generates one or more than one pulse on a trigger signal to restart up the VCO. Oppositely, if the VCO is not in the stable mode, there is no pulse on the trigger signal generated by the VCO restart up circuit and the VCO needs not to be restarted up. | 07-16-2015 |
20150200514 | METHOD FOR CALIBRATING A PLURALITY OF PINCETTES OF A WAFER CONVEYER - Calibrating a plurality of pincettes of a wafer conveyer includes installing a first pincette on two first components moveably installed on two first guiding tracks formed along a horizontal direction, installing a second pincette on two second components moveably installed on two second guiding tracks formed along the horizontal direction, disposing a first disc formed with three positioning components on a first holding portion of the first pincette, disposing a second disc formed with three positioning rings on a second holding portion of the second pincette, positioning three poles on the three positioning components through the three positioning rings, and fine tuning relative positions between the first pincette and the two first components and relative positions between the second pincette and the two second components to position the first pincette and the second pincette to horizontal levels according to indications of inclinometers disposed on three beams connecting the three poles. | 07-16-2015 |
20150200279 | METHOD OF MANUFACTURING MEMORY CELL - A method of manufacturing a memory cell is provided. First, a substrate is provided. A patterned dielectric layer and a patterned first conductive layer are formed on the substrate. Then, a charge trapping structure and a main gate are formed on a sidewall of the patterned dielectric layer and the patterned first conductive layer. A portion of the patterned first conductive layer and a portion of the patterned dielectric layer are removed until exposing the substrate. Next, at least a source/drain region is formed in the substrate. | 07-16-2015 |
20150200192 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor structure, including a substrate, having a dielectric layer disposed thereon, a first device region and a second device region defined thereon, at least one first trench disposed in the substrate within the first device region, at least one second trench and at least one third trench disposed in the substrate within the second device region, a work function layer, disposed in the second trench and the third trench, wherein the work function layer partially covers the sidewall of the second trench, and entirely covers the sidewall of the third trench, and a first material layer, disposed in the second trench and the third trench, wherein the first material layer covers the work function layer disposed on partial sidewall of the second trench, and entirely covers the work function layer disposed on the sidewall of the third trench. | 07-16-2015 |
20150200161 | E-FUSE CIRCUIT AND METHOD FOR PROGRAMMING THE SAME - An electronic-fuse (e-fuse) circuit includes: an e-fuse array; a control switch, coupled to the e-fuse array, for controlling whether a voltage supply is applied to the e-fuse array in programming; and a close loop feedback circuit, coupled to the control switch and the e-fuse array, for clamping at lease one node voltage of the e-fuse array to a reference voltage, and for controlling the control switch to control a blowing current in programming the e-fuse array. | 07-16-2015 |
20150193573 | METHOD FOR GENERATING LAYOUT OF PHOTOMASK - A method for generating a layout pattern of integrated circuit (IC) is provided. First, feature patterns are provided to a computer system and dummy pad patterns are generated in a space among the feature patterns. The layout pattern is then split into first feature patterns and second feature patterns. The dimensions of the first feature patterns are less than the dimensions of the second feature patterns. Afterwards, the dummy pad patterns are combined with the second features pattern to form a combined pattern. Then, mandrel patterns are generated in a space between the first feature patterns and the geometric patterns are generated according to the positions of the first feature patterns. Finally, the combined pattern, the mandrel patterns, and the geometric patterns are respectively outputted to form a first, a second, and a third photomasks. | 07-09-2015 |
20150187933 | LATERAL DOUBLE-DIFFUSED METAL-OXIDE-SEMICONUDCTOR TRANSISTOR DEVICE AND LAYOUT PATTERN FOR LDMOS TRANSISTOR DEVICE - A LDMOS transistor device includes a substrate including a first insulating structure formed therein, a gate formed on the substrate and covering a portion of the first insulating structure, a drain region and a source region formed in the substrate at two respective sides of the gate, a base region encompassing the source region, and a doped layer formed under the base region. The drain region and the source region include a first conductivity type, the base region and the doped layer include a second conductivity type, and the second conductivity type is complementary to the first conductivity type. A top of the doped layer contacts a bottom of the base region. A width of the doped layer is larger than a width of the base region. | 07-02-2015 |
20150187832 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating image sensor is disclosed. The method includes the steps of: providing a substrate having a dielectric layer thereon; forming a plurality of filtering layers on the dielectric layer; patterning the filtering layers for forming a first pass filter; coating a material layer on the dielectric layer such that a top surface of the material layer is even with a top surface of the first pass filter; and forming a plurality of color filters on the first pass filter. | 07-02-2015 |
20150179779 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming same are provided. The semiconductor structure includes a bipolar transistor. The bipolar transistor includes a base doped contact, an emitter doped contact, a collector doped contact, and well regions. The base doped contact, the emitter doped contact and the collector doped contact are formed in the different well regions having different dopant conditions from each other. | 06-25-2015 |
20150179748 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region. | 06-25-2015 |
20150179580 | HYBRID INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating hybrid interconnect structure is disclosed. The method includes the steps of: providing a material layer; forming a through-silicon hole in the material layer; forming a patterned resist on the material layer, wherein the patterned resist comprises at least an opening for exposing the through-silicon hole; and forming a conductive layer to fill the through-silicon hole and the opening in the patterned resist. | 06-25-2015 |
20150179516 | INTEGRATED STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating integrated structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon hole in the substrate; forming a patterned resist on the substrate, wherein the patterned resist comprises at least one opening corresponding to a redistribution layer (RDL) pattern and exposing the through-silicon hole and at least another opening corresponding to another redistribution layer (RDL) pattern and connecting to the at least one opening; and forming a conductive layer to fill the through-silicon hole, the at least one opening and the at least another opening in the patterned resist so as to form a through-silicon via, a through-silicon via RDL pattern and another RDL pattern in one structure. | 06-25-2015 |
20150176725 | SUPPORTING ASSEMBLY AND METHOD FOR USING THE SAME - A supporting assembly configured to support a plurality of tubes includes a first supporting rod, a second supporting rod opposite to the first supporting rod, a bridging member, and a rolling member. The first supporting rod includes several first parallel recesses. The bridging member is connected to one end of the first supporting rod or one end of the second supporting rod. The rolling member is received by the bridging member. | 06-25-2015 |
20150162419 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes the following steps. A substrate including at least a fin structure is provided, and a material layer is formed to cover the fin structure. Then, a first planarization process is performed on the material layer to form a first material layer, and an oxide layer is formed on the first material layer. Subsequently, the oxide layer is totally removed to expose the first material layer, and a second material layer is formed in-situ on the first material layer after totally removing the oxide layer. | 06-11-2015 |
20150155321 | SEMICONDUCTOR SENSOR DEVICE - A semiconductor sensor device is disclosed. The semiconductor sensor device includes a plurality of pixels and a phase grating structure. The phase grating structure has periodically arranged patterns and is disposed on the pixels. | 06-04-2015 |
20150155209 | METHOD FOR GENERATING DIE IDENTIFICATION BY MEASURING WHETHER CIRCUIT IS ESTABLISHED IN A PACKAGE STRUCTURE - A package structure is disclosed. The package structure includes a die; a substrate disposed corresponding to the die, wherein the substrate comprises a first dummy pad and a second dummy pad on a first surface of the substrate; and a first solder ball and a second solder ball on a second surface of the substrate and electrically connect the first dummy pad and the second dummy pad respectively. | 06-04-2015 |
20150147874 | METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE - The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin. | 05-28-2015 |
20150145067 | FIN STRUCTURE - A fin structure includes a substrate and a fin disposed on a top surface of the substrate. The fin has a height. An epitaxial structure surrounds the fin and the epitaxial structure has a top point which is the farthest point on the epitaxial structure away from the top surface of the substrate. There is a distance between the top point and the top surface of the substrate. A rational number of the distance to the height is not less than 7. | 05-28-2015 |
20150145027 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided according to one embodiment of the present invention and includes forming an interlayer dielectric on a substrate; forming a trench surrounded by the interlayer dielectric; depositing a dielectric layer and a work function layer on a surface of the trench sequentially and conformally; filling up the trench with a conductive layer; removing an upper portion of the conductive layer inside the trench; forming a protection film on a top surface of the interlayer dielectric and a top surface of the conductive layer through a directional deposition process; removing the dielectric layer exposed from the protection film; and forming a hard mask to cover the protection film. | 05-28-2015 |
20150140819 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate having trenches with different sizes is provided. A first oxide layer is formed to entirely cover the substrate. A prevention layer is formed on the first oxide layer. A first filling layer is formed on the prevention layer and fills the trenches until the first filling layer is higher than the substrate. A first polishing process is performed to polish the first filling layer until exposing the prevention layer. A second polishing process is performed to polish the first filling layer, the prevention layer and the first oxide layer until the substrate is exposed. | 05-21-2015 |
20150140800 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided. Subsequently, two spacers and a protective layer are formed on the conductive layer, and the two spacers and the protective layer jointly surround the protruded first gate stack layer and the protruded second gate stack layer. The two spacers and the protective layer are used as a mask to remove a part of the conductive layer. Afterwards, the two spacers and the protective layer are removed. | 05-21-2015 |
20150140780 | METHOD FOR FABRICATING SHALLOW TRENCH ISOLATION STRUCTURE - A method for fabricating shallow trench isolation structure is disclosed. The method includes the steps of: (a) providing a substrate; (b) forming a trench in the substrate; (c) forming a silicon layer in the trench; and (d) performing an oxidation process to partially transform a surface of the silicon layer into an oxide layer. | 05-21-2015 |
20150137323 | METHOD FOR FABRICATING THROUGH SILICON VIA STRUCTURE - A method for fabricating through silicon via (TSV) structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon via (TSV) in the substrate; depositing a liner in the TSV; removing the liner in a bottom of the TSV; and filling a first conductive layer in the TSV for forming a TSV structure. | 05-21-2015 |
20150137255 | SEMICONDUCTOR DEVICE - A semiconductor device is described, including a substrate including a first area and a second area, a first MOS element of a first conductivity type in the first area, and a second MOS element of the first conductivity type in the second area. The first area is closer to a pick-up region of the substrate than the second area. The substrate has a second conductivity type. The bottom depth of a first electrical conduction path in the substrate in the first area is smaller than that of a second electrical conduction path in the substrate in the second area. | 05-21-2015 |
20150137230 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF - A laterally diffused metal oxide semiconductor (LDMOS) and a manufacturing method thereof are provided. The LDMOS includes a substrate, a gate, a first well and a shallow trench isolation (STI). The gate is disposed above the substrate. The gate has a first gate region having a first dopant type and a second gate region having a second dopant type. The first well is disposed in the substrate. The STI is contacted with the first well and partially overlaps with the gate. | 05-21-2015 |
20150137228 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1. | 05-21-2015 |
20150137176 | SEMICONDUCTOR POWER DEVICE - A semiconductor power device is provided, comprising a substrate of a first conductive type, a buffering layer of a second conductive type formed on the substrate, a voltage supporting layer formed on the buffering layer, and alternating sections of different conductive types formed at the substrate. The voltage supporting layer comprises first semiconductor regions of the first conductive type and second semiconductor regions of the second conductive type, wherein the first semiconductor regions and the second semiconductor regions are alternately arranged. The alternating section and the buffering layer form a segmented structure of alternated conductive types, which is used as an anode of the semiconductor device. | 05-21-2015 |
20150137003 | SPECIMEN PREPARATION METHOD - A method of preparing ultra-thin TEM specimens is provided by flipping the sample upside down for FIB thinning Such preparation method is compatible with the ex-situ lift-out system and offers high quality TEM specimens without the curtaining effect. | 05-21-2015 |
20150136958 | LIGHT DETECTING DEVICE - A light detecting device is provided, comprising a substrate having a patterned metal layer formed thereon; a dielectric layer formed on the substrate, first pixel element formed on the dielectric layer, and a second pixel element. The dielectric layer at least has a first trench, and the first trench is positioned below the level of the first pixel element. The second pixel element comprises a buried portion formed correspondingly to the first trench, and an upper portion formed on the buried portion. The upper portion of the second pixel element is positioned at the same level of the first pixel element. | 05-21-2015 |
20150130016 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device and a manufacturing method thereof are disclosed. The semiconductor device includes a silicon substrate, a spacer, a doped region, and a deep trench isolation (DTI). The silicon substrate has a deep trench. The spacer is formed on an upper portion of the sidewall of the deep trench. The doped region is formed on a lower portion of the sidewall of the deep trench. The deep trench isolation is formed in the deep trench. | 05-14-2015 |
20150129980 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure comprises a substrate, a plurality of fins, an oxide layer and a gate structure. The fins protrude from the substrate and are separated from each other by the oxide layer. The surface of the oxide layer is uniform and even plane. The gate structure is disposed on the fins. The fin height is distance between the top of the fins and the oxide layer, and at least two of the fins have different fin heights. | 05-14-2015 |
20150129942 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. A semiconductor structure includes a device substrate, a conductive film, a dielectric film and a conductive plug. The device substrate includes a semiconductor substrate and a conductive structure on an active surface of the semiconductor substrate. The device substrate has a substrate opening passing through the semiconductor substrate and exposing the conductive structure. The conductive film, the conductive plug and the dielectric film between the conductive film and the conductive plug are disposed in the substrate opening. | 05-14-2015 |
20150125063 | METHOD OF OPTICAL PROXIMITY CORRECTION - A calculation method of optical proximity correction includes providing at least a feature pattern to a computer system. At least a first template and a second template are defined so that portions of the feature pattern are located in the first template and the rest of the feature pattern is located in the second template. The first template and the second template have a common boundary. Afterwards, a first calculation zone is defined to overlap an entire first template and portions of the feature pattern out of the first template. Edges of the feature pattern within the first calculation zone are then fragmented from the common boundary towards two ends of the feature pattern so as to generate at least two first beginning segments respectively at two sides of the common boundary. Finally, positions of the first beginning segments are adjusted so as to generate first adjusted segments. | 05-07-2015 |
20150123210 | EPITAXIAL STRUCTURE AND PROCESS THEREOF FOR NON-PLANAR TRANSISTOR - An epitaxial structure for a non-planar transistor is provided. A substrate has a fin-shaped structure. A gate is disposed across the fin-shaped structure. A silicon germanium epitaxial structure is disposed on the fin-shaped structure beside the gate, wherein the silicon germanium epitaxial structure has 4 <1,1,1> surfaces and its aspect ratio of width and thickness is at a range of 1:1˜1.3. A method for forming said epitaxial structure is also provided. | 05-07-2015 |
20150123197 | LATERAL-DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A lateral-diffused metal oxide semiconductor device including a substrate, a second deep well, a gate, a source, a drain and a first dopant region is provided. The substrate includes a first deep well having a first conductive type. The second deep well having a second conductive type is disposed in the first deep well. The gate is disposed on the substrate and the boundary of the first and the second deep well. The source and the drain having a second conductive type are disposed beside the gate and in the first deep well and the second deep well respectively. The first dopant region having a first conductive type is disposed in the second deep well, wherein the first dopant region is separated from the drain. Moreover, a method for fabricating said lateral-diffused metal oxide semiconductor device is also provided. | 05-07-2015 |
20150123184 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICE - A CMOS device includes a substrate, a pMOS transistor and an nMOS transistor formed on the substrate, and a gated diode. The gated diode includes a floating gate formed on the substrate in between the pMOS transistor and the nMOS transistor and a pair of a p-doped region and an n-doped region formed in the substrate and between the pMOS transistor and the nMOS transistor. The n-doped region is formed between the floating gate and the nMOS transistor, and the p-doped region is formed between the floating gate and the pMOS transistor. | 05-07-2015 |
20150123130 | TEST KEY STRUCTURE - A test key structure is provided. The test key structure comprises at least one semiconductor element. Each of the at least one semiconductor element including a well, a source region, a drain region and a gate. The source region is disposed in the well. The drain region is disposed in the well and separated from the source region. The gate is disposed above the well. The source region, the drain region and the well have the same type of doping. | 05-07-2015 |
20150118836 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is disclosed. Provided is a substrate having a dummy gate formed thereon, a spacer on a sidewall of the dummy gate and a first dielectric layer surrounding the spacer. The dummy gate is removed to form a gate trench. A gate dielectric layer and at least one work function layer is formed in the gate trench. The work function layer and the gate dielectric layer are pulled down, and a portion of the spacer is laterally removed at the same time to widen a top portion of the gate trench. A low-resistivity metal layer is formed in a bottom portion of the gate trench. A hard mask layer is formed in the widened top portion of the gate trench. | 04-30-2015 |
20150118835 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized. | 04-30-2015 |
20150118602 | PHOTOMASK AND FABRICATION METHOD THEREOF - A photomask including first opaque patterns and second opaque patterns is provided. The first opaque patterns are distributed in a first plane defined in the photomask, while the second opaque patterns are disposed above the first opaque patterns and spaced apart from the first opaque patterns. In other words, the first opaque pattern and second opaque pattern are not distributed in the same plane. | 04-30-2015 |
20150115461 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The method includes following steps. A first wafer is provided, which includes a first region, a second region, and a first semiconductor device disposed in the first region. No semiconductor device is disposed in the second region. A second wafer is provided, which includes a third region, a fourth region and a second semiconductor device disposed in the third region. No semiconductor device is disposed in the fourth region. The first region of the first wafer is overlapped with the fourth region of the second wafer. The second region of the first wafer is overlapped with the third region of the second wafer. A first conductive through via is formed to pass through the fourth region of the second wafer and the first region of the first wafer to electrically connect to the first semiconductor device. | 04-30-2015 |
20150115346 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes a substrate, shallow trench isolations protruding from the substrate, a floating gate formed conformally on the surface of the recess between each shallow trench isolation, a tunnel layer formed between each floating gate and the substrate, a dielectric layer formed conformally on the floating gates, and a control gate formed on the dielectric layer. | 04-30-2015 |
20150112623 | STRUCTURE FOR MEASURING DOPING REGION RESISTANCE AND METHOD OF MEASURING CRITICAL DIMENSION OF SPACER - A method of the measuring a critical dimension of a spacer is provided. The measurement is performed by using several test structures of measuring doping region resistance. Each of the test structure has different space disposed between a first gate line and a second gate line. By measuring a doping region resistance of each test structure, a plot of reciprocal of resistance versus space can be accomplished. Then, making regression of the plot, a correlation can be formed. Finally, a critical dimension of a spacer can be get by extrapolating the correlation back to 0 unit of reciprocal of resistance. | 04-23-2015 |
20150109590 | SCANNER ROUTING METHOD FOR PARTICLE REMOVAL - A scanner routing method for particle removal is disclosed. A dummy wafer coated with a viscosity builder is provided. The dummy wafer is moved, shot by shot, with an immersion scanner. The said moving includes moving edge shots in a direction from the outside of the dummy wafer toward the inside of the same. The scanner routing method of the invention is beneficial to remove unnecessary particles or chemicals in the immersion liquid and therefore improve the performance of the product wafer which is subsequently run after the dummy wafer. | 04-23-2015 |
20150108587 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The method includes following steps. A gate electrode layer is formed on a substrate. A spacer structure is formed on a sidewall of the gate electrode layer. A dielectric cap film is formed to cover the gate electrode layer and the spacer structure. A source/drain implantation is performed to the substrate with the dielectric cap film exposed to a condition of the source/drain implantation. | 04-23-2015 |
20150104943 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE - A method for forming a semiconductor structure. A dielectric layer including adjacent first and second dielectric regions is formed on a substrate. The dielectric layer includes a curable material. The first dielectric region is cured. A portion of the second dielectric region is etched to form an opening and leave a remaining portion of the second dielectric region. After the etching step, the remaining portion of the second dielectric region is cured. | 04-16-2015 |
20150103585 | High stability static random access memory cell - A Static Random Access Memory (SRAM) cell is a latch circuit formed with two inverters each formed with a PMOS transistor and an NMOS transistor. The latch circuit is coupled to a capacitor through a switch. When the switch is switched on, the stability of data stored in the SRAM cell will be enhanced. When the switch is switched off, data can be written to the SRAM cell quickly. | 04-16-2015 |
20150096590 | METHOD FOR CLEANING QUARTZ REACTION TUBE - A method for cleaning quartz reaction tube is disclosed. The method includes the steps of: introducing a quartz reaction tube to a cleaning chamber, wherein the quartz reaction tube comprises a first end and a second end; sealing the first end and the second end of the quartz reaction tube with a first sealing element and a second sealing element respectively, wherein the first sealing element is coupled to an input pipe and a cleaning rod, and the second sealing element is coupled to an output pipe; supplying a first cleaning agent into the quartz reaction tube from the input pipe; utilizing the cleaning rod to perform a cleaning process; and expelling the first cleaning agent from the output pipe. | 04-09-2015 |
20150095728 | TESTING METHOD FOR REDUCING NUMBER OF OVERKILLS BY REPEATEDLY WRITING DATA TO ADDRESSES IN A NON-VOLATILE MEMORY - A testing method for non-volatile memory includes writing a first set of data to a set of addresses in a non-volatile memory, reading a second set of data from the set of addresses, and writing the first set of data to the set of addresses again if the first set of data and the second set of data are not identical and number of times for writing the first set of data to the set of addresses is smaller than a predetermined number. | 04-02-2015 |
20150093870 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE STRUCTURE - A method of fabricating a semiconductor device structure is provided. The method includes the following step. A gate dielectric layer is formed on a substrate. A gate electrode is on the gate dielectric layer. The gate dielectric layer exposed by the gate electrode is treated. A first etching process is performed to remove at least a portion of the gate dielectric layer exposed by the gate electrode. A spacer is formed on the sidewall of the gate electrode. A second etching process is performed to form recesses in the substrate beside the gate electrode. Besides, during the first etching process and the second etching process, an etching rate of the treated gate dielectric layer is greater than an etching rate of the untreated gate dielectric layer. | 04-02-2015 |
20150091159 | SEMICONDUCTOR DEVICE WITH FINE CONDUCTIVE PILLAR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. A semiconductor device comprises a substrate, a conductive pattern formed on the substrate, and at least a conductive pillar having a predetermined height formed on the conductive pattern. The conductive pillar can be formed under a focus ion beam (FIB) or an electron beam environment. In one embodiment, a diameter of the conductive pillar is no more than 10 μm. | 04-02-2015 |
20150091059 | PROCESS FOR FABRICATING FIN-TYPE FIELD EFFECT TRANSISTOR (FinFET) STRUCTURE AND PRODUCT THEREOF - A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fm together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer. | 04-02-2015 |
20150085234 | LCOS DEVICE AND METHOD OF FABRICATING THE SAME - The present invention provides a LCOS device including a silicon substrate, a first dielectric layer, a first mirror layer, a second dielectric layer, and a second mirror layer. The first dielectric layer is disposed on the silicon substrate. The first mirror layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the first mirror layer. The second minor layer is disposed on the second dielectric layer. | 03-26-2015 |
20150079780 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor device is disclosed. A gate structure is formed on a substrate. The gate structure includes a dummy gate and a spacer at a sidewall of the dummy gate. A dielectric layer is formed on the substrate outside of the gate structure. A metal hard mask layer is formed to cover tops of the dielectric layer and the spacer and to expose a surface of the gate structure. The dummy gate is removed to form a gate trench. A low-resistivity metal layer is formed on the metal hard mask layer filling in the gate trench. The low-resistivity metal layer outside of the gate trench is removed. The metal hard mask layer is removed. | 03-19-2015 |
20150079777 | Method of Manufacturing Semiconductor Device Having Metal Gate - A method of manufacturing a semiconductor device having a metal gate is provided. A substrate having a first conductive type transistor and a second conductive type transistor formed thereon is provided. The first conductive type transistor has a first trench and the second conductive type transistor has a second trench. A first work function layer is formed in the first trench. A hardening process is performed for the first work function layer. A softening process is performed for a portion of the first work function layer. A pull back step is performed to remove the portion of the first work function layer. A second work function layer is formed in the second trench. A low resistive metal layer is formed in the first trench and the second trench. | 03-19-2015 |
20150079739 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A method for manufacturing a semiconductor substrate includes following steps. A wafer having a front side and a back side is provided. A plurality of gate structures at least a first insulating layer covering the gate structures are formed on the front side of the wafer. At least a polysilicon layer and a second insulating layer are formed on the back side of the wafer. Subsequently, at least a source/drain is formed in the front side of the wafer. Next, the second insulating layer is removed from the back side of the wafer. After removing the second insulating layer, the polysilicon layer is removed from the back side of the wafer. | 03-19-2015 |
20150076665 | ALIGNMENT MARK STRUCTURE - A conductive structure includes a wafer having a scribe line defined thereon, at least a first wiring layer formed in the scribe line, and at least a via layer disposed in the scribe line and under the wiring layer. The first wiring layer includes a main pattern and the via layer includes a closed frame pattern corresponding to the main pattern of the first wiring layer. | 03-19-2015 |
20150076623 | METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region. | 03-19-2015 |
20150074620 | METHOD OF MAKING PHOTOMASK LAYOUT AND METHOD OF FORMING PHOTOMASK INCLUDING THE PHOTOMASK LAYOUT - A method of making a photomask layout is provided. A graphic data of a photomask is provided. The graphic data includes at least one rectangular pattern. A correction step is performed to the graphic data by using a computer. The correction step includes adding a substantially ring-shaped pattern inside the rectangular pattern. A method of forming a photomask by using the photomask layout obtained by the said method is also provided. In an embodiment, the photomask is suitable for defining micro-lenses of a solid-state image sensor. | 03-12-2015 |
20150072532 | PATTERNING METHOD - A patterning method is provided. First, a material layer is formed over a substrate. Thereafter, a plurality of directed self-assembly (DSA) patterns are formed on the material layer. Afterwards, a patterned photoresist layer is formed by using a single lithography process. The patterned photoresist layer covers a first portion of the DSA patterns and exposes a second portion of the DSA patterns. Further, the material layer is patterned by an etching process, using the patterned photoresist layer and the second portion of the DSA patterns as a mask. | 03-12-2015 |
20150072531 | METHOD FOR FORMING LAYOUT PATTERN - A method for forming a layout pattern includes the following processes. First, a first layout pattern consisting of mandrel patterns and dummy mandrel patterns, a second layout pattern consisting of geometric patterns, and a third layout pattern consisting of pad patterns and dummy pad patterns, are respectively defined on a first mask, a second mask, and a third mask. Then, the first layout pattern is transferred to form a first patterned layer. Afterwards, spacers having a first critical dimension are formed on the sidewalls of the first patterned layer so as to constitute loop-shaped patterns. Then, the third layout pattern is transferred to form a second patterned layer having a second critical dimension, wherein the second critical dimension is greater than the first critical dimension. Finally, the loop-shaped patterns, the pad patterns, and the dummy pad patterns are transferred into a target layer on the substrate. | 03-12-2015 |
20150072272 | Method For Forming Photo-Mask And OPC Method - A method for forming a photo-mask is provided. A first photo-mask pattern relating to a first line, an original second photo-mask pattern relating to a first via plug, and a third photo-mask pattern relating to a second line are provided. A first optical proximity correction (OPC) process is performed. A second OPC process is performed, comprising enlarging a width of the second photo-mask pattern along the first direction to form a revised second photo-resist pattern. A contour simulation process is performed to make sure the revised second photo-mask pattern is larger or equal to the original second-mask pattern. The first photo-mask pattern, the revised second photo-mask pattern, and the third photo-mask pattern are output. The present invention further provides an OPC method. | 03-12-2015 |
20150069534 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer. | 03-12-2015 |
20150069533 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device having metal gate includes following steps. A substrate having at least a first semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench formed therein. Next, an n-typed work function metal layer is formed in the first gate trench. After forming the n-typed work function metal layer, a nitridation process is performed to form a first protecting layer on the n-typed work function metal layer. After forming the first protecting layer, an oxidation process is performed to the first protecting layer to form a second protecting layer on the n-typed work function metal layer. Then, a gap filling metal layer is formed to fill up the first gate trench. | 03-12-2015 |
20150064929 | METHOD OF GAP FILLING - A method of gap filling includes providing a substrate having a plurality of gaps formed therein. Then, an in-situ steam generation oxidation is performed to form an oxide liner on the substrate. The oxide liner is formed to cover surfaces of the gaps. Subsequently, a high aspect ratio process is performed to form an oxide protecting layer on the oxide liner. After forming the oxide protecting layer, a flowable chemical vapor deposition is performed to form an oxide filling on the oxide protecting layer. More important, the gaps are filled up with the oxide filling layer. | 03-05-2015 |
20150064905 | SEMICONDUCTOR PROCESS - A semiconductor process including the following steps is provided. A substrate is provided. A nitride layer is formed on the substrate, but exposing a silicon containing area. An oxidation process is performed to oxidize a surface of the silicon containing area to form an oxidized surface. The nitride layer is removed. | 03-05-2015 |
20150064896 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF | 03-05-2015 |
20150064869 | Method of forming Fin-FET - The present invention provides a method of forming Fin-FET. A substrate with an active region and a dummy region are defined thereon. A plurality of first fins and second fins are formed in the active region, and a plurality of dummy fins are formed in the dummy region and the active region. A first active region is provided in the active region. A revised first active region is formed by extending the first active region to cover at least one adjacent dummy fin. Next, a first dummy region is provided in the dummy region. A first mask layout is formed by combining the revised first active region and the first dummy region. A first patterned mask layer is formed by using the first mask layout. A first epitaxial process is performed for the first fins and the dummy fins exposed by the first patterned mask layer. | 03-05-2015 |
20150064861 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An underlayer is formed on the substrate to cover the first gate in the first region and the second gate in the second region. A patterned mask with a predetermined thickness is formed on the underlayer in the first region. The underlayer corresponding to the second gate in the second region is removed by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate. | 03-05-2015 |
20150061151 | PACKAGE STRUCTURE HAVING SILICON THROUGH VIAS CONNECTED TO GROUND POTENTIAL - A package structure having silicon through vias connected to ground potential is disclosed, comprising a first device, a second device and a conductive adhesive disposed between the first device and the second device. The first device comprises a substrate having a front surface and a back surface, and a plurality of through silicon vias filled with a conductor formed within the substrate. The first device is externally connected to the second device by wire bonding. | 03-05-2015 |
20150061042 | METAL GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A metal gate structure is provided. The metal gate structure includes a semiconductor substrate, a gate dielectric layer, a multi-layered P-type work function layer and a conductive metal layer. The gate dielectric layer is disposed on the semiconductor substrate. The multi-layered P-type work function layer is disposed on the gate dielectric layer, and the multi-layered P-type work function layer includes at least a crystalline P-type work function layer and at least an amorphous P-type work function layer. Furthermore, the conductive metal layer is disposed on the multi-layered P-type work function layer. | 03-05-2015 |
20150061041 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided. The dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench. A work function metal layer and a top barrier layer are sequentially formed in the gate trench. A treatment is performed to the top barrier layer so as to form a silicon-containing top barrier layer. A low-resistivity metal layer is formed in the gate trench. | 03-05-2015 |
20150060980 | PROGRAMMABLE DEVICE AND METHOD OF MANUFACTURING THE SAME - A programmable device and a method of manufacturing the same are provided. A programmable device comprises a substrate having a source region, a drain region and a diffusion region adjacent to the source region and the drain region; a channel coupling the source region and the drain region; a floating gate formed of a conductive material and positioned on the substrate and corresponding to the channel; and a trench formed in the diffusion region at the substrate, wherein the floating gate extends to the trench, and the conductive material covers a sidewall of the trench. | 03-05-2015 |
20150055125 | MEASUREMENT METHOD OF OVERLAY MARK - A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark. | 02-26-2015 |
20150054132 | LATERAL BIPOLAR JUNCTION TRANSISTOR AND FABRICATION METHOD THEREOF - Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region. | 02-26-2015 |
20150052491 | METHOD FOR GENERATING LAYOUT PATTERN - A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns. | 02-19-2015 |
20150050751 | METHOD OF CONTROLLING THRESHOLD VOLTAGE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of controlling a threshold voltage is provided. The method of controlling a threshold voltage includes performing a film-thickness measuring step to measure the thickness of a film layer on a wafer to obtain a film-thickness value. Then, at least one parameter is decided, selected, or generated according to the film-thickness value. Next, an ion implantation process is performed on the wafer, wherein the ion implantation process is executed according to the parameter to form a threshold voltage adjustment region in the wafer below the film layer. | 02-19-2015 |
20150048482 | SEMICONDUCTOR CAPACITOR - A semiconductor capacitor is includes a substrate, a plurality of odd layers formed on the substrate, and a plurality of even layers formed on the substrate. Each odd layer includes a plurality of first odd fingers and a first odd terminal electrically connected thereto, and a plurality of second odd fingers and a second odd terminal electrically connected thereto. Each even layer includes a plurality of first even fingers and a first even terminal electrically connected thereto, and a plurality of second even fingers and a second even terminal electrically connected thereto. The semiconductor capacitor further includes at least a first odd connecting structure electrically connecting the first odd terminals, at least a second odd connecting structure electrically connecting the second odd terminals, at least a first even connecting structure electrically connecting the first even terminals, and at least a second even connecting structure electrically connecting the second even terminals. | 02-19-2015 |
20150044879 | REMOVING METHOD - A removing method including the following steps. A substrate is transferred into an etching machine, wherein the substrate has a material layer formed thereon. A cycle process is performed. The cycle process includes performing an etching process to remove a portion of the material layer, and performing an annealing process to remove a by-product generated by the etching process. The cycle process is repeated at least one time. The substrate is transferred out of the etching machine. In the removing method of the invention, the cycle process is performed multiple times to effectively remove the undesired thickness of the material layer and reduce the loading effect. | 02-12-2015 |
20150044875 | METHOD OF FORMING PATTERN - A method of forming a pattern is disclosed. First, N kinds of different photomask patterns are provided. Thereafter, the N kinds of different photomask patterns are transferred to a hard mask layer by using at least N−1 kinds of light sources with different wavelengths, so as to form a hard mask pattern, wherein one of the at least N−1 kinds of light sources with different wavelengths is a light source with a wavelength of 193 nm, and N is an integer of three or more. | 02-12-2015 |
20150044831 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A first gate and a second gate are formed on a substrate. A first stress layer is formed to cover the first gate and the second gate. The first stress layer covering the first gate is etched to form a first spacer beside the first gate, but reserves the first stress layer covering the second gate. A first epitaxial layer is formed beside the first spacer. The first stress layer and the first spacer are entirely removed. A second stress layer is formed to cover the first gate and the second gate. The second stress layer covering the second gate is etched to form a second spacer beside the second gate, but reserves the second stress layer covering the first gate. A second epitaxial layer is formed beside the second spacer. The second stress layer and the second spacer are entirely removed. | 02-12-2015 |
20150041952 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes an interposer structure. The interposer structure includes an interposer substrate, a ground, through vias, a dielectric layer, and an inductor. The through vias are formed in the interposer substrate and electrically connected to the ground. The dielectric layer is on the interposer substrate. The inductor is on the dielectric layer. | 02-12-2015 |
20150041855 | SEMICONDUCTOR DEVICE - A semiconductor device includes at least two fin-shaped structures, a gate structure, at least two epitaxial structures and a silicon cap. The fin-shaped structures are disposed on a substrate and are covered by the gate structure. The epitaxial structures are disposed at one side of the gate structure and respectively directly contact each fin-shaped structure, wherein the epitaxial structures are spaced apart from each other. The silicon cap simultaneously surrounds the epitaxial structures. | 02-12-2015 |
20150037974 | METHOD OF PATTERNING PLATINUM LAYER - A method of patterning a platinum layer includes the following steps. A substrate is provided. A platinum layer is formed on the substrate. An etching process is performed to pattern the platinum layer, wherein an etchant used in the etching process simultaneously includes at least a chloride-containing gas and at least a fluoride-containing gas. | 02-05-2015 |
20150036116 | APERTURE FOR PHOTOLITHOGRAPHY - An aperture is configured to be disposed between an illumination source and a semiconductor substrate in a photolithography system. The aperture includes a light-transmission portion with a non-planar thickness profile to compensate the discrepancy of wave-fronts of the light beams of different orders. | 02-05-2015 |
20150035069 | FINFET AND METHOD FOR FABRICATING THE SAME - A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure in the substrate; forming a shallow trench isolation (STI) on the substrate and around the bottom portion of the fin-shaped structure; forming a first gate structure on the STI and the fin-shaped structure; and removing a portion of the STI for exposing the sidewalls of the STI underneath the first gate structure. | 02-05-2015 |
20140354325 | SEMICONDUCTOR LAYOUT STRUCTURE AND TESTING METHOD THEREOF - A semiconductor layout structure and a testing method thereof are disclosed. The semiconductor layout structure includes a device under test (DUT), a first testing pad, a second testing pad and a plurality of third testing pads. The DUT includes a plurality of metal-oxide-semiconductor (MOS) transistors. Each of the MOS transistors includes a first terminal, a second terminal and a third terminal. The first testing pad is coupled to the first terminals for being applied a first voltage. The second testing pad is coupled to the second terminals for being applied a second voltage. The third testing pads are respectively coupled to the third testing pads for being applied a third voltage. The third testing pads are electrical insulated from each other. The third voltage is larger than the first voltage and the second voltage. | 12-04-2014 |
20140353787 | IMAGE SENSOR AND PROCESS THEREOF - An image sensor including a microlens, a substrate, a first dielectric layer, a second dielectric layer and a color filter is provided. The microlens receives light; the substrate includes a light sensing element in a light sensing area for receiving light incident to the microlens. The first dielectric layer and the second dielectric layer are stacked on the substrate from bottom to top, wherein the second dielectric layer has a recess on the first dielectric layer and in an optical path between the microlens and the light sensing element. The color filter is disposed in the recess. Moreover, the present invention also provides an image sensing process for forming said image sensor. | 12-04-2014 |
20140353729 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The method comprises following steps. A gate material film is formed on a substrate in a first device region and a second device region. The gate material film in the first device region is patterned to form a first patterned gate. A first spacer material film containing a nitride material is formed on the first patterned gate in the first device region and the gate material film in the second device region. The first spacer material film and the gate material film are patterned in the second device region to form a second patterned gate. | 12-04-2014 |
20140349467 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface. | 11-27-2014 |
20140349452 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES - A method for manufacturing a semiconductor device is provided. A first stack structure and a second stack structure are formed to respectively cover a portion of a first fin structure and a second fin structure. Subsequently, a spacer is respectively formed on the sidewalls of the fin structures through an atomic layer deposition process and the composition of the spacers includes silicon carbon nitride. Afterwards, a interlayer dielectric is formed and etched so as to expose the hard mask layers. A mask layer is formed to cover the second stack structure and a portion of the dielectric layer. Later, the hard mask layer in the first stack structure is removed under the coverage of the mask layer. Then, a dummy layer in the first stack structure is replaced with a conductive layer. | 11-27-2014 |
20140349236 | Method for Forming Semiconductor Structure Having Opening - A method for forming a semiconductor structure having an opening is provided. First, a substrate is provided, wherein a first region and a second region are defined on the substrate and an overlapping area of the first region and the second region is defined as a third region. A pattern density of the first region is substantially greater than that of the second region. Then, a material layer is formed on the substrate. A first hard mask and a second hard mask are formed on the material layer. The first hard mask in the first region is removed to form a patterned first hard mask. The second hard mask in the third region is removed to form a patterned second hard mask. Lastly, the material layer is patterned by using the patterned second hard mask layer as a mask to form at least an opening in the third region only. | 11-27-2014 |
20140346645 | THROUGH SILICON VIA AND PROCESS THEREOF - A through silicon via includes a substrate and a conductive plug. The substrate has a hole in a side. The conductive plug is disposed in the hole, and the conductive plug having an upper part protruding from the side, wherein the upper part has a top part and a bottom part, and the top part is finer than the bottom part. Moreover, a through silicon via process formed said through silicon via is also provided, which includes the following step. A hole is formed in a substrate from a side. A first conductive material is formed to cover the hole and the side. A patterned photoresist is formed to cover the side but exposing the hole. A second conductive material is formed on the exposed first conductive material. The patterned photoresist is removed. The first conductive material on the side is removed to form a conductive plug in the hole. | 11-27-2014 |
20140343880 | METHOD FOR DERIVING CHARACTERISTIC VALUES OF MOS TRANSISTOR - A method for deriving characteristic values of a MOS transistor is described. A set of η | 11-20-2014 |
20140342553 | Method for Forming Semiconductor Structure Having Opening - According to one embodiment of the present invention, a method for forming a semiconductor structure having an opening is provided. First, a substrate is provided, wherein a first region and a second region are defined on the substrate and an overlapping area of the first region and the second region is defined as a third region. Then, a material layer is formed on the substrate. A first hard mask and a second hard mask are formed on the material layer. The first hard mask in the first region is removed to form a patterned first hard mask. The second hard mask in the third region is removed to form a patterned second hard mask. Lastly, the material layer is patterned by using the patterned second hard mask layer as a mask to form at least an opening in the third region only. | 11-20-2014 |
20140342473 | SEMICONDUCTOR PROCESSING METHOD - A method for detecting metal contamination from a film-forming process causing interface traps is described. The film-forming process is performed to form a dielectric film on a wafer. An annealing treatment is performed to reduce the interface traps between the wafer and the dielectric film. Thereafter, the bulk recombination lifetime (BRLT) of the wafer is measured to estimate the amount of the metal contamination. | 11-20-2014 |
20140339641 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a substrate, a first fin structure, an electrical contact structure and a gate structure. The first fin structure includes a horizontal fin structure extending along a first direction and a vertical fin structure extending along a second direction. The substrate has a first region and a second region. A portion of the horizontal fin structure and the vertical fin structure are disposed in the first region, and the electrical contact structure directly covers the horizontal fin structure and the vertical fin structure within the first region. The gate structure partially overlaps the horizontal fin structure within the second region. | 11-20-2014 |
20140339636 | HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE - A high voltage metal-oxide-semiconductor (HV MOS) transistor device includes a substrate, a drifting region formed in the substrate, a plurality of isolation structures formed in the drift region and spaced apart from each other by the drift region, a plurality of doped islands respectively formed in the isolation structures, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective two sides of the gate. The gate covers a portion of each isolation structure. The drift region, the source region, and the drain region include a first conductivity type, the doped islands include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. | 11-20-2014 |
20140339632 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well and a second well respectively having the first and second conductive types formed in the deep well, and extending down from the surface of the substrate; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion comprising at least two fingers penetrating into the isolation, and the fingers spaced apart and electrically connected to each other. | 11-20-2014 |
20140335674 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device is provided. The method includes at least the following steps. A gate structure is formed on a substrate. An epitaxial structure is formed on the substrate, wherein the epitaxial structure comprises SiGe, and the Ge concentration in the epitaxial structure is equal to or higher than | 11-13-2014 |
20140332952 | SEMICONDUCTOR STRUCTURE AND METHOD FOR TESTING THE SAME - A semiconductor structure comprising a substrate, a dielectric layer, a conductor post, a first conductive layer structure and a second conductive layer structure is provided. The substrate comprises an opening structure. The dielectric layer is disposed on a sidewall of the opening structure. The conductor structure is disposed in the opening structure and covers the dielectric layer. The first and second conductive layer structures are electrically connected to the conductor post. A voltage difference is existed between the first and second conductive layer structures, such that a current is passing through the first conductive layer structure, the opening structure and second conductive layer structure. A resistance values is related to the voltage difference and the current. A dimension of the opening structure is 10 times greater than a dimension of the first and second conductive layer structures. | 11-13-2014 |
20140332868 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing semiconductor devices includes following steps. A substrate having a pixel region and a periphery region defined thereon is provided, and at least a transistor is formed in the pixel region. A blocking layer is formed on the substrate, and the blocking layer includes a first opening exposing a portion of the substrate in the pixel region and a second opening exposing a portion of the transistor. A first conductive body is formed in the first opening and a second conductive body is formed in the second opening, respectively. The first conductive body protrudes from the substrate and the second conductive body protrudes from the transistor. A portion of the blocking layer is removed. A first salicide layer is formed on the first conductive body and a second salicide layer is formed on the second conductive body, respectively. | 11-13-2014 |
20140331191 | METHOD OF CORRECTING ASSIST FEATURE - A method of correcting assist features includes the following steps. At first, a first layout pattern is received by a computer system, and the first layout pattern is split into a plurality of first regions. Subsequently, a plurality of assist features are added into the first layout pattern to form a second layout pattern, wherein at least one of the assist features neighboring any one of the edges of the first regions is defined as a selected pattern. Then, the second layout pattern is split into a plurality of second regions. Afterwards, a check step is performed on the second region including the selected pattern, and the second layout pattern is corrected to form a corrected second layout pattern. | 11-06-2014 |
20140327080 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a manufacturing method of a semiconductor structure, comprising the following steps. First, a substrate is provided, a first dielectric layer is formed on the substrate, a metal gate is disposed in the first dielectric layer and at least one source/drain region (S/D region) is disposed on two sides of the metal gate, a second dielectric layer is then formed on the first dielectric layer, a first etching process is then performed to form a plurality of first trenches in the first dielectric layer and the second dielectric layer, wherein the first trenches expose each S/D region. Afterwards, a salicide process is performed to form a salicide layer in each first trench, a second etching process is then performed to form a plurality of second trenches in the first dielectric layer and the second dielectric layer, and the second trenches expose the metal gate. | 11-06-2014 |
20140327074 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a substrate, a multi-gate transistor device formed on the substrate, and an n-well resistor formed in the substrate. The substrate includes a plurality of first isolation structures and at least a second isolation structure formed therein. A depth of the first isolation structures is smaller than a depth of the second isolation structure. The multi-gate transistor device includes a plurality of fin structures, and the fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The n-well resistor includes at least one first isolation structure. The n-well resistor and the multi-gate transistor device are electrically isolated from each other by the second isolation structure. | 11-06-2014 |
20140327055 | REPLACEMENT GATE PROCESS AND DEVICE MANUFACTURED USING THE SAME - A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench. | 11-06-2014 |
20140319693 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias. | 10-30-2014 |
20140319613 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a gate positioned on the substrate, a drain and a source formed in the substrate at respective two sides of the gate, and a doped region formed in the source. The drain and the source comprise a first conductivity type and the doped region comprises a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. | 10-30-2014 |
20140315365 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench. | 10-23-2014 |
20140308761 | Sidewall Image Transfer Process - A sidewall image transfer (SIT) process is provided. First, a substrate is provided. A sacrificial layer having a pattern is formed on the substrate. A first measuring step is performed to measure a width of the pattern of the sacrificial layer. A material layer is formed conformally on the sacrificial layer, wherein a thickness of the material layer is adjusted according to the result of the first measuring step. Then, the material layer is removed anisotropically, so the material layer becomes a spacer on a sidewall of the sacrificial layer. Lastly, the sacrificial layer is removed. | 10-16-2014 |
20140306273 | STRUCTURE OF METAL GATE STRUCTURE AND MANUFACTURING METHOD OF THE SAME - A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. Finally, the gate trench is filled up with a conductive metal layer. | 10-16-2014 |
20140306272 | METHOD OF FORMING A FINFET STRUCTURE - A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor. | 10-16-2014 |
20140304666 | METHOD OF OPTICAL PROXIMITY CORRECTION FOR MODIFYING LINE PATTERNS AND INTEGRATED CIRCUTS WITH LINE PATTERNS MODIFIED BY THE SAME - A method of optical proximity correction executed by a computer system and integrated circuit layout formed by the same, the step of optical proximity correction comprises: providing an integrated circuit layout with a plurality of parallel line patterns, wherein one side of at least one line pattern is provided with a convex portion; and modifying the integrated circuit layout by forming a concave portion corresponding to the convex portion at the other side of the line pattern. | 10-09-2014 |
20140302677 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURES - A method for manufacturing semiconductor structures includes providing a substrate having a plurality of mandrel patterns and a plurality of dummy patterns, simultaneously forming a plurality of first spacers on sidewalls of the mandrel patterns and a plurality of second spacers on sidewalls of the dummy patterns, and removing the second spacers and the mandrel patterns to form a plurality of spacer patterns on the substrate. | 10-09-2014 |
20140300391 | OUTPUT BUFFER - An output buffer includes an input/output end, a voltage source, a first transistor and a second transistor. The first transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The second transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The control end of the first transistor and the control end of the second transistor are substantially perpendicular to each other, and the punch through voltage of the first transistor is higher than the punch through voltage of the second transistor. | 10-09-2014 |
20140295650 | METHOD FOR FABRICATING PATTERNED STRUCTURE OF SEMICONDUCTOR DEVICE - A method of fabricating a patterned structure of a semiconductor device is provided. First, a substrate having a first region and a second region is provided. A target layer, a hard mask layer and a first patterned mask layer are then sequentially formed on the substrate. A first etching process is performed by using the first patterned mask layer as an etch mask so that a patterned hard mask layer is therefore formed. Spacers are respectively formed on each sidewall of the patterned hard mask layer. Then, a second patterned mask layer is formed on the substrate. A second etching process is performed to etch the patterned hard mask layer in the second region. After the exposure of the spacers, the patterned hard mask layer is used as an etch mask and an exposed target layer is removed until the exposure of the corresponding substrate. | 10-02-2014 |
20140295629 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses. | 10-02-2014 |
20140284720 | SEMICONDUCTOR DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION - A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed at respective two sides of the gate in the substrate, at least a first doped region formed in the drain region, and at least a first well having the first doped region formed therein. The source region and the drain region include a first conductivity type, the first doped region and the first well include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. | 09-25-2014 |
20140284671 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross- sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure. | 09-25-2014 |
20140282295 | Method for Forming Photo-masks and OPC Method - The present invention provides a method for forming at least a photo mask. A first photo-mask pattern relating to a first structure is provides. A second photo-mask pattern relating to a second structure is provides. A third photo-mask pattern relating to a third structure is provides. The first structure, the second structure and the third structure are disposed in a semiconductor structure in sequence. An optical proximity process including a comparison step is provided, wherein the comparison step includes comparing the first photo-mask pattern and the third photo-mask pattern. Last, the first photo-mask pattern is import to form a first mask, the second photo-mask pattern is import to form a second mask, and the third photo-mask pattern is import to form a third mask. The present invention further provides an OPC method. | 09-18-2014 |
20140273386 | METHOD OF FORMING METAL SILICIDE LAYER - A method of forming a metal silicide layer includes the following steps. At first, at least a gate structure, at least a source/drain region and a first dielectric layer are formed on a substrate, and the gate structure is aligned with the first dielectric layer. Subsequently, a cap layer covering the gate structure is formed, and the cap layer does not overlap the first dielectric layer and the source/drain region. Afterwards, the first dielectric layer is removed to expose the source/drain region, and a metal silicide layer totally covering the source/drain region is formed. | 09-18-2014 |
20140273371 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the resistor region of the substrate; forming a tank in the STI; and forming a resistor in the tank and on two sides of the top surface of the STI outside the tank. | 09-18-2014 |
20140273368 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer. | 09-18-2014 |
20140264481 | PLUG STRUCTURE AND PROCESS THEREOF - A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer having an opening exposing the first plug is located on the first dielectric layer. The barrier layer conformally covers the opening, wherein the barrier layer has a bottom part and a sidewall part, and the bottom part is a single layer and physically contacts the first plug while the sidewall part is a dual layer. The second plug fills the opening and on the barrier layer. Moreover, a process of forming a plug structure is also provided. | 09-18-2014 |
20140264480 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device includes the following steps. At first, a semiconductor substrate is provided, and a metal gate structure and a first dielectric layer are disposed on the semiconductor substrate, wherein a top surface of the metal gate structure is aligned with a top surface of the first dielectric layer. Then, a patterned mask is formed on the metal gate structure, and the patterned mask does not overlap the first dielectric layer. Subsequently, a second dielectric layer covering the patterned mask is conformally formed on the semiconductor substrate. Furthermore, a part of the first dielectric layer and a part of the second dielectric layer are removed for forming at least a contact hole. | 09-18-2014 |
20140258946 | MASK SET FOR DOUBLE EXPOSURE PROCESS AND METHOD OF USING THE MASK SET - A mask set for double exposure process and method of using said mask set. The mask set is provided with a first mask pattern having a first base and a plurality of first teeth and protruding portions, and a second mask pattern having a second base and a plurality of second teeth, wherein the second base may at least partially overlap the first base such that each of the protruding portions at least partially overlaps one of the second teeth. | 09-11-2014 |
20140256151 | METHOD FOR REMOVING NITRIDE MATERIAL - A method for removing silicon nitride material includes following steps. A substrate having at least a gate structure formed thereon is provided, and at least a silicon nitride hard mask is formed on top of the gate structure. A first removal is performed to remove a portion of the silicon nitride hard mask with a first phosphoric acid (H | 09-11-2014 |
20140256136 | METHOD FOR FORMING FIN-SHAPED STRUCTURES - The present invention provides a method for forming a fin structure comprising the following steps: first, a multiple-layer structure is formed on a substrate; then, a sacrificial pattern is formed on the multiple-layer structure, a spacer is formed on the sidewall of the sacrificial pattern and disposed on the multiple-layer structure, the sacrificial pattern is removed, the spacer is used as a cap layer to etch parts of the multiple-layer structure, and then the multiple-layer structure is used as a cap layer to etch the substrate and to form at least one fin structure in the substrate. | 09-11-2014 |
20140256132 | METHOD FOR PATTERNING SEMICONDUCTOR STRUCTURE - A method for patterning a semiconductor structure is provided. The method comprises following steps. A first mask defining a first pattern in a first region and a second pattern in a second region adjacent to the first region is provided. The first pattern defined by the first mask is transferred to a first film structure in the first region, and the second pattern defined by the first mask is transferred to the first film structure in the second region. A second film structure is formed on the first film structure. A second mask defining a third pattern in the first region is provided. At least 50% of a part of the first region occupied by the first pattern defined by the first mask is identical with a part of the first region occupied by the third pattern defined by the second mask. | 09-11-2014 |
20140256115 | SEMICONDUCTOR PROCESS - A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided. | 09-11-2014 |
20140252482 | FINFET TRANSISTOR STRUCTURE AND METHOD FOR MAKING THE SAME - A FINFET transistor structure includes a substrate including a fin structure. Two combined recesses embedded within the substrate, wherein each of the combined recesses includes a first recess extending in a vertical direction and a second recess extending in a lateral direction, the second recess has a protruding side extending to and under the fin structure. Two filling layers respectively fill in the combined recesses. A gate structure crosses the fin structure. | 09-11-2014 |
20140252423 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench. | 09-11-2014 |
20140248762 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed. | 09-04-2014 |
20140246730 | EMBEDDED RESISTOR - An embedded resistor including a first interdielectric layer, a cap layer, a resistive layer and a cap film is provided. The first interdielectric layer is located on a substrate. The cap layer is located on the first interdielectric layer, wherein the cap layer has a trench. The resistive layer conformally covers the trench, thereby having a U-shaped cross-sectional profile. The cap film is located in the trench and on the resistive layer, or, an embedded thin film resistor including a first interdielectric layer, a cap layer and a bulk resistive layer is provided. The first interdielectric layer is located on a substrate. The cap layer is located on the first interdielectric layer, wherein the cap layer has a trench. The bulk resistive layer is located in the trench. | 09-04-2014 |
20140242811 | ATOMIC LAYER DEPOSITION METHOD - An ALD method includes providing a substrate in an ALD reactor, performing a pre-ALD treatment to the substrate in the ALD reactor, and performing one or more ALD cycles to form a dielectric layer on the substrate in the ALD reactor. The pre-ALD treatment includes providing a hydroxylating agent to the substrate in a first duration, and providing a precursor to the substrate in a second duration. Each of the ALD cycles includes providing the hydroxylating agent to the substrate in a third duration, and providing the precursor to the substrate in a fourth duration. The first duration is longer than the third duration. | 08-28-2014 |
20140242802 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A wafer on a pedestal is provided. The pedestal is lifted to approach a heating source and an etching process is performed on the wafer. An annealing process is performed on the wafer by the heating source. In another way, a wafer on a pedestal, and a heating source on a same side of the wafer as the pedestal are provided. An etching process is performed on the wafer by setting the temperature difference between the heating source and the pedestal larger than 180° C. | 08-28-2014 |
20140242770 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following step. A stacked structure is formed on a substrate. A contact etch stop layer is formed to cover the stacked structure and the substrate. A material layer is formed on the substrate and exposes a top part of the contact etch stop layer covering the stacked structure. The top part is redressed. | 08-28-2014 |
20140241027 | Static random access memory unit cell structure and static random access memory unit cell layout structure - A static random access memory unit cell layout structure is disclosed, in which a slot contact is disposed on one active area and another one across from the one. A static random access memory unit cell structure and a method of fabricating the same are also disclosed, in which, a slot contact is disposed on drains of a pull-up transistor and a pull-down transistor, and a metal-zero interconnect is disposed on the slot contact and a gate line of another pull-up transistor. Accordingly, there is not an intersection of vertical and horizontal metal-zero interconnects, and there is no place suffering from twice etching. Leakage junction due to stitch recess can be avoided. | 08-28-2014 |
20140239419 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device is provided. A silicon substrate is provided, and a gate insulating layer is formed on the silicon substrate. Then, a silicon barrier layer is formed on the gate insulating layer by the physical vapor deposition (PVD) process. Next, a silicon-containing layer is formed on the silicon barrier layer. The silicon barrier layer of the embodiment is a hydrogen-substantial-zero silicon layer, which has a hydrogen concentration of zero substantially. | 08-28-2014 |
20140235043 | METHOD FOR FORMING FIN-SHAPED STRUCTURE - A method for forming a fin-shaped structure includes the following steps. A pad layer is formed on a substrate. A sacrificial pattern is formed on the pad layer. A spacer is formed on the pad layer beside the sacrificial pattern, wherein the ratio of the height of the spacer to the pad layer is larger than 5. The sacrificial pattern is removed. The layout of the spacer is transferred to the substrate to form at least a fin-shaped structure having a taper profile in the substrate. | 08-21-2014 |
20140235038 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING EPITAXIAL LAYER - A method for forming epitaxial layer is disclosed. The method includes the steps of providing a semiconductor substrate, and forming an undoped first epitaxial layer in the semiconductor substrate. Preferably, the semiconductor substrate includes at least a recess, the undoped first epitaxial layer has a lattice constant, a bottom thickness, and a side thickness, in which the lattice constant is different from a lattice constant of the semiconductor substrate and the bottom thickness is substantially larger than or equal to the side thickness. | 08-21-2014 |
20140220482 | METHOD FOR FORMING PATTERNS - A method for forming patterns includes the following steps. A first layout including a first target pattern and a first unprintable dummy pattern is provided. A second layout including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlaps the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern cannot be formed in a wafer. | 08-07-2014 |
20140213066 | LAYOUT DECOMPOSITION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE APPLYING THE SAME - A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processor of a computing system. A design rule for layout decomposition is then identified by the logic processor, including identifying dense areas (areas with densely distributed features) on a substrate, and identifying areas with odd-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system for fabricating patterns of features in at least two of the areas with odd-numbered features in one of the dense areas. | 07-31-2014 |
20140213034 | METHOD FOR FORMING ISOLATION STRUCTURE - A method for forming an isolation structure includes the following steps. A hard mask layer is formed on a substrate and a trench is formed in the substrate and the hard mask layer. A protective layer is formed to cover the trench and the hard mask layer. A first isolation material is filled into the trench. An etching process is performed to etch back part of the first isolation material. | 07-31-2014 |
20140213028 | EPITAXIAL PROCESS - An epitaxial process includes the following steps. A substrate including a first area and a second area is provided. A first gate and a second gate are formed respectively on the substrate of the first area and the second area. A first spacer and a second spacer are respectively formed on the substrate beside the first gate and the second gate at the same time. A first epitaxial structure is formed beside the first spacer and then a second epitaxial structure is formed beside the second spacer by the first spacer and the second spacer respectively. | 07-31-2014 |
20140206174 | METHOD OF MAKING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, and a first region, a second region and a third region are defined thereon. Then, a first well having a first conductive type is formed in the semiconductor substrate of the first region and the second region, respectively. A semiconductor layer partially overlapping the first well of the second region is formed. Furthermore, a second well having a second conductive type is formed in the semiconductor substrate of the third region and the first well of the second region respectively, where the second well of the second region is disposed underneath the semiconductor layer. | 07-24-2014 |
20140206170 | METHOD OF FABRICATING MOS DEVICE - Provided is a method of fabricating a MOS device including the following steps. At least one gate structure is formed on a substrate, wherein the gate structure includes a gate conductive layer and a hard mask layer disposed on the gate conductive layer. A first implant process is performed to form source and drain extension regions in the substrate, wherein the gate conductive layer is covered by the hard mask layer. A process is of removing the hard mask layer is performed to expose the surface of the gate conductive layer. A second implant process is performed to form pocket doped regions in the substrate, wherein the gate conductive layer is not covered by the hard mask layer. | 07-24-2014 |
20140205953 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method for forming a semiconductor device comprises the following steps: first, a substrate is provided, a first photo-etching process is carried out with a first photomask to form at least one device structure and a plurality of compensation structures, wherein the first photomask comprises at least one device pattern and a plurality of dummy patterns. A photoresist layer is then formed on the device structure and each compensation structures; a second photo-etching process is then carried out with a second photomask to remove each compensation structure. | 07-24-2014 |
20140203828 | LAYOUT STRUCTURE OF ELECTRONIC ELEMENT AND TESTING METHOD OF THE SAME THEREOF - A layout structure of an electronic element comprising an electronic matrix, a first load and a second load is disclosed. The first load couples to a first end of the electronic matrix and comprises a first testing pad and a second testing pad coupling to the first testing pad. The second load couples to a second end of the electronic matrix and comprises a third testing pad and a fourth testing pad coupling to the third testing pad. | 07-24-2014 |
20140203394 | Chip With Through Silicon Via Electrode And Method Of Forming The Same - The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening. | 07-24-2014 |
20140203367 | Transistor Structure for Electrostatic Discharge Protection - The present invention discloses a transistor structure for electrostatic discharge protection. The structure includes a substrate, a doped well, a first doped region, a second doped region and a third doped region. The doped well is disposed in the substrate and has a first conductive type. The first doped region is disposed in the substrate, encompassed by the doped well and has the first conductive type. The second doped region is disposed in the substrate, encompassed by the doped well and has a second conductive type. The third doped region is disposed in the substrate, encompassed by the doped well and has the second conductive type. A gap is disposed between the first doped region and the second doped region. | 07-24-2014 |
20140201691 | LAYOUT DECOMPOSITION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE APPLYING THE SAME - A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system. | 07-17-2014 |
20140199854 | METHOD OF FORMING FILM ON DIFFERENT SURFACES - A method of forming a film is provided. The method includes at least the following steps. A first substrate and a second substrate are provided in a batch processing system, wherein a first surface of the first substrate is adjacent to a second surface of the second substrate, the first surface of the first substrate has a first surface condition, the second surface of the second substrate has a second surface condition, and the first surface condition is different from the second surface condition. A pretreatment gas is provided to the surfaces of the substrates for transforming the first surface condition and the second surface condition to a third surface condition. A reaction gas is provided to form the film on the surfaces, having the third surface condition, of the substrates. | 07-17-2014 |
20140199837 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE HAVING CONTACT PLUG - A method of forming a semiconductor structure having at least a contact plug includes the following steps. At first, at least a transistor and an inter-layer dielectric (ILD) layer are formed on a substrate, and the transistor includes a gate structure and two source/drain regions. Subsequently, a cap layer is formed on the ILD layer and on the transistor, and a plurality of openings that penetrate through the cap layer and the ILD layer until reaching the source/drain regions are formed. Afterward, a conductive layer is formed to cover the cap layer and fill the openings, and a part of the conductive layer is further removed for forming a plurality of first contact plugs, wherein a top surface of a remaining conductive layer and a top surface of a remaining cap layer are coplanar, and the remaining cap layer totally covers a top surface of the gate structure. | 07-17-2014 |