Patent application title: MEMORY DEVICE WITH USER CONFIGURABLE DENSITY/PERFORMANCE
Frankie F. Roohparvar (Monte Sereno, CA, US)
IPC8 Class: AG06F1200FI
Class name: Specific memory composition solid-state read only memory (rom) programmable read only memory (prom, eeprom, etc.)
Publication date: 2012-03-22
Patent application number: 20120072653
The memory device is comprised of a memory array having a plurality of
memory cells that are organized into memory blocks. Each memory cell is
capable of storing a selectable quantity of data bits (e.g., multiple
level cells or a single bit per cell). Control circuitry controls the
density configuration of read or write operations to the memory blocks in
response to a configuration command. In one embodiment, the configuration
command is part of the read or write command. In another embodiment, the
configuration command is read from a configuration register.
1. A memory device having selectable density configurations, the device
comprising: a memory array comprising a plurality of memory cells, each
memory cell configured to store a selectable quantity of data bits, the
memory array organized into memory blocks; a configuration register; and
control circuitry, coupled to the memory array, that controls the density
configuration in response to a configuration command, wherein each memory
block is assigned a plurality of configuration bits of the configuration
register such that each memory block is configured to have multiple
2. The memory device of claim 1 wherein the plurality of memory cells are floating gate memory cells.
3. The memory device of claim 1 wherein the plurality of memory cells are arranged in series strings of memory cells.
4. The memory device of claim 1 wherein the configuration register is a non-volatile register.
5. The memory device of claim 4 wherein the non-volatile register is a programmable fuse apparatus.
6. The memory device of claim 1 wherein the configuration register is a volatile memory array.
7. The memory device of claim 1 wherein the configuration register comprises both a non-volatile register and a volatile register.
8. A NAND flash memory device having selectable density configurations, the device comprising: a memory array comprising a plurality of memory cells that are organized into memory blocks, each memory cell configured to store a selectable quantity of data bits; control circuitry, coupled to the memory array, that determines the density configuration for a memory block in response to a configuration bit; and a configuration register, coupled to the control circuitry, for storing the configuration bit, wherein each memory block is assigned a plurality of density configuration bits.
9. The NAND flash memory device of claim 8 wherein the configuration register is configured to store trimming data, memory block lock data, and record keeping data for the memory device.
10. A semiconductor, non-volatile memory device having a plurality of selectable density configurations, the device comprising: a memory array comprising a plurality of memory cells grouped into memory blocks, each memory cell configured to store a selectable quantity of data bits; a control bus for receiving density configuration commands that are included in read and write commands; and control circuitry coupled to the memory array and the control bus and configured to control the density configuration in response to the received density configuration commands and programming of a configuration register, wherein each memory block is assigned a plurality of configuration bits of the configuration register such that each memory block is configured to have multiple densities.
11. The semiconductor, non-volatile memory device of claim 10 wherein each bit of the configuration register is assigned to a sub-block level.
12. The semiconductor, non-volatile memory device of claim 10 wherein a first state of each bit of the configuration register indicates a first density and a second state of each bit of the configuration register indicates a second density that is greater than the first density.
13. A method for configuring performance of a memory array, organized as memory blocks, in a memory device, the memory device comprising control circuitry coupled to a configuration register, the method comprising: loading configuration data into the configuration register; and setting a performance configuration for at least a subset of the memory array in response to the configuration data, wherein each memory block is configured to have a plurality of density configurations.
14. The method of claim 13 and further comprising the control circuitry receiving a write or read command to determine the density configuration of each memory block.
15. The method of claim 13 wherein the control circuitry uses single bit per cell read and write algorithms and multilevel cell read and write algorithms.
16. The method of claim 15 wherein the multilevel cell write algorithm stores more than two bits per memory cell.
17. The method of claim 13 and further comprising tracking density/performance levels of the memory blocks.
18. A method for configuring performance of a memory array having a plurality of memory blocks, the method comprising: receiving configuration data; and setting a performance configuration for at least a memory block of the memory array in response to the received configuration data, wherein each memory block is configured to be assigned multiple configuration data.
19. A method for configuring the density of a memory array, organized as memory blocks, the method comprising: receiving a command for initiating one of a read or a write operation on a memory block; determining if the received command comprises a memory density configuration; executing one of a single bit per cell read/write routine or a multilevel cell read/write routine on the memory block at the memory density configuration specified in the command; and storing the memory density configuration from the command in a configuration register, wherein each memory block is configured to have multiple memory density configurations as indicated by the configuration register.
20. The method of claim 19 wherein the multilevel cell read/write routine is configured to store a plurality of bits on one memory cell.
 This Application is a Continuation of U.S. application Ser. No. 10/861,646, titled "MEMORY DEVICE WITH USER CONFIGURABLE DENSITY/PERFORMANCE," filed Jun. 4, 2004, (allowed) which is commonly assigned and incorporated herein by reference.
 The present invention relates generally to memory devices and in particular the present invention relates to non-volatile memory devices.
 Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
 Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
 The present trend of electronic devices is increased performance at reduced cost. The component manufacturers, therefore, must continue to increase the performance of their devices while decreasing the cost to manufacture them.
 One way to increase a flash memory device's density while lowering its manufacturing cost is to use multiple level cells (MLC). Such a device stores two logical bits per physical cell. This reduces the overall cost of the memory. NAND flash memory devices are designed to operate in either one of two configurations on the same die: single bit per cell (SBC) or MLC. The selection of the configuration is done at the factory when the die is manufactured through a metal mask or a programmable fuse option.
 However, an MLC die, while having improved cost versus density, has drawbacks relative to performance. Both the programming and read operations can become slower for an MLC die. Therefore, the user typically has to choose between having high memory density at low cost and lower memory density with higher performance.
 For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device that combines the attributes of both MLC and SBC devices.
BRIEF DESCRIPTION OF THE DRAWINGS
 FIG. 1 shows a diagram of one embodiment of a NAND flash memory array of the present invention.
 FIG. 2 shows a block diagram of one embodiment of a flash memory device of the present invention that incorporates the memory array of FIG. 1.
 FIG. 3 shows a flowchart of one embodiment of a method for configuring the density/performance of a memory device.
 FIG. 4 shows a flowchart of another embodiment of a method for configuring the density/performance of a memory device.
 In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof.
 FIG. 1 illustrates a NAND flash array is comprised of an array of floating gate cells 101 arranged in series strings 104, 105. Each of the floating gate cells are coupled drain to source in the series chain 104, 105. Word lines (WL0-WL31) that span across multiple series strings 104, 105 are coupled to the control gates of every floating gate cell in order to control their operation. The memory array is arranged in row and column form such that the word lines (WL0-WL31) form the rows and the bit lines (BL1-BL2) form the columns.
 In operation, the word lines (WL0-WL31) select the individual floating gate memory cells in the series chain 104, 105 to be written to or read from and operate the remaining floating gate memory cells in each series string 104, 105 in a pass through mode. Each series string 104, 105 of floating gate memory cells is coupled to a source line 106 by a source select gate 116, 117 and to an individual bit line (BL1-BL2) by a drain select gate 112, 113. The source select gates 116, 117 are controlled by a source select gate control line SG(S) 118 coupled to their control gates. The drain select gates 112, 113 are controlled by a drain select gate control line SG(D) 114.
 The memory cells illustrated in FIG. 1 can be operated as either single bit cells (SBC) or multilevel cells (MLC). Multilevel cells greatly increase the density of a flash memory device. Such cells enable storage of multiple bits per memory cell by charging the floating gate of the transistor to different levels. MLC technology takes advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage range stored on the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of voltage ranges assigned to the cell.
 For example, a cell may be assigned four different voltage ranges of 200 mV for each range. Typically, a dead space or guard band of 0.2V to 0.4V is between each range. If the voltage stored on the cell is within the first range, the cell is storing a 00. If the voltage is within the second range, the cell is storing a 01. This continues for as many ranges are used for the cell.
 The embodiments of the present invention may refer to the MLC as a high density configuration. The embodiments of the present invention are not limited to two bits per cell. Some embodiments may store more than two bits per cell, depending on the quantity of different voltage ranges that can be differentiated on the cell. Therefore, the term high density generally refers to any density beyond single bit cells.
 FIG. 2 illustrates a block diagram of one embodiment of a flash memory device 200 of the present invention that incorporates the memory array illustrated in FIG. 1. The memory device 200 has been simplified to focus on features of the memory that are helpful in understanding the present invention. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art.
 The memory device 200 includes an array of flash memory cells 230 as discussed previously. The cells of the memory array 230 can be grouped into memory blocks. In one embodiment, a memory block comprises 512 bytes in a row by 32 rows. Alternate embodiments are comprised of memory blocks having different quantities of memory cells.
 An address buffer circuit 240 is provided to latch address signals provided on address input connections A0-Ax242. Address signals are received and decoded by a row decoder 244 and a column decoder 246 to access the memory array 230. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array 230. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.
 The memory device 200 reads data in the memory array 230 by sensing voltage or current changes in the memory array columns using sense amplifier/buffer circuitry 250. The sense amplifier/buffer circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array 230. Data input and output buffer circuitry 260 is included for bi-directional data communication over a plurality of data connections 262 with the controller 210. Write circuitry 255 is provided to write data to the memory array.
 Control circuitry 270 decodes signals provided on a control bus 272. These signals are used to control the operations on the memory array 230, including single density data read and write, high density data read and write, and erase operations. The control circuitry 270 may be a state machine, a sequencer, or some other type of controller. The control circuitry 270, in one embodiment, is responsible for executing the embodiments of the methods of the present invention for configuring the memory blocks as high or single density.
 The control circuitry 270 can also program the configuration registers 280 in which, in one embodiment, the high/single density configuration bits of the present invention can reside. This register may be a non-volatile, programmable fuse apparatus, a volatile memory array, or both. The configuration register 280 can also hold other data such as trimming data, memory block lock data, record keeping data for the memory device, and other data required for operation of the memory device.
 FIG. 3 illustrates a flowchart of one embodiment of a method for configuring the density/performance of a memory device. This embodiment uses special write and read commands to perform high density program and read operations. This embodiment puts the burden on the memory control circuitry to determine the density/performance configuration for a particular memory block. By having the control circuitry perform this task, the memory device does not require any extra hardware in order to switch blocks between high density and single density. The controller tracks the density/performance level.
 This embodiment uses two sets of algorithms--one for SBC reading and writing and another for MLC reading and writing. A higher level routine determines which set of algorithms to use depending on the received command. In this embodiment, the erase operation is substantially similar for each memory density.
 The method determines if the received command is a read or write command 301. If a write command was received, it is determined 303 whether the command is a single density write command or a special high density write command. A high density write command 307 causes the controller circuitry to program the specified memory block with two or more bits per cell. A single density write command 309 causes the controller circuitry to program the specified memory block with one bit per cell.
 If the received command is a read command, it is determined 305 whether the command is a single density read command or a high density read command. If the command is a high density read command 311, the memory block was previously programmed as an MLC cell and is, therefore, read with a high density read operation. A single density configuration read command causes the memory block to be read 313 assuming it was programmed as an SBC.
 In another embodiment of the present invention, illustrated in FIG. 4, a configuration register is used to pre-assign blocks of memory to the SBC or MLC configuration of operation. This could occur when the system is initialized. This embodiment would not require special commands than those used in MLC or SBC flash memory devices. Additionally, an existing register could be used to store the configuration data so that additional hardware is not required or, in another embodiment, a dedicated configuration register could be added to the memory device.
 In one embodiment, the register of the present invention has a bit for every memory block for indicating the operating mode (e.g., MLC or SBC) of that particular block. For example, a logical 1 stored in the memory block 0 configuration bit would indicate that the block is an SBC block while a logical 0 would indicate the block is operating as an MLC block. In another embodiment, these logic levels are reversed.
 Alternate embodiments can assign different quantities of blocks to each bit of the configuration register. For example, the register may have a configuration bit assigned to more than one memory block. Additionally, a configuration bit may be assigned to the sub-block level such that each block has multiple configuration bits.
 In one embodiment, row 0 of the flash memory device of the present invention is a configuration row. At initialization and/or power-up of the device, the configuration data from row 0 is loaded into the configuration register 401.
 When a command is received, it is determined whether it is a read or write command 403. For a read command, the configuration register is checked prior to the read operation to determine if the memory block has been assigned a high density or single density configuration 407. In a single density configuration 411, a single density read operation is performed 419. In a high density configuration 411, a high density read operation is performed 417.
 If a write command was received, the configuration register is checked prior to write operation to determine if the memory block has been assigned a high density or a single density configuration 409. In a single density configuration 409, a single density write operation is performed 415. In a high density configuration 409, a high density write operation is performed 413.
 In the embodiment of FIG. 4, the user determines the configuration of each block, or other memory cell grouping, and stores this data into the configuration register. When the memory device is powered down, the data in the configuration register is copied to row 0 for more permanent storage in non-volatile memory. In another embodiment, the user can store the configuration directly to the non-volatile, configuration row of the memory device.
 The flash memory of the present invention is comprised of memory blocks that can each be configured to store data in different densities. For example, one use of a single memory device might be to store both pictures and code. The picture data is more tolerant of corrupted data than the storage of code. Therefore, since the SBC configuration has a higher reliability than the MLC configuration, the user would typically choose the SBC configuration for the code storage and the MLC configuration for the picture storage.
 Similarly, since the MLC configuration might be eight to nine times slower in read and programming performance as compared to the SBC configuration, the user might choose the MLC configuration for memory blocks requiring faster read/write times. This could be useful in a system having fast bus speeds requiring fast storage and retrieval times.
 In summary, the embodiments of the present invention enable a memory device user to select between an MLC and an SBC configuration. Different configurations can be set up for different memory blocks or even to the sub-block level. Additionally, the configuration changes can be performed dynamically with configuration commands.
 Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.
Patent applications by Frankie F. Roohparvar, Monte Sereno, CA US
Patent applications in class Programmable read only memory (PROM, EEPROM, etc.)
Patent applications in all subclasses Programmable read only memory (PROM, EEPROM, etc.)