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DUANE MORRIS LLP;IP DEPARTMENT (TSMC)
PHILADELPHIA, PA US
1. 20080254600 METHODS FOR FORMING INTERCONNECT STRUCTURES 10-16-20082. 20080254588 METHODS FOR FORMING TRANSISTORS WITH HIGH-K DIELECTRIC LAYERS AND TRANSISTORS FORMED THEREFROM 10-16-2008
3. 20080252361 ELECTRICAL FUSES WITH REDUNDANCY - The present disclosure provides an electrical fuse cell with redundancy features and the method for operating the 10-16-2008
4. 20080233710 METHODS FOR FORMING SINGLE DIES WITH MULTI-LAYER INTERCONNECT STRUCTURES AND STRUCTURES FORMED THEREFROM 09-25-2008
5. 20080225617 METHOD FOR HIGH SPEED SENSING FOR EXTRA LOW VOLTAGE DRAM 09-18-2008
6. 20080225616 METHOD FOR INCREASING RETENTION TIME IN DRAM 09-18-2008
7. 20080218931 SYSTEM FOR DECHARGING A WAFER OR SUBSTRATE AFTER DECHUCKING FROM AN ELECTROSTATIC CHUCK 09-11-2008
8. 20080211106 VIA/CONTACT AND DAMASCENE STRUCTURES AND MANUFACTURING METHODS THEREOF 09-04-2008
9. 20080197473 CHIP HOLDER WITH WAFER LEVEL REDISTRIBUTION LAYER 08-21-2008