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Advanced Mirco Devices, Inc.;c/o Williams, Morgan & Amerson
HOUSTON, TX US
1. 20100223513 LATENCY DETECTION IN A MEMORY BUILT-IN SELF-TEST BY USING A PING SIGNAL 09-02-20102. 20100221911 PROVIDING SUPERIOR ELECTROMIGRATION PERFORMANCE AND REDUCING DETERIORATION OF SENSITIVE LOW-K DIELECTRICS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES 09-02-2010
3. 20100219534 MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS AND REFILLED AIR GAP EXCLUSION ZONES 09-02-2010
4. 20100219527 METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE INCLUDING METAL PILLARS HAVING A REDUCED DIAMETER AT THE BOTTOM 09-02-2010
5. 20100219475 INTEGRATION OF SEMICONDUCTOR ALLOYS IN PMOS AND NMOS TRANSISTORS BY USING A COMMON CAVITY ETCH PROCESS 09-02-2010
6. 20100199268 APPLICATION OF PLATFORM DEPENDENT ROUTINES IN VIRTUAL MACHINES BY EMBEDDING NATIVE CODE IN CLASS FILES 08-05-2010
7. 20100193882 IN SITU FORMED DRAIN AND SOURCE REGIONS INCLUDING A STRAIN-INDUCING ALLOY AND A GRADED DOPANT PROFILE 08-05-2010
8. 20100193881 REDUCTION OF THICKNESS VARIATIONS OF A THRESHOLD SEMICONDUCTOR ALLOY BY REDUCING PATTERNING NON-UNIFORMITIES PRIOR TO DEPOSITING THE SEMICONDUCTOR ALLOY 08-05-2010
9. 20100193873 INCREASED DEPTH OF DRAIN AND SOURCE REGIONS IN COMPLEMENTARY TRANSISTORS BY FORMING A DEEP DRAIN AND SOURCE REGION PRIOR TO A CAVITY ETCH 08-05-2010
10. 20100193866 GRADED WELL IMPLANTATION FOR ASYMMETRIC TRANSISTORS HAVING REDUCED GATE ELECTRODE PITCHES 08-05-2010
11. 20100187629 TENSILE STRAIN SOURCE USING SILICON/GERMANIUM IN GLOBALLY STRAINED SILICON 07-29-2010
12. 20100168892 METHOD AND SYSTEM FOR SYNCHRONIZING CHAMBER DOWN TIMES BY CONTROLLING TRANSPORT SEQUENCING IN A PROCESS TOOL 07-01-2010
13. 20100164121 METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE COMPRISING EXTRA-TAPERED TRANSITION VIAS 07-01-2010
14. 20100164098 SEMICONDUCTOR DEVICE INCLUDING A COST-EFFICIENT CHIP-PACKAGE CONNECTION BASED ON METAL PILLARS 07-01-2010
15. 20100164020 TRANSISTOR WITH AN EMBEDDED STRAIN-INDUCING MATERIAL HAVING A GRADUALLY SHAPED CONFIGURATION 07-01-2010
16. 20100164014 REDUCTION OF THRESHOLD VOLTAGE VARIATION IN TRANSISTORS COMPRISING A CHANNEL SEMICONDUCTOR ALLOY BY REDUCING DEPOSITION NON-UNIFORMITIES 07-01-2010
17. 20100163994 SOI DEVICE WITH A BURIED INSULATING MATERIAL HAVING INCREASED ETCH RESISTIVITY 07-01-2010
18. 20100155850 TECHNIQUE FOR PROVIDING STRESS SOURCES IN TRANSISTORS IN CLOSE PROXIMITY TO A CHANNEL REGION BY RECESSING DRAIN AND SOURCE REGIONS 06-24-2010
19. 20100136762 ENHANCING INTEGRITY OF A HIGH-K GATE STACK BY PROTECTING A LINER AT THE GATE BOTTOM DURING GATE HEAD EXPOSURE 06-03-2010
20. 20100133699 MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH AIR GAPS FORMED COMMONLY WITH VIAS 06-03-2010
21. 20100133628 HIGH-K GATE ELECTRODE STRUCTURE FORMED AFTER TRANSISTOR FABRICATION BY USING A SPACER 06-03-2010
22. 20100133615 MULTIPLE GATE TRANSISTOR HAVING FINS WITH A LENGTH DEFINED BY THE GATE ELECTRODE 06-03-2010
23. 20100090321 HIGH-K ETCH STOP LAYER OF REDUCED THICKNESS FOR PATTERNING A DIELECTRIC MATERIAL DURING FABRICATION OF TRANSISTORS 04-15-2010