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IBM CORPORATION- AUSTIN (JVL);C/O VAN LEEUWEN & VAN LEEUWEN
AUSTIN, TX US
1. 20110047350 PARTITION LEVEL POWER MANAGEMENT USING FULLY ASYNCHRONOUS CORES WITH SOFTWARE THAT HAS LIMITED ASYNCHRONOUS SUPPORT 02-24-20112. 20110035344 COMPUTING MIXED-INTEGER PROGRAM SOLUTIONS USING MULTIPLE STARTING VECTORS 02-10-2011
3. 20110022803 Two Partition Accelerator and Application of Tiered Flash to Cache Hierarchy in Partition Acceleration 01-27-2011
4. 20110010216 SOFTWARE LICENSE USAGE AMONGST WORKGROUPS USING SOFTWARE USAGE DATA 01-13-2011
5. 20100332678 SMART NAGLING IN A TCP CONNECTION - approach is provided to improve network efficiency 12-30-2010
6. 20100306392 CREATING CONTEXT-SENSITIVE WEBPAGE TIME-OUT INTERVALS 12-02-2010
7. 20100293510 WEBPAGE MAGNIFIER/FORMATTER USING CSS PROPERTIES AND CURSOR/MOUSE LOCATION 11-18-2010
8. 20100293373 INTEGRITY SERVICE USING REGENERATED TRUST INTEGRITY GATHER PROGRAM 11-18-2010
9. 20100250901 Selecting Fixed-Point Instructions to Issue on Load-Store Unit 09-30-2010
10. 20100235158 Automated System Latency Detection for Fabric Simulation 09-16-2010
11. 20100235156 Automated Simulation Fabric Discovery and Configuration 09-16-2010
12. 20100229176 Distribute Accumulated Processor Utilization Charges Among Multiple Threads 09-09-2010
13. 20100194525 Securing Premises Using Surfaced-Based Computing Technology 08-05-2010
14. 20100180020 IMPROVING SCALE BETWEEN CONSUMER SYSTEMS AND PRODUCER SYSTEMS OF RESOURCE MONITORING DATA 07-15-2010
15. 20100178994 Intelligent System To Indicate Appropriate Trajectories in Cue Sports 07-15-2010
16. 20100172572 Focus-Based Edge Detection - model generator computes a first image perimeter color difference value for each of a plurality of first pixels included in 07-08-2010
17. 20100138166 ESTIMATING CONSUMER ALCOHOL INTAKE USING NON-INVASIVE TECHNOLOGY 06-03-2010
18. 20100125436 Identifying Deterministic Performance Boost Capability of a Computer System 05-20-2010
19. 20100107244 Trust Event Notification and Actions Based on Thresholds and Associated Trust Metadata Scores 04-29-2010
20. 20100106560 Generating Composite Trust Value Scores Based on Assignable Priorities, Atomic Metadata Values and Associated Composite Trust Value Scores 04-29-2010
21. 20100106559 Configurable Trust Context Assignable to Facts and Associated Trust Metadata 04-29-2010
22. 20100106558 Trust Index Framework for Providing Data and Associated Trust Metadata 04-29-2010
23. 20100070469 ENHANCED SYNCHRONIZATION FRAMEWORK PROVIDING IMPROVED SYNC GRANULARITY 03-18-2010
24. 20100063995 Synchronizing Network Feeds in High-Frequency Network Events 03-11-2010
25. 20100050031 Providing Pseudo-Randomized Static Values During LBIST Transition Tests 02-25-2010
26. 20100037048 INPUT/OUTPUT CONTROL AND EFFICIENCY IN AN ENCRYPTED FILE SYSTEM 02-11-2010
27. 20100031271 DETECTION OF DUPLICATE MEMORY PAGES ACROSS GUEST OPERATING SYSTEMS ON A SHARED HOST 02-04-2010
28. 20100011248 LIGHT WEIGHT AND HIGH THROUGHPUT TEST CASE GENERATION METHODOLOGY FOR TESTING CACHE/TLB INTERVENTION AND DIAGNOSTICS 01-14-2010
29. 20090328129 Customizing Policies for Process Privilege Inheritance 12-31-2009
30. 20090307468 Generating a Test Case Micro Generator During Processor Design Verification and Validation 12-10-2009
31. 20090300317 SYSTEM AND METHOD FOR OPTIMIZING INTERRUPT PROCESSING IN VIRTUALIZED ENVIRONMENTS 12-03-2009
32. 20090288034 Locating and Identifying Controls on a Web Page 11-19-2009
33. 20090271714 IDENTIFYING MUTUAL FRIENDS IN ONLINE ENVIRONMENTS 10-29-2009
34. 20090259689 Interactive recipe preparation using instructive device with integrated actuators to provide tactile feedback 10-15-2009
35. 20090259688 Interactive recipe preparation using instructive device with integrated actuators to provide tactile feedback 10-15-2009
36. 20090259687 Interactive Recipe Preparation Using Instructive Device with Integrated Actuators to Provide Tactile Feedback 10-15-2009
37. 20090258332 INTERACTIVE RECIPE PREPARATION USING INSTRUCTIVE DEVICE WITH INTEGRATED ACTUATORS TO PROVIDE TACTILE FEEDBACK 10-15-2009
38. 20090258331 INTERACTIVE RECIPE PREPARATION USING INSTRUCTIVE DEVICE WITH INTEGRATED ACTUATORS TO PROVIDE TACTILE FEEDBACK 10-15-2009
39. 20090217371 SYSTEM AND METHOD FOR DYNAMIC CREATION OF PRIVILEGES TO SECURE SYSTEM SERVICES 08-27-2009
40. 20090208002 PREVENTING REPLAY ATTACKS IN ENCRYPTED FILE SYSTEMS 08-20-2009
41. 20090198698 System and Method for Adding Multi-Leval Security to Federated Asset Repositories 08-06-2009
42. 20090189983 SYSTEM AND METHOD FOR PATTERN BASED THRESHOLDING APPLIED TO VIDEO SURVEILLANCE MONITORING 07-30-2009
43. 20090150510 SYSTEM AND METHOD FOR USING REMOTE MODULE ON VIOS TO MANAGE BACKUPS TO REMOTE BACKUP SERVERS 06-11-2009
44. 20090144529 SIMD Code Generation For Loops With Mixed Data Lengths 06-04-2009
45. 20090138689 Partitioning Processor Resources Based on Memory Usage 05-28-2009
46. 20090129596 System and Method for Controlling Comments in a Collaborative Document 05-21-2009
47. 20090119442 Managing Write-to-Read Turnarounds in an Early Read After Write Memory System 05-07-2009
48. 20090112557 System and Method of Automating the Addition of RTL Based Critical Timing Path Counters to Verify Critical Path Coverage of Post-Silicon Software Validation Tools 04-30-2009
49. 20090094536 SYSTEM AND METHOD FOR ADDING MEMBERS TO CHAT GROUPS BASED ON ANALYSIS OF CHAT CONTENT 04-09-2009
50. 20090094462 SYSTEM AND METHOD FOR SELF POLICING OF AUTHORIZED CONFIGURATION BY END POINTS 04-09-2009
51. 20090077387 Authenticating Software Using Protected Master Key 03-19-2009
52. 20090077322 System and Method for Getllar Hit Cache Line Data Forward Via Data-Only Transfer Protocol Through BEB Bus 03-19-2009
53. 20090076641 System and Method for Semiconductor Identification Chip Read Out 03-19-2009
54. 20090070768 System and Method for Using Resource Pools and Instruction Pools for Processor Design Verification and Validation 03-12-2009
55. 20090070643 System and Method for Testing a Large Memory Area During Processor Design Verification and Validation 03-12-2009
56. 20090070632 System and Method for Testing SLB and TLB Cells During Processor Design Verification and Validation 03-12-2009
57. 20090070631 System and Method for Re-Shuffling Test Case Instruction Orders for Processor Design Verification and Validation 03-12-2009
58. 20090070629 System and Method for Testing Multiple Processor Modes for Processor Design Verification and Validation 03-12-2009
59. 20090070570 System and Method for Efficiently Handling Interrupts 03-12-2009
60. 20090070546 System and Method for Generating Fast Instruction and Data Interrupts for Processor Design Verification and Validation 03-12-2009
61. 20090070532 System and Method for Efficiently Testing Cache Congruence Classes During Processor Design Verification and Validation 03-12-2009
62. 20090049178 SYSTEM AND METHOD FOR MINIMIZING RETRY DELAYS IN HIGH TRAFFIC COMPUTER NETWORKS 02-19-2009
63. 20090043997 Time-Of-Life Counter For Handling Instruction Flushes From A Queue 02-12-2009
64. 20090024894 SYSTEM AND METHOD FOR PREDICTING IWARX AND STWCX INSTRUCTIONS IN TEST PATTERN GENERATION AND SIMULATION FOR PROCESSOR DESIGN VERIFICATION/VALIDATION IN INTERRUPT MODE 01-22-2009
65. 20090024892 System and Method of Testing using Test Pattern Re-Execution in Varying Timing Scenarios for Processor Design Verification and Validation 01-22-2009
66. 20090024891 System and Method for Pseudo-Random Test Pattern Memory Allocation for Processor Design Verification and Validation 01-22-2009
67. 20090024886 System and Method for Predicting lwarx and stwcx Instructions in Test Pattern Generation and Simulation for Processor Design Verification and Validation 01-22-2009
68. 20090024877 System and Method for Creating Different Start Cache and Bus States Using Multiple Test Patterns for Processor Design Verification and Validation 01-22-2009
69. 20090024876 System and Method for Verification of Cache Snoop Logic and Coherency Between Instruction & Data Caches for Processor Design Verification and Validation 01-22-2009
70. 20090024873 System and Method for Increasing Error Checking Performance by Calculating CRC Calculations After Multiple Test Patterns for Processor Design Verification and Validation 01-22-2009
71. 20090019255 System and Method for Cache-Locking Mechanism Using Segment Table Attributes for Replacement Class ID Determination 01-15-2009
72. 20090019252 System and Method for Cache-Locking Mechanism Using Translation Table Attributes for Replacement Class ID Determination 01-15-2009
73. 20090007249 SYSTEM AND METHOD FOR SELECTIVE AUTHENTICATION WHEN ACQUIRING A ROLE 01-01-2009
74. 20080313727 Dynamic Discovery and Database Password Expiration Management 12-18-2008
75. 20080307441 System and Method for Call Stack Sampling Combined with Node and Instruction Tracing 12-11-2008
76. 20080307402 SIMD Code Generation in the Presence of Optimized Misaligned Data Reorganization 12-11-2008
77. 20080306778 Accessibility Insurance Coverage Management 12-11-2008
78. 20080301695 Managing a Plurality of Processors as Devices 12-04-2008
79. 20080301606 Design Structure for Switching Digital Circuit Clock Net Driver Without Losing Clock Pulses 12-04-2008
80. 20080301500 System and Method for Identifying and Manipulating Logic Analyzer Data from Multiple Clock Domains 12-04-2008
81. 20080300849 Design Structure for Improved Logic Simulation Using a Negative Unknown Boolean State 12-04-2008
82. 20080297506 Ray Tracing with Depth Buffered Display - image is generated that includes ray traced pixel data and rasterized pixel data 12-04-2008
83. 20080295147 Integrated Security Roles - approach to handling integrated security roles is presented 11-27-2008
84. 20080282064 System and Method for Speculative Thread Assist in a Heterogeneous Processing Environment 11-13-2008
85. 20080276232 Processor Dedicated Code Handling in a Multi-Processor Environment 11-06-2008
86. 20080271029 Thread Scheduling with Weak Preemption Policy 10-30-2008
87. 20080271003 Balancing Computational Load Across a Plurality of Processors 10-30-2008
88. 20080263336 Processor Having Efficient Function Estimate Instructions 10-23-2008
89. 20080263091 Asynchronous Linked Data Structure Traversal 10-23-2008
90. 20080256333 SYSTEM AND METHOD FOR IGNORING FETCH PROTECTION 10-16-2008
91. 20080256275 Multi-Chip Module With Third Dimension Interconnect 10-16-2008
92. 20080250414 Dynamically Partitioning Processing Across A Plurality of Heterogeneous Processors 10-09-2008
93. 20080250208 System and Method for Improving the Page Crossing Performance of a Data Prefetcher 10-09-2008
94. 20080235679 Loading Software on a Plurality of Processors 09-25-2008
95. 20080229129 Remote Control Save and Sleep Override - approach is provided that handles a power down signal received by a device 09-18-2008
96. 20080229078 Dynamic Power Management in a Processor Design 09-18-2008
97. 20080222623 Efficient Code Generation Using Loop Peeling for SIMD Loop Code with Multiple Misaligned Statements 09-11-2008
98. 20080222395 System and Method for Predictive Early Allocation of Stores in a Microprocessor 09-11-2008
99. 20080222307 System and Method for Multiple IP Addresses During Domain Name Resolution 09-11-2008
100. 20080222306 System and Method for Accessing Multiple Addresses Per Domain Name Using Networked Repository 09-11-2008
101. 20080215882 Assigning Security Levels to a Shared Component 09-04-2008
102. 20080209127 System and method for efficient implementation of software-managed cache 08-28-2008
103. 20080201699 Efficient Data Reorganization to Satisfy Data Alignment Constraints 08-21-2008
104. 20080201463 Estimating Network Management Bandwidth - Network management bandwidth is estimated 08-21-2008