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IBM CORPORATION- AUSTIN (JVL);C/O VAN LEEUWEN & VAN LEEUWEN
AUSTIN, TX US
1. 20090288034 Locating and Identifying Controls on a Web Page 11-19-20092. 20090271714 IDENTIFYING MUTUAL FRIENDS IN ONLINE ENVIRONMENTS 10-29-2009
3. 20090259689 Interactive recipe preparation using instructive device with integrated actuators to provide tactile feedback 10-15-2009
4. 20090259688 Interactive recipe preparation using instructive device with integrated actuators to provide tactile feedback 10-15-2009
5. 20090259687 Interactive Recipe Preparation Using Instructive Device with Integrated Actuators to Provide Tactile Feedback 10-15-2009
6. 20090258332 INTERACTIVE RECIPE PREPARATION USING INSTRUCTIVE DEVICE WITH INTEGRATED ACTUATORS TO PROVIDE TACTILE FEEDBACK 10-15-2009
7. 20090258331 INTERACTIVE RECIPE PREPARATION USING INSTRUCTIVE DEVICE WITH INTEGRATED ACTUATORS TO PROVIDE TACTILE FEEDBACK 10-15-2009
8. 20090217371 SYSTEM AND METHOD FOR DYNAMIC CREATION OF PRIVILEGES TO SECURE SYSTEM SERVICES 08-27-2009
9. 20090208002 PREVENTING REPLAY ATTACKS IN ENCRYPTED FILE SYSTEMS 08-20-2009
10. 20090198698 System and Method for Adding Multi-Leval Security to Federated Asset Repositories 08-06-2009
11. 20090189983 SYSTEM AND METHOD FOR PATTERN BASED THRESHOLDING APPLIED TO VIDEO SURVEILLANCE MONITORING 07-30-2009
12. 20090150510 SYSTEM AND METHOD FOR USING REMOTE MODULE ON VIOS TO MANAGE BACKUPS TO REMOTE BACKUP SERVERS 06-11-2009
13. 20090144529 SIMD Code Generation For Loops With Mixed Data Lengths 06-04-2009
14. 20090138689 Partitioning Processor Resources Based on Memory Usage 05-28-2009
15. 20090129596 System and Method for Controlling Comments in a Collaborative Document 05-21-2009
16. 20090119442 Managing Write-to-Read Turnarounds in an Early Read After Write Memory System 05-07-2009
17. 20090112557 System and Method of Automating the Addition of RTL Based Critical Timing Path Counters to Verify Critical Path Coverage of Post-Silicon Software Validation Tools 04-30-2009
18. 20090094536 SYSTEM AND METHOD FOR ADDING MEMBERS TO CHAT GROUPS BASED ON ANALYSIS OF CHAT CONTENT 04-09-2009
19. 20090094462 SYSTEM AND METHOD FOR SELF POLICING OF AUTHORIZED CONFIGURATION BY END POINTS 04-09-2009
20. 20090077387 Authenticating Software Using Protected Master Key 03-19-2009
21. 20090077322 System and Method for Getllar Hit Cache Line Data Forward Via Data-Only Transfer Protocol Through BEB Bus 03-19-2009
22. 20090076641 System and Method for Semiconductor Identification Chip Read Out 03-19-2009
23. 20090070768 System and Method for Using Resource Pools and Instruction Pools for Processor Design Verification and Validation 03-12-2009
24. 20090070643 System and Method for Testing a Large Memory Area During Processor Design Verification and Validation 03-12-2009
25. 20090070632 System and Method for Testing SLB and TLB Cells During Processor Design Verification and Validation 03-12-2009
26. 20090070631 System and Method for Re-Shuffling Test Case Instruction Orders for Processor Design Verification and Validation 03-12-2009
27. 20090070629 System and Method for Testing Multiple Processor Modes for Processor Design Verification and Validation 03-12-2009
28. 20090070570 System and Method for Efficiently Handling Interrupts 03-12-2009
29. 20090070546 System and Method for Generating Fast Instruction and Data Interrupts for Processor Design Verification and Validation 03-12-2009
30. 20090070532 System and Method for Efficiently Testing Cache Congruence Classes During Processor Design Verification and Validation 03-12-2009
31. 20090049178 SYSTEM AND METHOD FOR MINIMIZING RETRY DELAYS IN HIGH TRAFFIC COMPUTER NETWORKS 02-19-2009
32. 20090043997 Time-Of-Life Counter For Handling Instruction Flushes From A Queue 02-12-2009
33. 20090024894 SYSTEM AND METHOD FOR PREDICTING IWARX AND STWCX INSTRUCTIONS IN TEST PATTERN GENERATION AND SIMULATION FOR PROCESSOR DESIGN VERIFICATION/VALIDATION IN INTERRUPT MODE 01-22-2009
34. 20090024892 System and Method of Testing using Test Pattern Re-Execution in Varying Timing Scenarios for Processor Design Verification and Validation 01-22-2009
35. 20090024891 System and Method for Pseudo-Random Test Pattern Memory Allocation for Processor Design Verification and Validation 01-22-2009
36. 20090024886 System and Method for Predicting lwarx and stwcx Instructions in Test Pattern Generation and Simulation for Processor Design Verification and Validation 01-22-2009
37. 20090024877 System and Method for Creating Different Start Cache and Bus States Using Multiple Test Patterns for Processor Design Verification and Validation 01-22-2009
38. 20090024876 System and Method for Verification of Cache Snoop Logic and Coherency Between Instruction & Data Caches for Processor Design Verification and Validation 01-22-2009
39. 20090024873 System and Method for Increasing Error Checking Performance by Calculating CRC Calculations After Multiple Test Patterns for Processor Design Verification and Validation 01-22-2009
40. 20090019255 System and Method for Cache-Locking Mechanism Using Segment Table Attributes for Replacement Class ID Determination 01-15-2009
41. 20090019252 System and Method for Cache-Locking Mechanism Using Translation Table Attributes for Replacement Class ID Determination 01-15-2009
42. 20090007249 SYSTEM AND METHOD FOR SELECTIVE AUTHENTICATION WHEN ACQUIRING A ROLE 01-01-2009
43. 20080313727 Dynamic Discovery and Database Password Expiration Management 12-18-2008
44. 20080307441 System and Method for Call Stack Sampling Combined with Node and Instruction Tracing 12-11-2008
45. 20080307402 SIMD Code Generation in the Presence of Optimized Misaligned Data Reorganization 12-11-2008
46. 20080306778 Accessibility Insurance Coverage Management 12-11-2008
47. 20080301695 Managing a Plurality of Processors as Devices 12-04-2008
48. 20080301606 Design Structure for Switching Digital Circuit Clock Net Driver Without Losing Clock Pulses 12-04-2008
49. 20080301500 System and Method for Identifying and Manipulating Logic Analyzer Data from Multiple Clock Domains 12-04-2008
50. 20080300849 Design Structure for Improved Logic Simulation Using a Negative Unknown Boolean State 12-04-2008
51. 20080297506 Ray Tracing with Depth Buffered Display - image is generated that includes ray traced pixel data and rasterized pixel data 12-04-2008
52. 20080295147 Integrated Security Roles - approach to handling integrated security roles is presented 11-27-2008
53. 20080282064 System and Method for Speculative Thread Assist in a Heterogeneous Processing Environment 11-13-2008
54. 20080276232 Processor Dedicated Code Handling in a Multi-Processor Environment 11-06-2008
55. 20080271029 Thread Scheduling with Weak Preemption Policy 10-30-2008
56. 20080271003 Balancing Computational Load Across a Plurality of Processors 10-30-2008
57. 20080263336 Processor Having Efficient Function Estimate Instructions 10-23-2008
58. 20080263091 Asynchronous Linked Data Structure Traversal 10-23-2008
59. 20080256333 SYSTEM AND METHOD FOR IGNORING FETCH PROTECTION 10-16-2008
60. 20080256275 Multi-Chip Module With Third Dimension Interconnect 10-16-2008
61. 20080250414 Dynamically Partitioning Processing Across A Plurality of Heterogeneous Processors 10-09-2008
62. 20080250208 System and Method for Improving the Page Crossing Performance of a Data Prefetcher 10-09-2008
63. 20080235679 Loading Software on a Plurality of Processors 09-25-2008
64. 20080229129 Remote Control Save and Sleep Override - approach is provided that handles a power down signal received by a device 09-18-2008
65. 20080229078 Dynamic Power Management in a Processor Design 09-18-2008
66. 20080222623 Efficient Code Generation Using Loop Peeling for SIMD Loop Code with Multiple Misaligned Statements 09-11-2008
67. 20080222395 System and Method for Predictive Early Allocation of Stores in a Microprocessor 09-11-2008
68. 20080222307 System and Method for Multiple IP Addresses During Domain Name Resolution 09-11-2008
69. 20080222306 System and Method for Accessing Multiple Addresses Per Domain Name Using Networked Repository 09-11-2008
70. 20080215882 Assigning Security Levels to a Shared Component 09-04-2008
71. 20080209127 System and method for efficient implementation of software-managed cache 08-28-2008
72. 20080201699 Efficient Data Reorganization to Satisfy Data Alignment Constraints 08-21-2008
73. 20080201463 Estimating Network Management Bandwidth - Network management bandwidth is estimated 08-21-2008