120Chapter4 • Using GNU make
4.3.1Defining Variables
Variables can be defined in a usual way by typing in the variable name, followed by an
equal sign. The equal sign is followed by the value that is assigned to the variable. Note that
there may be space characters on one or both sides of the equal sign. A typical variable assign-
ment may be as follows:
CFLAGS = -g –O2
Another example of defining the C compiler name is as follows:
CC = gcc
This variable than can be used in other parts of the makefile by placing a
$
sign and a pair
of parenthesis or braces. The following line in a makefile is used to compile a file
tftp.c
and
create an object file
tftp.o
with the help of above two variables;
$(CC) $(CFLAGS) –o tftp.o tftp.c
This line can also be written as follows:
${CC} ${CFLAGS} –o tftp.o tftp.c
4.3.2Types of Variables
There are two types of variables. Variables defined using the = sign are
recursively
expanded variables
. This means that a variable may be expanded depending upon value of a
variable at a later stage in the makefile. Consider the following lines in a makefile.
OBJ1 = ftp.o
OBJ2 = common.o
OBJS = $(OBJ1) $(OBJ2)
printobjs:
@echo $(OBJS)
OBJ1 = ftp.o tftp.o
Variable
OBJS
will contain a list of three files,
ftp.o
,
tftp.o
and
common.o
,
although
tftp.o
was added
after
the
echo
command. Output of this makefile is as follows.
[root@conformix make]# make
ftp.o tftp.o common.o
[root@conformix make]#
This is because
make
used the default target rule and executed the
echo
command.
Before printing out the value of the
OBJS
variable, it scanned the makefile to the end to re-eval-
uate the value of the
OBJ1
variable and hence the
OBJS
variable.
The other types of variables are
simply expanded
variables and the value of these variables
is determined at the time of their definition. These variables are defined using the
:= symbol
N O T E Variables are case sensitive in makefiles. A variable
$(OUTFILES)
is different from a variable
$(OutFiles)
.