REFRESH HARDWARE FOR GDR'S U8820,U8840.SINGLE CHIP MICROCOMPUTERS DESCRIBED

Created: 2/7/1990

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Document Date: ct

ReportDate: eb 90

ReportNumber:

Report Series: ScienceechnologyStart Page:Division: EAST

Report Subdivision: HICROELECTRONICS

City/Source of Document: Bast Berlin RADIO fernsEHEN ELEKTRONIK

Olaf Skeri and Wolfram Schmidt: "Dynamic Memories for Single Chip

Report Name: Europe

Headline: Refresh Hardware foringle Chip Microcomputers Doscribed<eat>

Source Line: ast Berlin RADIO FERNSBKEN ELEKTRONIK in Germanct

Subalug: [Article by Olaf Skerl and Wolfram Schmidt: "Dynamic

Memories for Single Chip0 and

full text of article:

1. [Article by Olaf Skorl and Wolfram Schmidt: "Dynamic Memories for Single Chip0'

[Text] From the Division for Technical Electronics ot the wilhelm Pieck University in Rostock

This articleircuit for the single chip0 which makes it possible to operate these microcomputers in conjunction with dynamic memorlea without taking up time for refresh functions. The circuit also avoids any tlae conflicts between the refresh process and time-sensitive Interrupt operations. The principle used and the refresh hardware circuit will be explained.

single chip microcomputers are frequently used in measuring technology since their Integrated peripheral functionsimple sot up of computero used for measuring purposes. Some applications require larger memory capacities which can be implemented by using DRAMs. However. DRAMo have the disadvantage that the information

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stored has to be refreshed at short intervals.

TheBCardware support for the refresh function. However, th* single chip microcomputers of00 seriesomplicated dram refresh procedure since no refresh function has been implemented and refreshing must therefor* be done via software. During one refresh period ofll memory cells must be refreshedeasthis process take* up at leastercent of th* computing tin* of the single chip microcomputer. In addition, during tin* sensitiv* interrupt operations there may be conflicts between the refresh function and the interrupts. To relieve the single chip microcomputer and. more importantly, to avoid conflicts during interruptimple Circuit was designed which allows th* refreshing of DRAMs using th* control signals of tho single chip microcomputer.

Operating Principle

The DRAMs are refreshed in the background of command call cycles. Thisivision of the singl* chip microcomputer memory space into data and program, the signal /DMust be enabled. Therefore,ommand call the single chip microcomputer accesnes the program segment only. During this time, the data segment can b* accessed simultaneously without affecting tho computer's operation a* long as the data segment is kept separate from th* single chip microcomputer. This principle is used for refreshing the data memory.

Signals /RAS and /CAS which are used to drive the DRAMs are generated by control signals /AS, /DS, /KDS. Since enabling of these control signals is inconsistent in some machine cycles . during the interrupt accept cycle, the LDE commands andhe control signal /SYNC of the single chip microcomputer must b* included in th* refresh logic. The rising edge of /SYNC is always followedegular command call.

For this reason, the memories are always refreshad during the machin* cycle directly following tho /SYNC. there is always *xactly one refresh cycle for each command, with an external clock frequencyHz.olumns are refreshedn an average without using computing tlm* of th* singl* chip

microcomputer.

refresh hardware consists ofit refresh counter,multiplexer to provide the refresh address and awhich generates the required control signals basic circuit shown inses the signals /SYNC andthe single chip mlcroexxaputer it can only be used for the

development, which are the only one* to provide the control signals mentioned.

lock Diagram ofata and Address Lines of the SingleControlemory and Refreshontrol Signals ofChip MicroprocessorGRAPHICS

Description

hows the refresh hardware circuit, he time diagram. DRAM selection follows basically the suggestion givenet>reset>).

GRAPHICSigureefresh Hardware Circuit DiagramD0 to8A0 to

nf>ll<reset>cset>GRAPHICS

GRAPHICSigureime Diagram for Memory Access and Rofresh Cyclesow Order Part PC,p-Code,ow Order Part Memoryata,AS-only-Refrash)p code read,yte command, internalat* Memoryode readGRAPHICS"

When the data memory is accessed, the signal /RAS is generated byfrom the rising edge of /AS.eoet>eset> switch linos ADO to AD7 of the single chip microcomputer--whero the low order address part Is

located at this time--to tha DRAM address inputs. The /CAS signal is generated from control signal /DSelay in the gatesnd the address multiplexers apply the high order address part (A8) to the DRAM address Inputs. Signal /RAS la reset with the rising edge of /DS.

ignal of the single chip microcomputer Is used forread/write control. The runtime performance of these signalsthe DRAMs to function in the early write modehisswitching of the data inputs and outputs of DRAMs

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be able to use the same memory refresh drive circuitrythe internal ROM. the signal /KDS is included in thaUsing the AND operation of control signals /DS and /MDS.signal is generated which performs the Bast* functions asis enabled both when the external memory and the internal ROM[see

Since enabling of /MDS is inconsistent in son* machineh* refresh process is synchronized with /SYNC. Th* /RFSH signal i* enabled during the rising edge of /SYNC and it is disabled again during the subsequent negative edge ofhe AND operation of /DM and /RFSH results in the signal /RASE SRAShe /AS signal can enable the DRAM signal /PAS only when /RASE is active. Thus. /RAS can become enabled only when the single chip microcomputer accobsob the data segment of the memory, or directly following /SYNC. In both cases, regular /Aa-/DS orDS signal sequences are generated which prevent an incorrect memory selection.

Tha DRAM signal /CAS is switched via /DMhe /CAS signalnabled only when the single chip microcomputer accesses th* data segment; in all other instances it remains disabled. ThisAS-only refresh. Following /SYNC, /RAS is enabled and /CAS is disabled (see

With th* negative edge of /RAS,4 accept the address at address inputs AO to A7ine address into the address latch.rit* or read access, this address is the linef the memoryefresh cycle it is th* current refresh addr*ca,

Th* refresh address is generated byit refresh countero make counters critical, th* counter* are not advanced until the DRAMs have acceptod th* refresh addreas during the rising edge of /RFSH. This gives th* counter outputs sufficient time to respond to the new counter status. Thus, each refresh process uses the refresh address of the preceding refresh cycl*.

To Include th* refresh address the tristate outputs of the addresseset> ande*et> and of> are controlled via signals /OEl2 which ara derived from /DM. If /DM is. the data memory i* accessed, the address multiplexers arend the respective memory address reaches the memory address inputs. Driveisf /DM is disabled, driverIs enabled, and the counter passes the refresh address to the DRAMti. During that time, the address multiplexers are disabled, so that the memory can be refreshed (see

Summaiy

The refresh hardwar* described allows the use of dynamic memories in systems with single chip microcomputers without using up their computing time for refresh routines. It also avoid* tIra* conflict* betweenprocesses and interrupt operations. Timing

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was designed so that LS-TTL circuits can be used for the complete drive circuitry with external clock frequencies of uphip typea such asS with access timess ore sufficient for the DRAMsowever, only chip00 can be used as single chip microcomputers since their special control signals /MDS and /SYNC are required for driving the refresh circuit. He did not study the possibility of using this hardware for single chip microcomputer1 DC/1.

Bibliography

e Paly. "Random4- RADIO FERNSEHFN ELECTRONIK, Berlin ii. 7 4, ; 5. pp.

ingle Chiperlin, VE8 Verlag Technlk,

Handbook of TTL and CMOS Circuits.'1 Berlin VEB Vorlag Technlk.

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