Article Abstract:
This paper represents a comparative simulation modeling of the performance of the uniprocessor, single-bus multiprocessor, and two-bus multiprocessor computer systems. The performance indexes of the single-bus and two-bus multiprocessor systems compared to the uniprocessor system, that are used in the modeling, are processor speedup factors S(subscript P1) and S(subscript P2) respectively. A third performance index, Bus-speedup factor, S(subscript B), is derived to compare the performance of the two-bus and single-bus systems. The first two indexes provide measures of the processing speedup improvement of both multiprocessors with respect to the uniprocessor system, while the third index provides a measure of the performance improvement resulting from adding an extra bus to the single-bus multiprocessor system. Three data transfer protocols are considered in this work: First Come First Served (FCFS), Token Ring (TR), and the Priority (PR) policy. Simulation experiments show that increasing the number of processors in the considered multiprocessor architectures does not necessarily improve the overall performance. Moreover, adding an extra bus to the single-bus architecture provides some speedup improvement that depends on the nature of the task program and the data transfer protocol. Simulation results show that FCFS and TR scheduling policies provide better performance than the PR policy. However, FCFS requires relatively less hardware and software complexity than the TR. (Reprinted by permission of the publisher.)
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Article Abstract:
For shared bus multiprocessors operated in multiprogramming mode, the addition of second-level caches tends to significantly increase system performance. Trace-driven simulation was employed to obtain performance measurements over a range of system parameters, with the cache sizes at both levels being the parameters of most interest. For both light and heavy system loading, the addition of second-level caches was found to boost system performance. For heavily loaded multiprocessor cases, the workload-averaged percentage increases in performance ranged from 187% with 32k byte first-level caches to 507% with 4K byte first-level caches when when 128k byte second-level caches were added. The main memory configuration and number of processors largely dictates the performance of a shared bus multiprocessor running in multiprogramming mode. The addition of larger second-level caches to the system results in increased system performance over a range of system configurations and workloads. (Reprinted by permission of the publisher.)
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Article Abstract:
The purpose of this paper is to illustrate the techniques of converting SLAM (Simulation Language for Alternative Modeling) models to Petri Nets and vice versa. Conversion of SLAM models into Petri Nets will allow the modeler to represent complex systems graphically. On the other hand, conversion of Petri Nets into SLAM will result in quick and efficient generation of statistical results with very little programming effort. For demonstration purposes a SLAM model of a simple queuing system has been converted into a PN one and contrasted. A PN model of CPU-IO interaction was converted into SLAM model, where the results obtained using both tools are shown to be identical. (Reprinted with permission of the publisher.)
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